光刻胶灰化技术用于同步辐射闪耀光栅制作

在分析光刻胶光栅浮雕图形缺陷成因的基础上,首次将光刻胶灰化工艺引入到全息－离子束刻蚀制作闪耀光栅工艺中,并成功地为国家同步辐射实验室光化学站制作了１２００１／ｍｍ,闪耀波长为１３０ｎｍ的锯齿槽形光栅。测试结果表明光刻胶灰化处理对制作大面积优质的光刻胶光栅非常有效和实用。     

离子束刻蚀过程中光刻胶收缩行为研究

光刻胶作为离子束刻蚀的掩膜已得到了普遍采用，由于它在受到离子束轰击时会发热收缩、不利于刻蚀线条高宽比的提高，限制了它的进一步使用。在离子束的轰击下，光刻胶的收缩不仅与其发热程度有关，而且与刻蚀线条的宽度也有关，通过改变刻蚀时基片和旋转台之间的热接触状态发现，光刻胶发热越厉害，收缩量越大。而在光刻胶发热程度很小或者不发热时，收缩量极小，可以忽略不计。而在同一发热状态下，不同宽度线条的光刻胶收缩量也不一样，宽度越大，收缩量就越大，宽度越小，收缩量也越小。结果造成在不同宽度线条的接合处，线条边缘出现弯曲。     

O2/SF6混合气体对光刻胶的离子刻蚀研究

以O2＋SF6为刻蚀气体,在一定压力下使用RIE刻蚀机刻蚀光刻胶。通过改变功率、O2流量和SF6流量,研究以上因素的改变对光刻胶灰化速率的影响。实验结果表明：单组分O2存在下,O2流量的增加不会影响光刻胶的灰化速率。设备Plasma功率以及气体比率变化对灰化率有显著影响,并通过光谱分析对光刻胶的灰化反应机理进行了初步研究。     

啁啾光纤光栅相位掩模槽形控制新方法研究

在啁啾光纤光栅相位掩模的制作中,针对光刻胶光栅槽形要求比较高的问题,提出离子束刻蚀和反应离子束刻蚀相结合的方法,来实现对相位掩模槽形占宽比的控制.运用高级线段运动算法模拟分析刻蚀中的图形演化,用Ar离子束刻蚀对光刻胶光栅掩模形貌进行修正,然后采用CHF3反应离子束刻蚀,实验和模拟均表明,Ar离子束刻蚀能很好的改善掩模与基片交界处的基片侧壁形貌,使得在CHF3反应离子束刻蚀下能得到较小的占宽比.对槽形控制提供了有意义的实验手段.     

Ar/CHF_3反应离子束刻蚀SiO_2的研究

介绍了Ar/CHF3反应离子束刻蚀和离子束入射角对图形侧壁陡直度及刻蚀选择比的影响。使用紫外曝光技术在SiO2基片上获得光刻胶掩模图形,采用Ar CHF3来刻蚀石英基片,调节二者的流量配比,混合后通入离子源。在Ar和CHF3的流量比为1∶2,总压强为2×10-2Pa,离子束流能量为450 eV,束流为80 mA,加速电压220 V~240 V,离子束入射角15°并旋转样品台的情况下,刻蚀20 min后,得到光栅剖面倾角陡直度为80°~90°。同时发现,添加CHF3后,提高了SiO2的刻蚀速率和刻蚀SiO2与光刻胶的选择比,最高可达7∶1。     

Ar/CHF3反应离子束刻蚀SiO2的研究

介绍了Ar/CHF3反应离子束刻蚀和离子束入射角对图形侧壁陡直度及刻蚀选择比的影响.使用紫外曝光技术在SiO2基片上获得光刻胶掩模图形,采用Ar+CHF3来刻蚀石英基片,调节二者的流量配比,混合后通入离子源.在Ar和CHF3的流量比为12,总压强为2×10-2 Pa,离子束流能量为450 eV,束流为80 mA,加速电压220 V～240 V,离子束入射角15°并旋转样品台的情况下,刻蚀20 min后,得到光栅剖面倾角陡直度为80°～90°.同时发现,添加CHF3后,提高了SiO2的刻蚀速率和刻蚀SiO2与光刻胶的选择比,最高可达71.     

离心旋转喷雾式清洗技术

应用．前段光刻胶去除和灰化后清洗．自对准多晶硅化物去除．后段灰化后清洗．凸块制程中．晶圆回收     

软X射线偏折仪用自支撑莫尔光栅研制

介绍了莫尔光栅制作的主要方法和进展。利用紫外光刻、离子束刻蚀技术制作自支撑金莫尔光栅，讨论了金膜厚度要求、电镀金膜质量和光栅占空比控制等影响莫尔光栅质量的关键技术问题。实验结果表明，通过设计较小占空比的光栅掩模、紫外光刻时擦除基片边缘的光刻胶棱以消除衍射效应、离子束刻蚀时基片倾斜一定的角度旋转刻蚀等措施可以改善自支撑金莫尔光栅的占空比。     

一种制作亚微米线条的有效方法

本文介绍利用普通接触式曝光系统和等离子刻蚀机来制作亚微米线条。基本工艺是用深紫外线作为光源，对曝光后的光刻胶在ＨＭＤＳ或ＴＭＤＳ气氛下加热处理，然后采用氧反应离子刻蚀，结果可得到０．７微米的光刻胶线条，其端面完整、侧壁陡直，非常适合于大规模集成电路制造中的剥离工艺。     

基于光刻胶热熔法的全息光栅表面粗糙度平滑处理

根据表面热动力学原理提出了一种成本低廉、制作周期短、易于实现的光刻胶热熔法,阐述了光刻胶热熔法的基本原理,探讨了光刻胶热熔对光刻胶光栅表面刻槽形状的影响。实验中,分别对经过和未经过热熔处理的光刻胶光栅做了离子束刻蚀。结果表明,利用表面张力作用可使熔融状态下的光刻胶光栅刻槽表面变得平滑,粗糙度降低,并且成功地在K9玻璃基底上得到了槽形较好的全息光栅。     

后段工艺干法去除光刻胶研究

干法去胶是用等离子体将光刻胶剥除,相对于湿法去胶,干法去胶的效果更好、速度更快.在现代集成电路制造中,干法去胶工艺加氟可有效地提高去除光刻胶的能力,特别是在离子注入之后的去胶工艺,含氟气体产生的氟离子可以防止光刻胶硬化.但在后段干法去胶工艺中,由于含氟气体的引入,会产生一系列的问题.因此,文中提出了对去胶气体组合配比进...     

各膜层对光刻胶灰化的影响

研究各膜层对灰化速率的影响,增强对灰化工艺的了解,为四次光刻工艺改善提供参考。采用探针台阶仪测量在相同灰化条件下不同膜层样品的灰化速率和有源层损失量,对结果进行机理分析和讨论。实验结果表明:有源层会降低灰化速率,源/漏金属层可以增大灰化速率,栅极金属层对灰化速率无影响。对于正常膜层结构的阵列基板,源/漏层图形密度越大,灰化速率越小,图形密度每增大1%,灰化速率下降14nm/min。有源层和源/漏金属层对灰化等离子体产生影响,从而影响灰化速率。     

Fabrication of Silicon Microlens Arrays Using Ion Beam Milling

A spherical mask for the fabrication of microlens arrays was prepared by melt-ing photoresist,and the spherical photoresist shape was transferred into a silicon substrate using ion beam milling.The ion beam milling process was computer simulated using the Sig-mund ion beam sputtering theory of collision cascades.The experiment results show that mi-crolens arrays can be effectively formed at low substrate temperature of less than 200℃，Shapes and dimensions of photoesist masks and silicon microlens arrays were examined by the scanning electron microscope and tested by the surface stylus measurement.     

On-line diagnostic monitoring of photoresist ashing

On-line statistical process control (SPC) has been implemented on a single-wafer remote microwave plasma photoresist asher. SPC for ashing is made more difficult because the prior processes, e.g., ion implantation, affect the properties of the resist material, and consequently the ashing behavior. The system presented comprehends the variety of incoming wafer states from a complex process flow. On-line SPC charts track photoresist clear time on a wafer-to-wafer basis using optical emission spectroscopy. The data is corrected for the “first-wafer” effect, whereby the clear time for a wafer decreases as the delay time between ashing wafers increases. The data is standardized using an expected time and variance for each process flow level to allow all results to be presented in a single set of individuals and moving-standard deviation Shewhart charts. Standard SPC rules are applied automatically within each process flow level to test for unnatural variation in the data. Observed abnormal behavior is due mainly to changes in the incoming material for a specific process flow level, not deviations in the ashing process. When a shift in incoming wafer state is detected, the expected response for that process level is automatically updated to reflect the change. The usefulness of on-line monitoring as a means for identifying misprocessing at prior process steps has been demonstrated, Early diagnosis can save money by avoiding expensive downstream processing on previously misprocessed wafers, In our demonstration laboratory, the equipment has processed wafers from a dozen process flow levels     

Removal of post-etch photoresist and sidewall residues using organic solvent and additive combined with physical forces

The effect of tetramethyl ammonium hydroxide (TMAH) used as additive in organic solvent (N-methyl pyrrolidone, NMP) on removal efficiency of post-etch photoresist was investigated on both blanket substrate and single damascene structures. In contrast to plasma ashing, photoresist removal using NMP/TMAH combined with megasonics showed no carbon depletion and no significant change in k-value. Mixing TMAH with NMP enhanced photoresist removal efficiency with respect to pure NMP. Photoresist removal using NMP/TMAH resulted in lower low-k capacitance (lower k-value) compared with that of plasma ashing process, due to the removal of the damaged layer generated during plasma etching. As a consequence of the removal of the damaged layer, a CD change was observed. The CD loss was estimated to be about 7 nm for 1% TMAH, and became negligible for 0.1% TMAH. Analysis of low-k sidewall using angle-resolved X-ray photoelectron spectroscopy showed that solvent mixture containing TMAH also removed sidewall residues generated by the etch plasma.     

Resist-related damage on ultrathin gate oxide during plasma ashing

This paper presents an important observation of plasma-induced damage on ultrathin oxides during O₂ plasma ashing by metal “antenna” structures with photoresist on top of the electrodes. It is found that for MOS capacitors without overlying photoresist during plasma ashing, only minor damage occurs on thin oxides, even for oxide thickness down to 4.2 nm and an area ratio as large as 10⁴. In contrast, oxides thinner than 6 nm with resist overlayer suffer significant degradation from plasma charging. This phenomenon is contrary to most previous reports. It suggests that the presence of photoresist will substantially affect the plasma charging during ashing process, especially for devices with ultrathin gate oxides