Self-biased cross-coupled low-cost fully-differential CMOS operational amplifier

A low-cost fully-differential operational amplifier (opamp) using a novel self-biased cascode output stage and cross-coupled input stage is proposed. Fabricated in only an 84/spl times/67 /spl mu/m/sup 2/ area with TSMC 0.35 /spl mu/m technology, and loaded with more than 100 pF capacitance, the opamp possesses 60 dB DC gain, 3 V//spl mu/s slew rate, 7.8 MHz unity-gain bandwidth, and -48 dB total harmonic distortion.     

Low-voltage high performance compact all cascode CMOS current mirror

A high performance and compact current mirror with extremely low input and high output resistances (R/sub in//spl sim/0.01/spl Omega/, R/sub out//spl sim/10 G/spl Omega/), high copying accuracy, very low input and output voltage requirements (V/sub in/, V/sub out//spl ges/V/sub DSsat/), high bandwidth (200 MHz using a 0.5 /spl mu/m CMOS technology) and low settling time (25 ns) is proposed. Simulations and experimental results are shown that validate the circuit.     

A low-noise high-precision operational amplifier

A low-noise high-precision operational amplifier has recently been fabricated in monolithic form with dielectric isolation. The amplifier exhibits a V/SUB OS/ of 10 /spl mu/V, V/SUB OS/T/SUB c/ of 0.3 /spl mu/V//spl deg/C, voltage gain of 140 dB with a 600 /spl Omega/ load, and an input noise voltage of 9 nV//spl radic/Hz. The settling time to within 0.01 percent of final value is 15 /spl mu/s for a 10 V pulse.     

A high-voltage monolithic operational amplifier

An operational amplifier capable of operating with power supplies up to /spl plusmn/40 V is discussed. The device exhibits output voltage and input common mode swings to within a few volts of either power supply, has an input offset current of 1 nA, a slew rate of 2 V//spl mu/s, and is internally compensated. This paper describes special circuit and device techniques used to reliably fabricated this amplifier with essentially standard monolithic diffused technology.     

A low input capacitance voltage follower in a compatible silicon-gate MOS-bipolar technology

Using a compatible silicon-gate p-MOS-bipolar technology (SIGBIP), a voltage follower is described with protected MOSFET input stage featuring less than 1-pA input current, less than 0.1-pF input capacitance, 10-MHz bandwidth, 20-/spl mu/V p-t-p noise from 1 Hz to 100 kHz. Offset drift is less than 30 /spl mu/V//spl deg/C. The circuit is based on a new very high-gain differential stage which allows full bootstrapping of all its input capacitances. The circuit measures only 0.9 mm/SUP 2/ and is mounted in a 4-pin TO-18 package. The circuit can successfully be used for charge measurements, and especially for wide-band measurements from very high impedance sources (>10 M/spl Omega/) as occurring in bioelectronics, biochemistry, etc.     

A CMOS chopper amplifier

A highly sensitive CMOS chopper amplifier for low-frequency applications is described. It is realized with a second-order low-pass selective amplifier using a continuous-time filtering technique. The circuit has been integrated in a 3-/spl mu/m p-well CMOS technology. The chopper amplifier DC grain is 38 dB with a 200-Hz bandwidth. The equivalent input noise is 63 nV//spl radic/Hz and free from 1/f noise. The input offset is below 5 /spl mu/V for a tuning error less than 1%. The amplifier consumes only 34 /spl mu/W.     

A CMOS analog front-end IC for portable EEG/ECG monitoring applications

A new digital programmable CMOS analog front-end (AFE) IC for measuring electroencephalograph or electrocardiogram signals in a portable instrumentation design approach is presented. This includes a new high-performance rail-to-rail instrumentation amplifier (IA) dedicated to the low-power AFE IC. The measurement results have shown that the proposed biomedical AFE IC, with a die size of 4.81 mm/sup 2/, achieves a maximum stable ac gain of 10 000 V/V, input-referred noise of 0.86 /spl mu/ V/sub rms/ (0.3 Hz-150 Hz), common-mode rejection ratio of at least 115 dB (0-1 kHz), input-referred dc offset of less than 60 /spl mu/V, input common mode range from -1.5 V to 1.3 V, and current drain of 485 /spl mu/A (excluding the power dissipation of external clock oscillator) at a /spl plusmn/1.5-V supply using a standard 0.5-/spl mu/m CMOS process technology.     

High-performance RF mixer and operational amplifier BiCMOS circuits using parasitic vertical bipolar transistor in CMOS technology

The electrical characteristics of the parasitic vertical NPN (V-NPN) BJT available in deep n-well 0.18-/spl mu/m CMOS technology are presented. It has about 20 of current gain, 7 V of collector-emitter breakdown voltage, 20 V of collector-base breakdown voltage, 40 V of Early voltage, about 2 GHz of cutoff frequency, and about 4 GHz of maximum oscillation frequency at room temperature. The corner frequency of 1/f noise is lower than 4 kHz at 0.5 mA of collector current. The double-balanced RF mixer using V-NPN shows almost free 1/f noise as well as an order of magnitude smaller dc offset compared with CMOS circuit and 12 dB flat gain almost up to the cutoff frequency. The V-NPN operational amplifier for baseband analog circuits has higher voltage gain and better input noise and input offset performance than the CMOS ones at the identical current. These circuits using V-NPN provide the possibility of high-performance direct conversion receiver implementation in CMOS technology.     

A monolithic junction FET-n-p-n operational amplifier

A monolithic operational amplifier with junction FET inputs in combination with n-p-n bipolar transistors is described. Both dc and small signal analysis of the amplifier are carried out. Electrically the devices are comparable with discrete state-of-the- art p-channel FET's. The circuits are fabricated with a process requiring a single diffusion more than standard techniques. The process is reproducible enough to allow economical fabrication. The amplifier realizes input currents of less than 1 nA, a minimum slewing rate at unity gain of 75 V//spl mu/s and bandwidths in excess of that of any monolithic operational amplifier reported to date.     

A quad CMOS single-supply op amp with rail-to-rail output swing

The realization of a commercially viable, general-purpose quad CMOS amplifier is presented, along with discussions of the tradeoffs involved in such a design. The amplifier features an output swing that extends to either supply rail, together with an input common-mode range that includes ground. The device is especially well suited for single-supply operation and is fully specified for operation from 5 to 15 V over a temperature range of -55 to +125/spl deg/C. In the areas of input offset voltage, offset voltage drift, input noise voltage, voltage gain, and load driving capability, this implementation offers performance that equals or exceeds that of popular general-purpose quads or bipolar of Bi-FET construction. On a 5-V supply the typical V/SUB os/ is 1 Mv, V/SUB os/ drift is 1.3 /spl mu/V//spl deg/C, 1-kHz noise is 36 nV//spl radic/Hz, and gain is one million into a 600-/spl Omega/ load. This device achieves its performance through circuit design and layout techniques as opposed to special analog CMOS processing, thus lending itself to use on system chips built with digital CMOS technology.     

A low-voltage micropower JFET/bipolar operational amplifier

A single cell supply (operable down to 1.2 V) micropower operational amplifier using compatible low pinchoff voltage JFET's (V/SUB p/=0.4 V) in conjunction with standard bipolar technology has been developed. The subvolt pinchoff JFET's have proved useful in the common-mode feedback-assisted biasing of a simple p-n-p input stage to permit single supply operation, the design of a low-voltage high-performance current mirror and a differential to single-ended converter. The amplifier exhibits excellent ac performance (unity gain slew rate=0.25 V//spl mu/s, unity gain bandwidth=850 kHz) with low power dissipation (245 /spl mu/W).     

Cryogenic capacitive transimpedance amplifier for astronomical infrared detectors

We have developed a new capacitive transimpedance amplifier (CTIA) that can be operated at 2 K, and have good performance as readout circuits of astronomical far-infrared array detectors. The circuit design of the present CTIA consists of silicon p-MOSFETs and other passive elements. The process is a standard Bi-CMOS process with 0.5 /spl mu/m design rule. The open-loop gain of the CTIA is more than 300, resulting in good integration performance. The output voltage swing of the CTIA was 270 mV. The power consumption for each CTIA is less than 10 /spl mu/W. The noise at the output showed a 1/f noise spectrum of 4 /spl mu/V//spl radic/Hz at 1 Hz. The performance of this CTIA nearly fulfills the requirements for the far-infrared array detectors onboard ASTRO-F, Japanese infrared astronomical satellite to be launched in 2005.     

SODEL FET: novel channel and source/drain profile engineering schemes by selective Si epitaxial growth technology

In this paper, novel channel and source/drain profile engineering schemes are proposed for sub-50-nm bulk CMOS applications. This device, referred to as the silicon-on-depletion layer FET (SODEL FET), has the depletion layer beneath the channel region, which works as an insulator like a buried oxide in a silicon-on-insulator MOSFET. Thanks to this channel structure, junction capacitance (C/sub j/) has been reduced in SODEL FET, i.e., C/sub j/ (area) was /spl sim/0.73 fF//spl mu/m/sup 2/ both in SODEL nFET and pFET at Vbias =0.0 V. The body effect coefficient /spl gamma/ is also reduced to less than 0.02 V/sup 1/2/. Nevertheless, current drives of 886 /spl mu/A//spl mu/m (I/sub off/=15 nA//spl mu/m) in nFET and -320 /spl mu/A//spl mu/m (I/sub off/=10 nA//spl mu/m) in pFET have been achieved in 70-nm gate length SODEL CMOS with |V/sub dd/|=1.2 V. New circuit design schemes are also proposed for high-performance and low-power CMOS applications using the combination of SODEL FETs and bulk FETs on the same chip for 90-nm-node generation and beyond.     

High-performance double-recessed enhancement-mode metamorphic HEMTs on 4-in GaAs substrates

Enhancement-mode InAlAs/InGaAs/GaAs metamorphic HEMTs with a composite InGaAs channel and double-recessed 0.15-/spl mu/m gate length are presented. Epilayers with a room-temperature mobility of 10 000 cm/sup 2//V-s and a sheet charge of 3.5/spl times/10/sup 12/cm/sup -2/ are grown using molecular beam epitaxy on 4-in GaAs substrates. Fully selective double-recess and buried Pt-gate processes are employed to realize uniform and true enhancement-mode operation. Excellent dc and RF characteristics are achieved with threshold voltage, maximum drain current, extrinsic transconductance, and cutoff frequency of 0.3 V, 500 mA/mm, 850 mS/mm, and 128 GHz, respectively, as measured on 100-/spl mu/m gate width devices. The load pull measurements of 300-/spl mu/m gate width devices at 35 GHz yielded a 1-dB compression point output power density of 580 mW/mm, gain of 7.2 dB, and a power-added efficiency of 44% at 5 V of drain bias.     

Micro-power low-offset instrumentation amplifier IC design for biomedical system applications

This work presents a micro-power low-offset CMOS instrumentation amplifier integrated circuit with a large operating range for biomedical system applications. The equivalent input offset voltage is improved using a new circuit technique of offset cancellation that involves a two-phase clocking scheme with a frequency of 20 kHz. Channel charge injection is cancelled by the symmetrical circuit topology. With the wide-swing cascode bias circuit design, this amplifier realizes a very high power-supply rejection ratio (PSRR), and can be operated at single supply voltage in the range between 2.5-7.5 V. It was fabricated using 0.5-/spl mu/m double-poly double-metal n-well CMOS technology, and occupies a die area of 0.2 mm/sup 2/. This amplifier achieves a 160-/spl mu/V typical input offset voltage, 0.05% gain linearity, greater than 102-dB PSRR, an input-referred rms noise voltage of 45 /spl mu/V, and a current consumption of 61 /spl mu/A at a low supply voltage of 2.5 V. Experimental results indicate that the proposed amplifier can process the input electrocardiogram signal of a patient monitoring system and other portable biomedical devices.     

Amplifier techniques for combining low noise, precision, and high-speed performance

A monolithic operational amplifier is presented which optimizes voltage noise both in the audio frequency band, and in the low frequency instrumentation range. In addition, the design demonstrates that the requirements for low noise do not necessitate compromising the specifications in other respects. Techniques are set forth for combining low noise with high-speed and precision performance for the first time in a monolithic amplifier. Achieved results are: 3 nV//spl radic/Hz white noise, 80 nV/SUB p-p/ noise from 0.1 to 10 Hz, 17 V//spl mu/s slew rate, 63 MHz gain-bandwidth product, 10 /spl mu/V offset voltage, 0.2 /spl mu/V//spl deg/C drift with temperature, 0.2 /spl mu/V/month drift with time, and a voltage gain of two million.     

A low-power 22-bit incremental ADC

This paper describes a low-power 22-bit incremental ADC, including an on-chip digital filter and a low-noise/low-drift oscillator, realized in a 0.6-/spl mu/m CMOS process. It incorporates a novel offset-cancellation scheme based on fractal sequences, a novel high-accuracy gain control circuit, and a novel reduced-complexity realization for the on-chip sinc filter. The measured output noise was 0.25 ppm (2.5 /spl mu/V/sub RMS/), the DC offset 2 /spl mu/V, the gain error 2 ppm, and the INL 4 ppm. The chip operates with a single 2.7-5 V supply, and draws only 120 /spl mu/A current during conversion.     

High slew rate monolithic operational amplifier using compatible complementary P-N-P's

An internally compensated monolithic operational amplifier, fabricated using only junction-isolated bipolar processing, slews in excess of 500 V//spl mu/s, and settles to within 0.1 percent in 200 ns as a pulse inverter. Performance in the noninverting mode is only slightly degraded in comparison with the inverting mode. In addition, the following performance levels have been achieved: 50-MHz unity-gain bandwidth with 96-dB open-loop gain, 30-mW quiescent power at /spl plusmn/3 V, /spl plusmn/50-mA output current capability, and output voltage to within 0.5 V of either supply. In order to achieve the above performance, the following innovations were made: 1) a process for junction-isolated compatible complementary p-n-p transistors with low collector series resistance, 2) a high-speed class-B output stage, 3) push-pull middle stages, 4) driven internal reference voltages locked to the noninverting input, and 5) very small voltage drops across large internal shaping capacitors which permit use of high-capacitance junctions.     

A realization of a below-1-V operational and 30-MS/s sample-and-hold IC with a 56-dB signal-to-noise ratio by applying the current-based circuit approach

This paper demonstrates the low-voltage and low-power operation of a MOS sample-and-hold circuit while preserving speed and accuracy, aiming at the realization of a pipelined low-voltage and low-power analog-to-digital converter on a system large-scale integrated circuit. It was fabricated by utilizing 0.35-/spl mu/m CMOS technology. The main feature of this circuit is that all the input, signals, and output are in the current form. The circuit consists of simple current mirrors. In order to eliminate the signal-dependent current transfer ratio error, voltages at the drain terminals of mirror transistors are fixed as constant. A source degeneration resistor, which is a transistor in the triode operational region, is connected to a mirror transistor in order to alleviate the influence of the threshold and transconductance parameter variations. Control signals are boosted in voltage and applied to the gate of switch NMOS transistors in the signal path in order to reduce the on-resistance of analog switches. A differential configuration is adopted throughout the entire circuit and effectively cancels switch feedthrough errors. As a result, a 30-MS/s operation with a signal-to-noise ratio (SNR) of 56 dB from a 1-V supply has been achieved, when the input current is /spl plusmn/200 /spl mu/A. The chip even operated down to 0.85 V with a 20-MHz clock. The SNR was measured as 50 dB with an input current of /spl plusmn/100 /spl mu/A.     

A monolithic conditioner for thermocouple signals

The authors discusses a monolithic signal conditioner for direct thermocouple input which provides gain, common-mode signal rejection, and cold-junction compensation. It provides 50 to 1 ambient temperature rejection and a nominal 10 mV//spl deg/C output range. It operates on as little as 800 /spl mu/W, provides a thermocouple fault alarm and has provision for use as a set-point feedback controller as well as for signal measurements. The circuit is fabricated on a standard linear IC process and uses laser-wafer-trimmed thin-film resistors to achieve 1/spl deg/C temperature calibration.