基于Electronics Workbench的逻辑电路设计

针对加快电子电路的设计,缩短电子产品的生存周期,提高逻辑判断分析能力及电子设计效率.采用基于EWB仿真软件,结合74191的逻辑功能特点,设计了四位同步二进制可逆计数器.通过EWB仿真软件,从数字逻辑信号分析仪输出的波形来看,实现了对输入脉冲信号进行计数的功能.理论设计方案预期与仿真实验结果基本一致.     

一种基于多值RRAM的快速逻辑电路

针对移动物联网设备,提出一种基于多值RRAM的快速逻辑电路,以实现非易失性存储与快速逻辑运算。利用RRAM多值存储特性,采用Crossbar结构,实现了简单快速的译码器与高存储密度查找表,使逻辑电路具有较快的运算速度和较小的面积。基于该结构实现了4位、8位和16位的乘法器,其外围电路采用SMIC 65 nm CMOS工艺实现,而其核心多值RRAM则采用Verilog-A 模型模拟。仿真结果表明,与传统CMOS逻辑电路相比,基于多值RRAM的16位乘法器的速度提高了35.7%,面积减少了14%。     

A byte organized NMOS/CCD memory with dynamic refresh logic

A 9216 bit NMOS/CCD memory organized as 1024 words by 9 bits is described. It employs a buried channel two phase charge-coupled device (CCD) storage cell combined with n-channel silicon gate Isoplanar (TM) MOS technology for logic functions and TTL compatible interfacing. Techniques of charge detection by using internally generated reference voltages are detailed. A low noise CCD input writing scheme and a dynamic sense-refresh cell are described. Input-output logic is given that permits operating modes of read, write, read-modify-write, and recirculate. Operation at the specification limits of 100 kHz and 2 MHz is shown.     

A byte organized NMOS/CCD memory with dynamic refresh logic

A 9216 bit NMOS/CCD memory organized as 1024 words by 9 bits is described. It employs a buried channel two phase charge-coupled device (CCD) storage cell combined with n-channel silicon gate Isoplanar (TM) MOS technology for logic functions and TTL compatible interfacing. Techniques of charge detection by using internally generated reference voltages are detailed. A low noise CCD input writing scheme and a dynamic sense-refresh cell are descried. Input-output logic is given that permits operating modes of read, write, read-modify-write, and recirculate. Operation at the specification limits of 100 kHz and 2 MHz is shown.     

100 GHz Binary counter based on DC SQUID's

A binary counter using bistable dc SQUID's as flip flop circuits is demonstrated. All of the functions: LOAD, COUNT, STORE, READ, and CLEAR can be performed. The use of single flux quantum logic results in high sensitivity (10^-18J input pulse energy), high speed (100 GHz count rate) and low power (10^-7W at 100 GHz count rate).     

A monolithic charge-balancing successive approximation A/D technique

A new multiple-differential-voltage input, MOS, sampled-data, `charge-balance' comparator which can `weight' or scale each of many input voltage pairs has been developed. This comparator easily allows a differential analog input voltage capability on a monolithic A/D converter and greatly reduces the required number of resistors and decoding switches of a potentiometric successive approximation register (SAR) A/D design. An 8 bit converter has been built which uses 20 Rs and 32 switches as compared to the 256 Rs and 512 switches of a standard 2/SUP N/R ladder design. Measurements made on the 8 bit A/D converter are reported and indicate that at least 12 bit converters are possible with this technique. Therefore, a 13 bit converter has been designed which exhibits even greater component reductions-33 Rs and 64 switches instead of 8192 Rs and 16384 switches. A simple interface to microprocessors is provided for both converters which makes use of the standard logic signals of the control bus where the A/D is designed to appear as memory or an I/O port to the microprocessor. A new flexible reference voltage circuit is presented which, in combination with the analog differential input voltage feature, can accommodate arbitrary analog input voltage spans with any desired zero scale offset.     

Computer-aided design of an eight bit binary counter N-MOS chip for large scale integration (LSI)

An integrated eight bit synchronous binary counter along with input/output circuits: gate protection, two phase clock, pad-out has been designed for MOS LSI. The counter has a master-slave flip-flop and a combinational logic to generate the next state, and outgoing carry outputs from this stage. The combination logic has been implemented using pass transistors and thus acts as a steering type logic. This type of logic is very fast, consumes lesser power and needs significantly less area for its implementation.Latest CAD techniques: interactive Graphics system of Applicon AGS/860 LSI Design Station, MOS circuit simulation program MSINC and Design Rule Check (DRC) program have been used for design and chip layout. The entire chip has been laid out in the area of 3 × 3 mm² including test devices and structures for testability analysis. The design is based on LOCOS N-MOS (E-D) technology and 8 micron design rules. The Electromask pattern generation (PG) tape has been prepared from Applicon for making chrome masks.A set of six masks have been used for the fabrication of device and die encapsulated in dual-in line package and tested for its performance. Counter works up to 5 MHz clock frequency as expected from design calculations. From 25 stage ring oscillator frequency measurement the gate delay comes out to be 6 nS.The counter design could easily be substituted as a sub-system/building block or cell in any MOS LSI system design where it makes a part of it.     

Gambling for the mnemonically impaired

We obtain asymptotically tight bounds on the maximum amount of information that a single bit of memory can retain about the entire past. At each of n successive epochs, a single fair bit is generated and a one-bit memory is updated according to a family of memory update rules (possibly probabilistic and time-dependent) depending only on the value of the new input bit and on the current state of the memory. The problem is to estimate the supremum over all possible update rules of the minimum mutual information between the state of the memory at time (n + 1) and each of the previous n input bits. We show that this supremum is asymptotically equal to 1/(2n² ln 2) bit, as conjectured by Venkatesh and Franklin (1991). We use this result to derive asymptotically sharp estimates of related maximin correlations between the memory and the input bits, thus resolving two more questions left open by Venkatesh and Franklin and by Komlos et al. (1993). Finally, we generalize the results to the case of an m-bit memory, again obtaining asymptotically tight bounds in many cases     

可控量子计数器的构造

本文构造了可控量子计数器,当控制位为“0”时所有输入位原样输出,而当控制位为“1”时输出输入进一位,该模型在应用上可为量子计算机提供具有通用性和可扩展性的计数和存储单元。     

非可逆逻辑门的量子可逆实现研究

逻辑关系可用逻辑函数表示,量子逻辑关系是可逆的,引入和定义了量子逻辑函数;通过引入辅助量子位,增添量子输出信号的区分位,完成对非可逆逻辑门的改造,使非可逆逻辑门在量子电路中得到可逆实现,并研究了一些有用的非可逆逻辑门的改造方法,给出可实现的优化后的量子电路。     

硅光学双稳态(SOB)器件

利用作者近期研制的硅光电表面负阻晶体管（PNEGIT）或光电“∧”双极晶体管（PLBT）两种硅光电负阻器件,提出并成功地实现了一种新型的硅光学双稳态器件。即以PNEGIT（或PLBT）作为光的输入器件,以其驱动一发光管（LED）作为光输出器件,由于PNEGIT和PLBT都具有光电负阻特性,致使在输出光功率（Pout）-输入光功率（Pin）特性上出现逆时针方向的光学双稳回线。这种器件具有光开关、光逻辑、光放大、光存贮、光眼福等多种功能,扩展了硅光电器件在光逻辑、光计算、光通讯等领域中的应用。     

A compact high-speed (31,5) parallel counter circuit based oncapacitive threshold-logic gates

A novel high-speed circuit implementation of the (31,5)-parallel counter (i.e., population counter) based on capacitive threshold logic (CTL) is presented. The circuit consists of 20 threshold logic gates arranged in two stages, i.e., the parallel counter described here has an effective logic depth of two. The charge-based CTL gates are essentially dynamic circuits which require a periodic refresh or precharge cycle, but unlike conventional dynamic CMOS gates, the circuit can be operated in synchronous as well as in asynchronous mode. The counter circuit is implemented using conventional 1.2 μm double-poly CMOS technology, and it occupies a silicon area of about 0.08 mm². Extensive post-layout simulations indicate that the circuit has a typical input-to-output propagation delay of less than 3 ns, and the test circuit is shown to operate reliably when consecutive 31-b input vectors are applied at a rate of up to 16 Mvectors/s. With its demonstrated data processing capability of about 500 Mb/s, the CTL-based (31,5) parallel counter offers a number of application possibilities, e.g., in high-speed parallel multiplier arrays and data encoding circuits     

Logic operations in memory using a memristive Akers array

In-memory computation is one of the most promising features of memristive memory arrays. In this paper, we propose an array architecture that supports in-memory computation based on a logic array first proposed in 1972 by Sheldon Akers. The Akers logic array satisfies this objective since this array can realize any Boolean function, including bit sorting. We present a hardware version of a modified Akers logic array, where the values stored within the array serve as primary inputs. The proposed logic array uses memristors, which are nonvolatile memory devices with noteworthy properties. An Akers logic array with memristors combines memory and logic operations, where the same array stores data and performs computation. This combination opens opportunities for novel non-von Neumann computer architectures, while reducing power and enhancing memory bandwidth.     

单电子存储器

介绍了单电子存储器的发展情况和几种单电子存储器的基本特性,并将库仑阻塞效应作为存储器工作的理论基础进行了讨论。随着传统存储器集成度的不断提高,每个存储单元的电子数目不断减少,并逐渐接近其极限,使传统存储器的发展面临困难。采用单电子存储器有望解决这个困难,它们通常具有单个量子点或者是多隧穿结结构,存储一个比特的信息只需要精确控制增加或者减少一定数目的电子就可以实现。单电子器件的工作通常只需要很少的电子甚至一个电子就可以实现,具有高速和低功耗的特点,因此可以实现信息超高密度存储。与单电子逻辑电路相比,单电子存储器更容易解决随机背景电荷涨落的问题,因此从实际应用的角度来看,单电子存储器的应用前景更为光明。     

Efficient reversible NOR gates and their mapping in optical computing domain

Reversible logic is a computing paradigm in which there is a one to one mapping between the input and the output vectors. Reversible logic gates are implemented in an optical domain as it provides high speed and low energy computations. In the existing literature there are two types of optical mapping of reversible logic gates: (i) based on a semiconductor optical amplifier (SOA) using a Mach–Zehnder interferometer (MZI) switch; (ii) based on linear optical quantum computation (LOQC) using linear optical quantum logic gates. In reversible computing, the NAND logic based reversible gates and design methodologies based on them are widely popular. The NOR logic based reversible gates and design methodologies based on them are still unexplored. In this work, we propose two NOR logic based n-input and n-output reversible gates one of which can be efficiently mapped in optical computing using the Mach–Zehnder interferometer (MZI) while the other one can be mapped efficiently in optical computing using the linear optical quantum gates. The proposed reversible NOR gates work as a corresponding NOR counterpart of NAND logic based Toffoli gates. The proposed optical reversible NOR logic gates can implement the reversible boolean logic functions with a reduced number of linear optical quantum logic gates or reduced optical cost and propagation delay compared to their implementation using existing optical reversible NAND gates. It is illustrated that an optical reversible gate library having both optical Toffoli gate and the proposed optical reversible NOR gate is superior compared to the library containing only the optical Toffoli gate: (i) in terms of number of linear optical quantum gates when implemented using linear optical quantum computing (LOQC), (ii) in terms of optical cost and delay when implemented using the Mach–Zehnder interferometer.     

Advancements in bipolar VLSI circuits and technologies

Due to their inherent speed advantage over FETs, bipolar circuits are widely used for high-performance masterslice and custom logic and for high-speed static memory arrays. For logic, traditional circuits such as transistor-transistor logic and emitter-coupled logic are still mostly used, but new circuit technologies such as integrated injection logic or merged transistor logic and Schottky transistor logic or integrated Schottky logic have been devised to manage the VLSI technology constraints. For high-speed memory applications such as caches, local stores, or registers, conventional memory cells are increasingly being replaced by more advanced memory devices allowing higher bit densities and lower power dissipation. Significant progress can be expected through technology extensions such as dielectric isolation, multilayer metallization, and polysilicon techniques, in addition to shrinking the devices to 1 /spl mu/m dimensions or below.     

具有1比特记忆的组合器的相关性

探讨了具有1比特记忆的组合器的输出序列和输入序列的相关性以及记忆对相关性的影响。     

A 1-GHz logic circuit family with sense amplifiers

This paper describes a newly developed logic circuit family based on dual-rail bit lines and sense amplifiers that is used extensively in a 1.0-GHz, single-issue, 64-bit PowerPC integer processor, gigahertz unit test site (guTS). The family consists of an incrementor, a count-leading-zero, a rotator, and a read-only memory. Each macro consists of a leaf-cell array, dual-rail bit lines, a row of sense amplifiers, a control block, and peripheral circuits. A common read-out scheme sensing the differential voltage of dual-rail bit lines is used. The hardware was fabricated in a 0.25-μm drawn channel length, six-metal-layer (Al) CMOS technology (1.8-V nominal VDD). Wafer testing was performed using a probe card. The macros were tested cycle by cycle by scanning the input data to the read/write address latches and data latches, and scanning the result out from the output receiving latches. Functional testing was performed on guTS macros at frequencies up to 1.0 GHz at 25°C with nominal VDD (1.1 GHz for the ROM)     

Functional Demonstration of a Memristive Arithmetic Logic Unit (MemALU) for In‐Memory Computing

The development of in‐memory computing has opened up possibilities to build next‐generation non‐von‐Neumann computing architecture. Implementation of logic functions within the memristors can significantly improve the energy efficiency and alleviate the bandwidth congestion issue. In this work, the demonstration of arithmetic logic unit functions is presented in a memristive crossbar with implemented non‐volatile Boolean logic and arithmetic computing. For logic implementation, a standard operating voltage mode is proposed for executing reconfigurable stateful IMP, destructive OR, NOR, and non‐destructive OR logic on both the word and bit lines. No additional voltages are needed beyond “V_P” and its negative component. With these basic logic functions, other Boolean functions are constructed within five devices in at most five steps. For arithmetic computing, the fundamental functions including an n‐bit full adder with high parallelism as well as efficient increment, decrement, and shift operations are demonstrated. Other arithmetic blocks, such as subtraction, multiplication, and division are further designed. This work provides solid evidence that memristors can be used as the building block for in‐memory computing, targeting various low‐power edge computing applications.