Method for online nondestructive hardness assurance for CMOS LSI circuits realized in SOS technology

The radiation performance of digital CMOS circuits realized in SOS technology is investigated in relation to the radiation-induced charge at the silicon-sapphire interface. A nondestructive hardness-assurance method based on radiation annealing is proposed, and reasons are given why this approach should be feasible. The limits of applicability of the method are assessed.     

A CMOS/SOS 4K static RAM

Discusses high density CMOS/SOS technology used to develop a fully static 4096-bit RAM with a five-transistor storage cell. Selection of a five-transistor memory cell has reduced the access to the flip-flop storage element to a single word line transistor and bit line. The word line transistor must be able to prevent data altering currents from entering the memory cell at all times except for the write operation. The write operation is enhanced by reducing the bias voltage across the memory cell, thereby making the current needed to alter the cell smaller. Through the use of a 5 /spl mu/m design rule, the memory cell occupies 2913 /spl mu/m/SUP 2/. The 4096-bit static CMOS/SOS RAM contains 22553 transistors in 20 mm/SUP 2/. Organised as 1024 4-bit words, the RAM has a read cycle time of 350 ns and standby power dissipation of 50 /spl mu/W at V/SUB cc/=5 V and temperature of 27/spl deg/C.     

16K CMOS/SOS asynchronous static RAM

A new CMOS/SOS `buried-contact' process allows fabrication of dense static memory cells. The technology is applied in a 16K RAM with 1150 /spl mu/m/SUP 2/ (1.78 mil/SUP 2/) cells based on 5 /spl mu/m design rules.     

Surface induced latchup in VLSI CMOS circuits

Experimental as well as theoretical results on the latch-up effect in CMOS structures with and without an epitaxial layer are presented. In structures with an epitaxial layer the critical current for latchup firing is two orders of magnitude higher and latchup is essentially surface controlled. The strong surface effect observed is a consequence of the gate influence of surface conduction of the field oxide MOSFET's and on current gains of the bipolar transistors. Latch-up sensitivity can be decreased by increasing p⁺/p-well and n⁺/n-well spacing, by decreasing expitaxial layer thickness and by increasing substrate doping. In reducing the lateral dimensions, short-channel effects of the field oxide transistors imply the most severe limitations for latch-up immunity.     

An 18 ns CMOS/SOS 4K static RAM

A high-speed CMOS/SOS 4K word/spl times/1 bit static RAM is described. The RAM features a MoSi/SUB 2/ gate CMOS/SOS technology with 2 /spl mu/m gate length and 500 /spl Aring/ thick gate oxide. Performance advantage of SOS over bulk is discussed for the scaled-down MOS LSI with 1-2 /spl mu/m gate. A standard 6-transistor CMOS cell and a two-stage sense amplifier scheme are utilized. In spite of the rather conservative 3.5 /spl mu/m design rule except for the 2 /spl mu/m gate length, the cell size of 36/spl times/36 /spl mu/m, the die size of 3.11/spl times/4.07 mm, and the typical read access and cycle time of 18 ns are achieved. The active and standby power dissipation are 200 mW and 50 /spl mu/W, respectively.     

CMOS/SOS memory circuits for radiation environments

Memory circuit techniques which combine radiation hardness with high density, high speed, and low power dissipation have been developed. CMOS/SOS circuits featuring self-compensation, self-biasing, and parameter tracking accommodate a wide range of nonuniform on-chip parameter variations. These variations may occur as the result of exposure to a nuclear radiation event or from MOS device processing, temperature, or power-supply effects. The circuits discussed in this paper are key elements for radiation-hardened memory designs [up to 10/SUP 6/ rad (Si)] with state-of-the-art LSI density and performance. The CMOS/SOS memory cell sizes (3.1 mil/SUP 2/ for a six-device static cell and 2.5 mil/SUP 2/ for a four-device static cell) are nearly five times smaller than previous radiation-hardened cells.     

Quadruple-well CMOS for VLSI technology

A novel process has been developed to fabricate high-density CMOS with four wells. These wells are self aligned to increase packing density. Two of them are relatively deep wells used to optimize both n- and p-channel active devices. The other two are shallow wells under field oxide to form channel stops for both device types. The channel stops provide rigorous isolation among similar devices and between the devices of the opposite polarity. Subthreshold leakage currents in isolation regions are <0.05 pA/µm when devices are biased at <16.5 V. The channel stops also suppress lateral parasitic bipolar action. To reduce the vertical bipolar gain, a new process technique employing a double-retrograde well and transient annealing has been established. For the CMOS structure with 2-µm p⁺-to-p-well spacing, we have eliminated latchup by suppressing the beta product to below unity. Moreover, the quadruple-well approach has produced active n- and p-channel FET's with excellent characteristics such as low threshold voltage (∼±0.5 V), low subthreshold slope (≲95 mV/dec), low contact resistivity (∼10^-7Ω-cm²), and high channel mobility (620 and 210 cm²/V . s).     

CMOS sensors for on-line thermal monitoring of VLSI circuits

The paper presents appropriate sensors for the realization of the design principle of design for thermal testability (DfTT). After a short overview of the available CMOS temperature sensors, a new family of temperature sensors will be presented, developed by the authors especially for the purpose of thermal monitoring of VLSI chips. These sensors are characterized by the very low silicon area of about 0.003-0.02 mm² and the low power consumption (200 μW). The accuracy is in the order of 1°C. Using the frequency-output versions an easy interfacing of digital test circuitry is assured. They can be very easily incorporated into the usual test circuitry, via the boundary-scan architecture. The paper presents measured results obtained by the experimental circuits. The facilities provided by the sensor connected to the boundary-scan test circuitry are also demonstrated experimentally     

TaSi2gate for VLSI CMOS circuits

It is shown, that lateral shrinkage of 2-µm CMOS devices and reduction of the gate oxide thickness to about 20 nm is significantly facilitated by replacing the n⁺-poly-Si or polycide gates by TaSi2. Due to its higher work function, TaSi2allows the simultaneous reduction of the channel doping in the n-channel and the charge compensation in the p-channel without changing the threshold voltages. Thus compared with n⁺-poly-Si gate n-channel transistors substrate sensitivity and substrate current are reduced, and low-level breakdown strength is raised. In p-channel transistors, the subthreshold current behavior and UT(L)-dependence are improved. Consequently, the channel length of both n- and p-channel transistors can be reduced by about 0.5 µm without significant degradation. The MOS characteristics Nss, flatband and threshold voltage stability, and dielectric strength appear similar for TaSi2and n+-poly Si gate transistors.     

Configurable CMOS multiplier/divider circuits for analog VLSI

The design of five simple CMOS opamp based multipler/divider circuits is presented. Each two opamp and six MOSFET transistor circuit simultaneously achieves four-quadrant multiplication and division. Applications of the new circuits in analog signal processing and neural networks are discussed. The multiplier/divider circuits are all insensitive to MOS intrinsic parasitic capacitances. They do, however, exhibit different sensitivities to opamp finite unity-gain bandwidth. These sensitivities may be mitigated using the configurability property of the circuits. Finally experimental results are provided to support some of the theoretical claims.     

Submicrometer polysilicon gate CMOS/SOS technology

A process is described for the fabrication of CMOS/SOS submicrometer devices and integrated circuits. The process utilizes the lateral diffusion of boron into polycrystalline silicon and a subsequent anisotropic etchant to define the narrow poly gates. Devices with channel lengths as small as 0.3 µm have been fabricated and characterized. Both avalanche and tunnel injection of carriers into the gate dielectric have been measured and both can have an impact on the limit of voltage operation. At present, these mechanisms appear to place an upper limit of about 8 V on the operating voltage of dynamic circuits containing 0.5- µm channel length devices. The propagation delay of 0.5-µm channel length CMOS/SOS inverters is about 200 ps at 5 V and dynamic binary counters will operate with a maximum input frequency of 550 MHz and 8 V while dissipating 130 mW.     

Floating substrate effects on speed performance in scaled CMOS/SOS circuits

Floating substrate effects on speed degradation in 2 ?m SOS circuits have been investigated. It has been found that the drain-substrate capacitive coupling is dominant in highly doped substrate devices, based on experimental results obtained from CMOS ring oscillators. Cycle-time-dependent sense amplifier output transition times have also been explained by this capacitive coupling.     

MOSFET-only switched-capacitor circuits in digital CMOS technology

Design techniques are described for the realization of precision high linearity switched-capacitor (SC) stages constructed entirely from MOS transistors. The proposed circuits use the gate-to-channel capacitance of MOSFET's for realizing all capacitors. As a result, they can be fabricated in any inexpensive basic digital CMOS technology, and the chip area occupied by the capacitors can be reduced. A number of different SC stages have been designed and fabricated using the proposed techniques. These included SC amplifiers, gain/loss stages, and data converters. Both the simulations and the experimental results obtained indicate that very high linearity (comparable to that achieved using analog fabrication processes with two poly-Si layers) can be achieved in these circuits using basic CMOS technology     

数字VLSI电路测试技术-BIST方案

分析了数字VLSI电路的传统测试手段及其存在问题,通过对比的方法,讨论了内建自测试(BIST)技术及其优点,简介了多芯片组件(MCM)内建自测试的目标、设计和测试方案。     

Self-aligned ion implant masking for CMOS VLSI technology

Conventional self-aligned ion implantation masking is often inadequate in CMOS VLSI fabrication. We describe a method of increasing this ion implant masking with minimal additional processing. Scanning electron micrographs portray the enhanced ion implant masking.     

Process technology for radiation-hardened CMOS integrated circuits

A process technology for radiation-hardened CMOS integrated circuits has been defined. Process parameters for the SiO/SUB 2/ gate insulator have been optimized for radiation hardness, and circuit latch-up due to parasitic p-n-p-n structures on the integrated circuits has been prevented by gold-doping the silicon substrate to reduce carrier lifetime. The device yields for the hardened technology have been evaluated and the reliability has been characterized by bias-temperature life testing.