共查询到20条相似文献,搜索用时 140 毫秒
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本文验证了F-N应力导致的SOI n- MOSFET器件性能退化与栅控二极管的产生-复合(G-R)电流的对应关系。F-N应力导致的界面态增加会导致SOI-MOSFET结构的栅控二极管的产生-复合(G-R)电流增大,以及MOSFET饱和漏端电流,亚阈斜率等器件特性退化。通过一系列的SOI-MOSFET栅控二极管和直流特性测试,实验观察到饱和漏端电流的线性退化和阈值电压的线性增加,亚阈摆幅的类线性上升以及相应的跨导退化。理论和实验证明栅控二极管是一种很有效的监控SOI-MOSFET退化的方法。 相似文献
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针对AlGaN/GaN HEMT器件在寿命试验过程中经常出现的栅源、栅漏和源漏泄漏电流随试验时间的延长而增大的现象,展开了深入的研究.分析了当前HEMT器件泄漏电流的各种主流退化模型,通过试验发现热载流子效应、逆压电效应等难以完全解释泄漏电流间的退化差异.进一步的研究显示,电极间的泄漏电流的差异主要是由材料中的缺陷和陷阱的密度分布不均匀造成的.在应力的作用下,初始密度越大,试验过程中缺陷和陷阱的增长速度就越快,泄漏电流的增长速度也就越快.但应力撤除后,由陷阱辅助隧穿导致的泄露电流会逐渐地得到恢复. 相似文献
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为了研究1200 V SiC MOSFET在重复非钳位感性开关(Unclamped-Inductive-Switching, UIS)应力下的电学参数退化机制,基于自行搭建的UIS实验平台以及Sentaurus仿真设计工具,首先深入分析了重复UIS测试后器件静态参数与动态参数的退化;接着基于FN隧穿公式对栅极漏电流数据进行拟合,得到随着UIS测试次数增加SiC/SiO2界面的势垒高度从2.52 eV逐渐降低到2.06 eV;最后解释了SiC MOSFET在重复UIS测试后的电流输运过程。结果表明,在重复雪崩应力的作用下,大量的正电荷注入至结型场效应管区域上方的栅极氧化层中,影响了该区域的电场分布以及耗尽层厚度,导致被测器件(Device Under Test, DUT)的导通电阻、漏源泄漏电流、电容特性等电学参数呈现出不同程度的退化,并且氧化物中的正电荷的积累也使电子隧穿通过栅介质的电流得到了抬升。 相似文献
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The degradation of device under GIDL(gate-induced drain leakage current)stress has been studied using LDD NMOSFETs with 1.4 nm gate oxides.Experimental result shows that the degradation of device parameters depends more strongly on Vd than on Vg.The characteristics of the GIDL current are used to analyze the damage generated during the stress.It is clearly found that the change of GIDL current before and after stress can be divided into two stages.The trapping of holes in the oxide is dominant in the first stage,but that of electrons in the oxide is dominant in the second stage.It is due to the common effects of edge direct tunneling and band-to-band tunneling.SILC(stress induced leakage current)in the NMOSFET decreases with increasing stress time under GIDL stress.The degradation characteristic of SILC also shows saturating time dependence.SILC is strongly dependent on the measured gate voltage.The higher the measured gate voltage,the less serious the degradation of the gate current.A likely mechanism is presented to explain the origin of SILC during GIDL stress. 相似文献
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Cherng-Ming Yih Shui-Ming Cheng Chung S.S. 《Electron Devices, IEEE Transactions on》1998,45(11):2343-2348
A new gate current model which considers the hot-electron induced oxide damage in n-MOSFET's was developed for the first time. The spatial distributions of oxide damage, including the interface state (Nit ) and oxide trapped charge (Qox) were characterized by using an improved gated-diode current measurement technique. A numerical model feasible for accurately simulating gate current degradation due to the stress generated Nit and Qox has thus been proposed. Furthermore, the individual contributions of Nit and Qox to the degradation of gate current can thus be calculated separately using these oxide damage. For devices stressed under maximum gate current biases, it was found that the interface state will degrade the gate current more seriously than that of the oxide trapped charge. In other words, the interface states will dominate the gate current degradation under IG,max. Good agreement of the simulated gate current has been achieved by comparing with the measured data for pre-stressed and post-stressed devices. Finally, the proposed degradation model is not only useful for predicting the gate current after the hot-electron stress, but also provides a monitor that is superior to substrate current for submicron device reliability applications, in particular for EPROM and flash EEPROM devices 相似文献
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Ja-Hao Chen Shyh-Chyi Wong Yeong-Her Wang 《Electron Devices, IEEE Transactions on》2001,48(12):2746-2753
The DC pulse hot-carrier-stress effects on the degradation in gate-induced drain leakage (GIDL) current in nMOSFETs in a high field regime and the mechanisms of stress-induced degradation are studied. In this paper, we investigate DC pulse stress parameters in GIDL which include frequency, rise/fall time, and stressing pulse amplitude. The contributions of hot-hole injection, interface state generation, and hot-electron injection in a period of transient stress are identified. It is found that the device degradation increases with increased pulse frequency under maximum gate current stress, while it decreases with reduced pulse frequency under maximum substrate current stress. This work is useful for DC pulse hot-carrier-stress reliability analysis under circuit operation 相似文献
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《Electron Devices, IEEE Transactions on》1986,33(9):1329-1333
We have employed a technique of constant current stress between the gate and drain of a MOS transistor to study the degradation of the threshold voltage, transconductance, and substrate current characteristics of the transistor. From the transistor characteristics, we propose that the degradation mechanism is a combined effect of trapping of holes in the gate oxide created by impact ionization due to the high electric field (> 8 MV/cm) across the oxide, and electron trapping phenomena. The degradation characteristics of the transistor under this constant current stress are quite similar to that observed normally due to the injection of hot electrons in the gate oxide when the transistor is biased in "ON" condition and the gate and drain voltages are selected to produce maximum substrate current. 相似文献
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Cheng-Liang Huang Soleimani H.R. Grula G.J. Sleight J.W. Villani A. Ali H. Antoniadis D.A. 《Electron Devices, IEEE Transactions on》1997,44(4):646-650
LOCOS-induced stress effects on thin-film SOI devices are investigated. We show that as the field oxide thickness increases, degradation (enhancement) of nMOSFET's (pMOSFET's) I-V characteristics becomes increasingly pronounced. The total degradation or enhancement of I-V characteristics can reach ~40% of drive current for devices under certain processing conditions. Estimated stress results using four-point bending measurement show that the stress level on the silicon film is of order 1200 MPa for devices with ~40% of I-V degradation/enhancement. We attribute the stress phenomenon to the volumetric expansion of field oxide during the LOCOS process 相似文献
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Shing-Hwa Renn Pelloie J.-L. Balestra F. 《Electron Devices, IEEE Transactions on》1998,45(11):2335-2342
Hot-carrier effects are thoroughly investigated in deep submicron N- and P-channel SOI MOSFETs, for gate lengths ranging from 0.4 μm down to 0.1 μm. The hot-carrier-induced device degradations are analyzed using systematic stress experiments with three main types of hot-carrier injections-maximum gate current (Vg≈Vd ), maximum substrate current (Vg≈Vd/2) and parasitic bipolar transistor (PBT) action (Vg≈0). A two-stage hot-carrier degradation is clearly observed for all the biasing conditions, for both N- and P-channel devices and for all the gate lengths. A quasi-identical threshold value between the power time dependence and the logarithmic time dependence is also highlighted for all the stress drain biases for a given channel length. These new findings allow us to propose a reliable method for lifetime prediction using accurate time dependence of degradation in a wide gate length range 相似文献
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Transient hot-electron effect and its impact on circuit reliability are investigated. The rate of device decay is monitored as a function of the gate pulse transient period. Simulation results reveal that excess charges during a fast turn off time may cause an increase in the maximum substrate current. This, along with our experimental data, identifies that transient excess carrier may cause the enhancement of device degradation under certain stress conditions. The enhancement factor of the degradation is a function of the gate pulse transient time. Correlation between the analysis based upon AC/DC measurement and calculations based upon transient simulation are shown in the paper. Better agreement with experimental data is obtained by using the transient analysis and on chip test/stress structures. The correlation between AC and DC stress data is also shown based on the impact ionization model. A hot-electron design guideline is proposed based on the circuit reliability analysis. This guideline can help improve the circuit reliability without adversely effecting the circuit performance. 相似文献
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A set of different short term stress conditions are applied to AlGaN/GaN high electron mobility transistors and changes in the electronic behaviour of the gate stack and channel region are investigated by simultaneous gate and drain current low frequency noise measurements. Permanent degradation of gate current noise is observed during high gate reverse bias stress which is linked to defect creation in the gate edges. In the channel region a permanent degradation of drain noise is observed after a relatively high drain voltage stress in the ON-state. This is attributed to an increase in the trap density at the AlGaN/GaN interface under the gated part of the channel. It was found that self-heating alone does not cause any permanent degradation to the channel or gate stack. OFF-state stress also does not affect the gate stack or the channel. 相似文献