IC设计中的ESD保护技术探讨

ESD是集成电路设计中最重要的可靠性问题之一。IC失效中约有40%与ESD/EOS(电学应力)失效有关。为了设计出高可靠性的IC,解决ESD问题是非常必要的。文中讲述一款芯片ESD版图设计,并且在0.35μm 1P3M 5V CMOS工艺中验证,成功通过HBM-3000V和MM-300V测试。这款芯片的端口可以被分成输入端口、输出端口、电源和地。为了达到人体放电模型(HBM)-3000V和机器放电模型(MM)-300V,首先要设计一个好的ESD保护网络。解决办法是先让ESD的电荷从端口流向电源或地,然后从电源或地流向其他端口。其次,给每种端口设计好的ESD保护电路,最后完成一张ESD保护电路版图。     

An on-wafer test structure to measure the effect of thermally-induced stress on silicon devices

We have developed a new on-wafer test structure to monitor the effect of stress on the electrical properties of semiconductor devices. We have fabricated this structure on two wafers with different oxygen concentrations. We show that we can directly relate the effect of thermally-induced stress to the oxygen concentration in the wafer by means of simple electrical parameters measurement. This simple measurement technique appears to be very sensitive to small variations of stress fields in silicon devices.     

ESD laboratory simulations and signature analysis of a CMOS programmable logic product

It is well established in the semiconductor I/C industry that the proportion of customer field returns attributed to damage resulting from electrical over-stress (EOS) and electro-static discharge (ESD) can amount to 40% to 50% (Cook C, Daniel S. Characteristics and failure analysis of advanced CMOS submicron ESD protection structures. EOS/ESD symposium proceedings ?14, Dallas, TX, 1992. p. 147; Denson WK, Green TJ. A review of EOS/ESD field failures in military equipment. EOS/ESO symposium proceedings-10, 1988. p. 7. Straub RJ. Automotive Electronics IC Reliability. CICC Proceedings, 1990; Euzent BL, Maloney TJ, Donner II R. Reducing field failure rate within proven EOS/ESO design. EOS/ESO Symposium Proceedings ?13, Los Vegas, NV, 1991. p. 59). ESD events are the subset of EOS events caused by high voltages that are associated with electrostatic charge. Although additional hard and soft failures can occur in the factory, these are normally screened by effective test programs. It is therefore necessary to determine the probable cause of failure before cost effective corrective action can be initiated.Distinguishing between EOS and ESD failures and differentiating the subtle differences between damage due to the several distinct ESD models continues to challenge failure analysis capabilities as dimensions shrink and critical defect sizes are reduced. Many of the damage sites are not visible with optical microscopy. De-processing together with very high magnification examination using the scanning electron microscope (SEM) is most often necessary. However, the use of test model simulators to replicate the ESD events can most often replicate a failure signature, i.e. a unique die location and morphology associated with the specific model (Morgan IH. ESO Failure Analysis Signatures. Proceedings of the 3rd ESO Forum, Grain, Germany, 1993. p. 275).This paper summarizes the evaluation performed on a standard programmable logic complimentary metal-oxide silican (CMOS) product to ascertain the ESD immunity. The study entailed ESD simulation using a variety of ESD models, conducting detailed physical failure analysis and then comparing the results with documented analyses performed on customer field returns and factory failures. As a result of the differences in current stress magnitude and over-stress time domain, the location, type and severity of damage at the failure site is known to show considerable variation (Morgan IH. A Handbook of ESO models. AMD Internal Publication, 1992 (available from AMD literature department upon request)). The purpose of the study was to develop a catalogue of failure signatures, and to determine to what extent this catalogue could be used to relate a signature to electrical failure for a particular die and pin function.     

用扫描声学显微镜进行塑封器件的封装分层分析

在塑封IC器件中，封装分层往往会产生电和封装的可靠性问题。由过电应力(EOS)和再流焊中的水汽膨胀引起的分层会显示出不同的失效模式。扫描声学显微镜可以用来检测封装分层，能在失效分析的早期阶段快速地鉴别失效原因。     

Simulating the dynamic electrothermal behavior of power electroniccircuits and systems

The simulator solves for the temperature distribution within the semiconductor devices, packages, and heat sinks (thermal network) as well as the currents and voltages within the electrical network. The thermal network is coupled to the electrical network through the electrothermal models for the semiconductor devices. The electrothermal semiconductor device models calculate the electrical characteristics based on the instantaneous value of the device silicon chip surface temperature and calculate the instantaneous power dissipated as heat within the device. The thermal network describes the flow of heat from the chip surface through the package and heat sink and thus determines the evolution of the chip surface temperature used by the semiconductor device models. The thermal component models for the device silicon chip, packages, and heat sinks are developed by discretizing the nonlinear heat diffusion equation and are represented in component form so that the thermal component models for various packages and heat sinks can be readily connected to one another to form the thermal network     

电导数测试用于大功率半导体激光器的快速筛选

对氧化物条型ＧａＡｓ／ＧａＡｌＡｓ大功率量子阱激光器的电导数曲线及其参数与器件可靠性之间的相关性进行了讨论,指出ｍ,ｈ,ｂ参数可以评价器件质量和可靠性。实验结果表明电导数测试是大功率半导体激光器快速筛选的新方法。     

A study on electrochemical effects in external capacitor packages

Exposing semiconductor devices with external capacitors to harsh environmental conditions may lead to electrical failures with the formation of conductive paths. This paper presents examples of the analysis of modules with the purpose to understand the respective failure modes. Appropriate sample preparation, sensitive analytical methods like micro-X-ray fluorescence spectroscopy (μXRF), ToF-SIMS, SEM/EDX, X-ray-microscopy as well as micro computed X-ray-tomography (μCT) have been applied to identify the root causes of the electrical failures.As a main conclusion of these investigations, we found that electrolytes can easily penetrate thermoplastic overmold materials which are typically used by module manufacturers. This can lead to either reversible electrical failures which can be eliminated by drying or irreversible electrical failures because of material migration. The effective failure mode depends on mechanical and climate conditions inside the module which could not be simulated up to now under laboratory but only under application conditions.     

Light emission as an analysis tool for GaAs ICs

As GaAs IC integration continues, device characterization and failure analysis get more difficult to perform. Standard visual and electrical inspections are becoming less adequate to evaluate devices and determine root cause of failures. A relatively new technique, used for several years on silicon devices, is light emission microscopy. The properties of light emission on silicon devices have been known for several decades. The light-producing properties of GaAs, a direct bandgap material, make it a natural for light emission study. This overview is intended to discuss the methodology and results of GaAs MESFET light emission.     

Electrostatic-Discharge Awareness & Control?An R&M 2000 Issue

As weapon systems become more sophisticated to meet multiple complex hostile threats, there will be an increasing reliance upon a high density of analog and digital microelectronic components, modules, and subsystems. Hybrid microelectronics are moving toward submicron geometries for semiconductor components, multilayer interconnects, and higher component densities on larger area substrates. This miniaturization increases the susceptibility of microelectronic circuitry to electrical overstress (EOS) and electrostatic discharge (ESD). Since EOS and ESD directly affect reliability and maintainability, procedures must be developed to account for them in engineering design, manufacturing, and testing. Over the past several years, there has been a concerted effort to raise ESD awareness at all levels of design and production at Motorola and other electronic firms. This paper briefly describes what measures should be considered and presents examples of their implementation at Motorola to increase reliability, lower costs, and reduce maintainability factors.     

Small-signal operation of semiconductor devices includingself-heating, with application to thermal characterization andinstability analysis

A rigorous mathematical treatment of dynamic self-heating in semiconductor devices is presented. Two formulations for the admittance parameters are given. The thermal behavior of the device is referred to device temperature in the first formulation, and to ambient temperature in the second. Contrary to previous work, nonlinear thermal effects are included. An analytical model for the thermal resistance is derived which confirms the relevance of these effects. Applications of the above results to device modeling and thermal characterization are studied in detail by means of numerical simulations. Possible sources of inaccuracies are evidenced. Finally, it is shown that the differential analysis of thermal feedback provides a general and rigorous means to determine the conditions for the onset of thermally-induced instabilities     

Thermal instability of low voltage power-MOSFETs

This paper analyzes an anomalous failure mechanism detected on last generation low voltage power metal oxide semiconductor (MOS) devices at low drain current. Such a behavior, apparently due to a kind of second breakdown phenomenon, has been scarcely considered in literature, as well as in manufacturer data sheets, although extensive experimental tests show that it is a common feature of modern low voltage metal oxide semiconductor held effect transistor (MOSFET) devices. The paper starts by analyzing some failures, systematically observed on low voltage power MOSFET devices, inside the theoretical forward biased safe operating area. Such failures are then related to an unexpected thermal instability of the considered devices. Experimental tests have shown that in the considered devices the temperature coefficient is positive for a very wide drain current range, also including the maximum value. Such a feature causes hot spot phenomena in the devices, as confirmed by microscope inspection of the failed devices. Finally, it is theoretically demonstrated that the thermal instability is a side effect of the progressive die size and process scaling down. As a result, latest power MOSFETs, albeit more efficient and compact, are less robust than older devices at low drain currents, thus requiring specific circuit design techniques     

Characterization and modelling of ageing failures on power MOSFET devices

A method based on the failure analysis of power MOSFET devices tested under extreme electrothermal fatigue is proposed. Failure modes are associated to several structural changes that have been investigated through acoustic, electron and ion microscopy. The main aging mode is related to the exponential increase in drain resistance due to delamination at the die attach. Earlier failures are observed when very local defects due to electrical over stresses (EOS) occur at the source metallization or at the wire bonding. Aging models were elaborated to account for the die attach delamination, but are still lacking to take in account the structural evolution of the Al metallization. This new methodology, based on accelerated tests and structural observations aims at designing a new generation of power components that will be more reliable.     

Procedures for Selection of Semiconductor Diodes for Use in Undersea Cable Systems

The nonredundant transistorized repeaters used in undersea cable systems are intended to operate on the ocean floor without maintenance for twenty years. To provide the best possible assurance that this high level of reliability is in fact attained, semiconductor transistors and diodes manufactured for cable use are screened to identify and eliminate the early failures. Devices surviving the screening are then subjected, for at least six months, to real time aging which simulates the worst-case use-conditions. The devices are removed from the aging environment and certain of the devices are selected for use in undersea cable operation. It is the purpose of this paper to discuss the empirically derived procedures for selecting two types of semiconductor diodes. The test data on which the selection is based consist, in each case, of period measurements of four electrical parameters while the diodes are aging. There was apparently no accepted and well formulated statistical model for the data on which a conventional technique could be based. Thus more unconventional procedures for device selection had to be constructed. The selection procedures have been implemented and perform well.     

Single-insertion temperature testing of semiconductor ICs

This paper presents a preliminary-design study considering the feasibility and conceptual implementation of single-insertion temperature testing of any type of semiconductor integrated circuit (IC): memory, microcontroller, microprocessor, or application specific IC. Analyses are presented that establish the necessary thermal response rate of a device under test to make single-insertion testing comparable in throughput performance to a conventional test method. Modeling with ideal conditions to obtain the fastest device response shows that single-insertion testing in testing plastic packaged parts (or slow responding devices) will only be applicable when the test parallelism is very high (>32) and lot overhead times are long (⩾1 h). Given that actual lot overhead times are generally less than 1 h and the trend is for decreasing lot overhead times, the test method is likely more applicable to testing die-exposed type devices, since the test parallelism can be much lower for a given lot overhead time     

芯片的EOS失效分析及焊接工艺优化

为了研究电过应力对功率MOSFET可靠性的影响,分别对含有焊料空洞、栅极开路和芯片裂纹缺陷的器件进行失效分析与可靠性研究.利用有限元分析、电路模拟及町靠性加速实验,确定了器件发生EOS失效的根本原因,并通过优化芯片焊接温度.时间曲线和利用开式感应负载测试方法,比较了工艺优化前、后器件抗EOS的能力,结果表明优化后器件的焊料空洞含量显著减少,抗EOS能力得到明显提高.     

Plastic packaging is highly reliable

Plastic encapsulation is now a high reliability (HiRel) method of packaging active semiconductor devices and microelectronics in general. This paper shows that the traditional requirement for hermetic packaging can be overturned in favor of plastic packaging, on the following grounds: the full range of laboratory evidence of HiRel silicone junction coated IC undertaken by many researchers, showing that plastic encapsulations can now be used for microelectronics and optoelectronics in telecommunication, automotive, military and space applications as the better option in many instances; the inadequacy of the Mil-Std hermeticity specification; the demonstrated field failures of Mil-Std-883 hermetic packaged devices and the massive ingress of moisture, which caused many failures of telecommunication switching systems; and the demonstrated better field-reliability in rural tropical climates, of assessed, standard PEM from major manufacturers     

半导体器件的发展动态

本文首先对国内半导体分立器件和半导体集成电路的质量水平做了估价,接着进行了国内半导体器件市场分析,讨论了器件销售所面临的困难和造成困难的原因,探讨了器件生产厂家的出路和发展方向,并对国产器件所存在的问题做了评述。文中还对半导体器件引进生产线情况做了介绍。本文在概述了分立器件的发展方向之后,重点阐述国内半导体集成电路的发展动态(我国IC工业发展现状、国内生产IC的主要品种、“七五”期间IC工业的发展及ASIC),并对国外IC发展动态做了扼要说明。     

Electrical and Mechanical Self‐Healing in High‐Performance Dielectric Elastomer Actuator Materials

Dielectric elastomers are of interest for actuator applications due to their large actuation strain, high bandwidth, high energy density, and their flexible nature. If future dielectric elastomers are to be used reliably in applications that include soft robotics, medical devices, artificial muscles, and electronic skins, there is a need to design devices that are tolerant to electrical and mechanical damage. In this paper, the first report of self‐healing of both electrical breakdown and mechanical damage in dielectric actuators using a thermoplastic methyl thioglycolate–modified styrene–butadiene–styrene (MGSBS) elastomer is provided. The self‐healing functions are examined from the material to device level by detailed examination of the healing process, and characterization of electrical properties and actuator response before and after healing. It is demonstrated that after dielectric breakdown, the initial dielectric strength can be recovered by up to 67%, and after mechanical damage, a 39% recovery can be achieved with no degradation of the strain–voltage response of the actuators. The elastomer can also heal a combination of mechanical and electrical failures. This work provides a route to create robust and damage tolerant dielectric elastomers for soft robotic and other applications related to actuator and energy‐harvesting systems.     

200 nm gated field emitters

The fabrication and electrical characteristics of 200-nm chromium-gated silicon field emitters are reported. These gated emitters are the smallest yet reported. A turn-on voltage of approximately 35 V represents a sublinear scaling of device operating voltage with device size. Emitter failures appear to be very similar to failures of 2-μm devices produced using the same process     

A DC and small signal AC model for organic thin film transistors including contact effects and non quasi static regime

We present a compact model for the DC and small signal AC analysis of Organic Thin Film Transistors (OTFTs). The DC part of the model assumes that the electrical current injected in the OTFT is limited by the presence of a metal/organic semiconductor junction that, at source, acts as a reverse biased Schottky junction. By including this junction, modeled as a reverse biased gated diode at source, the DC model is able to reproduce the scaling of the electrical characteristics even for short channel devices.The small signal AC part of the model uses a transmission line approach in order to compute the impedances of the channel and parasitic regions of the device. The overlap capacitances and the presence of non-ideal metal/organic semiconductor junctions are taken in account as well and the model can be easily adapted to different device geometries. The model is particularly well suited for printed devices, often realized with large process tolerances, since it takes into consideration the presence of parasitic regions and their effect on the AC operation.The model has been validated on printed OTFTs using a pentace-derivative as organic semiconductor with a quite peculiar device layout. It has been fully implemented in Verilog-A programming language.