A high-endurance low-temperature polysilicon thin-film transistorEEPROM cell

A planar type polysilicon thin-film transistor (poly-Si TFT) EEPROM cell with electron cyclotron resonance (ECR) N₂O-plasma oxide has been developed with a low temperature (⩽400°C) process. The poly-Si TFT EEPROM cell has an initial threshold voltage shift of 4 V for programming and erasing voltages of 11 V and -11 V, respectively. Furthermore, the poly-Si TFT EEPROM cell maintains the threshold voltage shift of 4 V after 100 000 program/erase cycles. The excellent high endurance of the fabricated poly-Si TFT EEPROM cell is attributed to the ECR N₂O-plasma oxide with good charge-to-breakdown (Qbd) characteristics     

Novel Twin Poly-Si Thin-Film Transistors EEPROM With Trigate Nanowire Structure

This letter demonstrates a novel twin poly-Si thinfilm transistor (TFT) electrical erasable PROM (EEPROM) that utilizes trigate nanowires (NWs). The NW TFT EEPROM has superior gate control because its trigate structure provides a higher memory window and program/erase (P/E) efficiency over those of a single-channel one. For endurance and retention, the memory window can be maintained at 1.5 V after $hbox{10}^{3}$ P/E cycles and 25% charge loss for ten years of NW twin poly-Si EEPROM. This investigation explores its feasibility in future active matrix liquid crystal display system-on-panel and 3-D stacked Flash memory applications.      

A single poly EEPROM cell structure for use in standard CMOSprocesses

A single poly EEPROM cell structure implemented in a standard CMOS Process is developed. It consists of adjacently placed NMOS and PMOS transistors with an electrically isolated common polysilicon gate. The common gate works as a “floating gate”. The inversion layer as “control node (gate)”. Test chips which were fabricated in a 0.8 μm/150 Å standard CMOS logic process showed 5-9 V of threshold voltage shift and more than 10000 cycles of endurance with good data retention under high temperature. This EEPROM cell can be easily integrated with CMOS digital and analog circuits     

Electrical/thermal properties of nonplanar polyoxides and theconsequent effects for EEPROM cell operation

The electrical/thermal properties of nonplanar polyoxides and the resulting effects for EEPROM operational margins are reported. The polyoxide between floating gate (FG) and control gate (CG) of FLOTOX-type EEPROM cells is nonplanar because it always contains edges, where CG wraps over FG. At such edges a highly stable electrical passivation of Fowler-Nordheim (FN) leakage currents occurs, which can cause a degradation of EEPROM operational margins, due to an electron discharge mechanism from the FG of charged EEPROM cells during the first charging operation after conventional baking. The EEPROM cell study includes the dependence on repeated passivation/depassivation of the polyoxide, on baking temperature and baking time. It is found that the average magnitude of the electron discharge is reduced after each passivation/depassivation cycle, which points to a progressive increase of the number of electrons captured in deep neutral electron traps at the polyoxide edges. Analysis of the temperature dependence leads to an activation energy (thermal detrapping energy of the electrons) of 1.3 eV for the degradation mechanism of EEPROM cell operational margins as well as the nonplanar polyoxide depassivation     

A novel flash EEPROM cell based on trench technology forintegration within power integrated circuits

A flash EEPROM suitable for integration within power integrated circuits (PIC's) is presented. The EEPROM cell uses a trench floating gate to give a large gate charge while using no more silicon area than a conventional flash EEPROM cell. The cell shows good immunity against the induced disturbance voltages which are present in a PIC, and the storage lifetime is greater than ten years at a reading voltage of V_D=2.2 V     

A side-wall transfer-transistor cell (SWATT cell) for highlyreliable multi-level NAND EEPROMs

A multi-level NAND Flash memory cell, using a new Side-WAll Transfer-Transistor (SWATT) structure, has been developed for a high performance and low bit cost Flash EEPROM. With the SWATT cell, a relatively wide threshold voltage (V_th) distribution of about 1.1 V is sufficient for a 4-level memory cell in contrast to a narrow 0.6 V distribution that is required for a conventional 4-level NAND cell. The key technology that allows this wide V_th distribution is the Transfer Transistor which is located at the side wall of the Shallow Trench Isolation (STI) region and is connected in parallel with the floating gate transistor. During read, the Transfer Transistors of the unselected cells (connected in series with the selected cell) function as pass transistors. So, even if the V_th of the unselected floating gate transistor is higher than the control gate voltage, the unselected cell will be in the ON state. As a result, the V_th distribution of the floating gate transistor can be wider and the programming can be faster because the number of program/verify cycles can be reduced. Furthermore, the SWATT cell results in a very small cell size of 0.57 μm² for a 0.35 μm rule. Thus, the SWATT cell combines a small cell size with a multi-level scheme to realize a very low bit cost. This paper describes the process technology and the device performance of the SWATT cell, which can be used to realize NAND EEPROM's of 512 Mbit and beyond     

A 128 K flash EEPROM using double-polysilicon technology

An easily manufacturable 128 K flash EEPROM (electrically erasable programmable read-only memory) was developed based on a novel cell. Programming is achieved through hot-electron injection and erasing through electron tunneling from the floating gate to the drain. The cell is 20% larger than an EPROM cell and contains an integral series transistor which ensures selflimited erasing, reduces leakage, and increases the cell current. The flash EEPROM device can withstand thousands of program/erase cycles. Endurance failures are due to threshold window closing caused by electron trapping in the gate oxide. Typical erasure time is 1 s to clear the entire memory.     

An adaptive thin-film transistor

A thin-film transistor (TFT) is described whose transfer characteristic can be reversibly adapted by a short duration voltage pulse applied to a high impedance gate electrode. The device is a four-terminal two-gate structure. A source, drain, and insulator gate contact form the basic TFT, while the amount and polarity of the polarization charge on the surface of the ferroelectric material of a second gate contact determines the pinchoff voltage of the TFT transfer characteristic. Measurements on experimental units demonstrate that the pinchoff voltage is adjustable over a sizable range, and that TFT transconductance changes in excess of 1000 to 1 can be obtained. The time required to change between different states of the TFT characteristic is limited by the switching time of the ferroelectric material which, in general, can be of the order of microseconds. Electrical instabilities in the transfer characteristics of the devices, however, may limit their practical circuit application. The instabilities are observed as a slow time variation of pinchoff voltage after a state has been established. Experimental units use triglycine sulfate for the ferroelectric material and tellurium-silicon monoxide thin film transistors.     

TFT栅极绝缘层和非晶硅膜层的ITO污染对电学特性影响的研究

本文对TFT在栅极绝缘层和非晶硅膜层沉积过程中,透明电极ITO成分对膜层的污染和TFT电学性质的影响进行分析研究。通过二次离子质谱分析和电学测试设备对样品进行分析。ITO成分会对PECVD设备、栅极绝缘层和非晶硅膜层产生污染,并会影响TFT的电学特性。建议采用独立的PECVD设备完成ITO膜层上面的栅极绝缘层和非晶硅膜层的沉积,并且对设备进行周期性清洗,可降低ITO成分的污染和提高产品的电学性能。     

Optimum design of dual-control gate cell for high-density EEPROM's

A new floating-gate-type cell with a dual-control gate (dc cell) has been developed and the structure optimized to realize high-density EEPROM's. In this new cell, an address selection transistor has been eliminated, thus attaining a single-transistor-per-cell configuration. The address selection is achieved by coincidence of two control gates, which are connected to column or row decoders supplied with an appropriate programming voltage. The stored charge in the floating gate suffers some disturbance by repetition of half-selection mode operation--defined as a state in which one of the control gates is set to high and the other to low during programming. In order to improve the endurance of the cell against half-selection mode operation, a new source biasing method has been introduced. As a result, the endurance has been improved by more than 3 orders of magnitude. A WRITE/ERASE endurance of 10⁵cycles and a data retention capability of more than 10 years have been obtained for the dc cell. The design parameters for a 64K EEPROM chip are also described.     

A new architecture for the NVRAM-an EEPROM backed-up dynamic RAM

An architecture for a nonvolatile RAM (NVRAM) suitable for high-density applications is described. In the cell, a dynamic RAM cell is merged into an EEPROM cell. A capacitor is constructed between the control gate and the drain diffusion layer of the FLOTOX-type EEPROM memory cell. The equivalent circuit in the dynamic RAM mode consists of two transistors and a capacitor, which eliminates a dummy cell. A dynamic RAM sense amplifier is used in both modes, and it works as a data latch when data are transferred between the dynamic RAM and the EEPROM. The process of the NVRAM is compatible with ordinary EEPROMs     

A degradation mechanism of EEPROM cell operational margins whichremains undetected by conventional quality assurance

We report an electron-discharge mechanism from the floating gate of charged EEPROM cells during the first charging operation after baking (250°C, 24 h). For an ensemble of measured EEPROM tells the discharge occurs statistically with threshold-voltage reductions up to over 1 V. Responsible is Fowler-Nordheim (FN) tunneling through the interpolyoxide at the edge where the control gate wraps over the floating gate. This FN tunneling is normally suppressed by a localized highly stable electrical passivation, which is automatically generated by programming operations. Baking partly destroys this passivation so that subsequent cell charging removes more electrons from the floating gate by FN tunneling via the interpolyoxide than it adds via the tunneling oxide     

Submicron super TFTs for 3-D VLSI applications

High performance submicron super TFTs are reported. A novel grain enhancement method is used to form large single grain silicon at the channel region of the TFT, making its structure comparable to SOI MOSFET. The process can be performed with high controllability, thus giving much smaller device-to-device variation compared to conventional TFT process. The reported n-channel super TFT displays a subthreshold swing of 72 mV/dec, g_max=198 mS/mm and an I_dast of 0.3 mA/μm at V_g-V_t=1.5 V, with L_G=0.4 μm and t_ox=110 Å. The super TFT technology will facilitate the formation of three-dimensional (3-D) VLSI circuits and double gate CMOS     

Polymer Inverter Fabricated by Inkjet Printing and Realized by Transistors Arrays on Flexible Substrates

We have fabricated organic thin-film transistors (OTFTs) and implemented inverters on flexible substrates using polythiophene (PHT) as the semiconductor and polyvinylphenol (PVP) as the gate dielectric. The semiconductor was defined by inkjet printing. The poor consistency of the printing process has affected the uniformity of inkjet-printed OTFTs enormously. We also proposed a method to increase the yield by incorporating a pre-testing step during circuit fabrication. We designed and fabricated a basic unit of circuits called a thin-film transistor (TFT) array. These devices were then connected to each other to form a gate via printed nano-silver. To verify the implementation flow, we designed and measured bootstrap inverters and ring oscillator composed of them. The five-stage ring oscillator has been fabricated and oscillated at the frequency, 60 Hz, when the supply voltage is 40 V      

A single-poly EEPROM cell in SIMOX technology for high-temperatureapplications up to 250°C

A thin-film SIMOX technology has been used for fabrication of a single-polysilicon EEPROM cell suitable for high-temperature applications. The two transistor cell is composed of a select transistor and a floating gate transistor with 10 nm tunnel oxide. The EEPROM process extension requires only a few steps suitable for embedded memory applications with low cost and turn around time. Endurance and data retention characteristics of the SIMOX EEPROM cell are presented for a temperature of 250°C. The problem of temperature induced leakage currents in the select transistor at elevated temperatures is investigated     

不同双栅极设计对a-Si:H TFT特性影响

本实验于原有的单底栅a-Si TFT产品结构下,通过增加不同的顶栅极设计方式(不同a-Si覆盖比例、不同沟道几何形貌、不同沟道W/L比例)来研究双栅极设计对a-Si TFT特性的影响。实验结果显示双栅极a-Si TFT比现行单底栅a-Si TFT可以提升I_on 7%、降低SS 3%、同时对I_off以及TFT稳定性影响不明显,显示双栅极a-Si TFT设计结构具有在不提高成本以及不变更工艺流程下,达到整体提升TFT特性的效果。顶栅极 TFT 特性不如底栅极,推测为a-Si/PVX界面不佳使得电子导通困难导致,未来可以借由改善a-Si/PVX界面工艺提升顶栅极TFT特性。     

A novel depletion-gate amorphous silicon thin-film transistor

A novel type of amorphous silicon (a-Si) thin-film transistor (TFT) in which a depletion gate is added to the top of the second nitride layer of a conventional a-Si TFT has been fabricated. In this transistor, switching is done by the depletion gate instead of the accumulation gate as in conventional a-Si TFTs. The pinch-off voltage and ON-OFF current ratio of the transistor can be changed by the accumulation gate bias. The transistor exhibits high ON-OFF current ratio, low contact resistance, and low gate-source capacitance     

新型SiO2栅介质非晶硅薄膜晶体管室温红外探测器

对用作室温红外探测敏感单元的非晶硅薄膜晶体管进行了研究，提出了一种新型SiO2栅介质非晶硅薄膜晶体管室温红外探测器。该探测器的基本工作机理与传统的SiNx栅介质薄膜晶体管相类似，但在器件性能方面不仅具有较高的响应度，而且具有更好的温度稳定性；在制作工艺方面具有更高的工艺重复性和栅介质淀积的均匀性。     

新型SiO2栅介质非晶硅薄膜晶体管室温红外探测器

对用作室温红外探测敏感单元的非晶硅薄膜晶体管进行了研究,提出了一种新型SiO2栅介质非晶硅薄膜晶体管室温红外探测器。该探测器的基本工作机理与传统的SiN2栅介质薄膜晶体管相类似,但在器件性能方面不仅具有较高的响应度,而且具有更好的温度稳定性;在制作工艺方面具有更高的工艺重复性和栅介质淀积的均匀性。     

A novel nonvolatile memory cell suitable for both flash andbyte-writable applications

The structure, operation, and fabrication of a novel EEPROM/flash cell and array architecture are described. The cell is about half the size of the traditional floating gate tunnel oxide (FLOTOX) electrically erasable programmable read only memory (EEPROM) cell when laid out with the same design rules. This approach has a simple fabrication sequence and requires minimum overhead circuitry rendering it especially suitable for embedded applications. Characterization shows this approach has good retention and has million cycle endurance. Both read and write disturbs are characterized. There are large margins for both types of disturbs. In fact, the data on write disturbs show the disturb margins to be so large that disturb margin can be safely traded off for reduced stress on select transistors