一种高速并串转换控制电路设计

串行接口常用于高速数据传输,实现多路低速并行数据合成一路高速串行数据.设计了一种高速并串转换控制电路,实现在低频时钟控制下,通过内部锁相环(PLL)实现时钟倍频和数据选通信号,最终形成高速串行数据流,实现每5路全并行数据可按照顺序打包并转换为1路高速串行编码,最后通过一个低电压差分信号(LVDS)接口电路输出.该芯片通过0.18 μmCMOS工艺流片并测试验证,测试结果表明在120 MHz外部时钟频率下,该并串转换控制芯片能够实现输出速度600 Mbit/s的高速串行数据,输出抖动特性约为80 ps,整体功耗约为23 mW.     

1.25Gbps串并并串转换接收器的低抖动设计

对1.25Gbps应用于千兆以太网的低抖动串并并串转换接收器进行了设计,应用了带有频率辅助的双环时钟数据恢复电路,FLL扩大了时钟数据恢复电路的捕捉范围。基于三态结构的鉴频鉴相从1.25Gbps非归零数据流中提取时钟信息,驱动一个三级的电流注入环形振荡器产生1.25GHz的低抖动时钟。从低抖动考虑引入了均衡器。该串并并串转换接收器采用TSMC0.35μm2P3M3.3V/5V混合信号CMOS技术工艺。测试结果表明了输出并行数据有较好的低抖动性能:1σ随机抖动(RJ)为7.3ps,全部抖动(TJ)为58mUI。     

一种1.25 Gbps CMOS以太网串并/并串转换电路

用0．35μm CMOS工艺实现了单芯片1．25Gbps千兆以太网串并／并串转换电路。该电路兼容ANSI的光纤信道物理层标准(FC-0)。与同类电路相比，其核心单元—并串转换电路和串并转换电路—具有结构简单、面积小的优点[1，2]，其高速串行数据随机抖功只有同类电路的一半。另外，电路中还集成了锁相环环路滤波电容。     

基于FPGA的高速串并/并串转换器设计

在数字通信系统的数据传输中,多数通信数据为串行方式,而大多数处理器要求数据以并行方式存储和处理,所以经常需要将串行传输的数据变换成并行传输,或者将并行传输的数据变换成串行传输,这时就需要串并/并串转换器。在此介绍了串并/并串转换器基本原理,并通过QuartusⅡ仿真平台进行仿真验证,最后下载到FPGA芯片EP1K30QC208-2实现了串并/并串转换器的设计,仿真及实验结果表明采用此设计方案是可行的。     

接收器中并行数据与字节时钟同步的电路设计

在串并转换接收器中,并行数据在字节时钟的作用下并行输出.如何保证同一时刻输出的并行数据属于同一个字节,即并行数据与字节时钟的同步,是串并转换接受器中的一个关键问题.根据串并转换电路可以使用移位寄存结构,字节时钟可以在串行时钟的基础上使用计数器得到,而计数器又模可变的特点,设计了一种在数据的串并转换中进行并行数据与字节时钟同步的电路,经过理论分析与软件仿真,证明电路性能良好可行.     

1.25 Gbps并串转换CMOS集成电路

分析了由超高速易重用单元构造的树型和串行组合结构 ,实现了在输入半速率时钟条件下 1 0路到1路吉比特率并串转换。通过理论推导着重讨论了器件延时和时钟畸变对并串转换的影响 ,指出了解决途径。芯片基于 0 .3 5μm CMOS工艺 ,采用全定制设计 ,芯片面积为 2 4.1 9mm2 。串行数据输出的最高工作速率达到 1 .62 Gbps,可满足不同吉比特率通信系统的要求。在 1 .2 5 Gbps标准速率 ,工作电压 3 .3 V,负载为 5 0 Ω的条件下 ,功耗为 1 74.84m W,输出电压峰 -峰值可达到 2 .42 V,占空比为 49% ,抖动为 3 5 ps rms。测试结果和模拟结果一致 ,表明所设计的电路结构在性能、速度、功耗和面积优化方面的先进性。文中设计的芯片具有广泛应用和产业化前景。     

基于130 nm CMOS工艺的5 Gbit/s 10:1并串转换芯片

介绍了一种基于GSMC 130 nm CMOS工艺的高速率低功耗10:1并串转换芯片。在核心并串转换部分,该芯片使用了多相结构和树型结构相结合的方式,在输入半速率时钟的条件下,实现了10路500 Mbit/s并行数据到1路5 Gbit/s串行数据的转换。全芯片完整后仿真结果显示,在工作电压(1.2±10%)V、温度-55~100℃、全工艺角条件下,该芯片均可正确完成10:1并串转换逻辑功能,并输出清晰干净的5 Gbit/s眼图。在典型条件下,芯片整体功耗为25.2 mW,输出电压摆幅可达到260 mV。     

一种采用半速结构的CMOS串行数据收发器的设计

设计了一种单片集成的CMOS串行数据收发器．该收发器用于线上速率为1.25Gb/s的千兆以太网中,全集成了发送和接收的功能,主要由时钟发生器、时钟数据恢复电路、并串／串并转换电路、线驱动器和均衡器组成．为了降低系统设计难度和电路功耗,收发器采用了半速率时钟结构．电路采用1.8V 0.18μm 1P6M CMOS数字工艺,芯片面积为2.0mm×1.9mm．经Cadence Spectre仿真验证以及流片测试,电路工作正常,功能良好．     

AT24系列存储器数据串并转换接口的IP核设计

AT24系列EEPROM芯片是基于I^2C（Inter-Integrated Circuit）总线协议而设计的。该存储器与微处理器通信，需要把串行数据转换成并行数据，或把并行数据转换成串行数据后，通信过程才能进行。介绍和VHDL语言设计该存储器数据串并转换接口的IP核，从而通过硬件（FPGA或其他可编程芯片）实现AT24系列存储器与8位微处理器之间的并行通信。     

4Gbps低功耗并串转换CMOS集成电路

为满足传输数据的高速低功耗的要求,文章设计了一种半速率时钟驱动的二级多路选择开关式的10：1并串转换器。第一级为两个5：1的并行串化器,共用一个多相发生器。多相发生器由五个动态D触发器构成。第二级为一个2：1的并行串化器。采用半速率时钟、多路选择开关结构降低了大部分电路的工作频率,降低了工艺要求,也降低了功耗。通过调整时钟与数据间的相位关系,提高相位裕度,降低了数据抖动。采用1．8V 0．18μm CMOS工艺进行设计。用Hspice仿真器在各种PVT情况下做了仿真,结果表明该转换器在输出4Gbps数据时平均功耗为395μW,抖动18s^-1．     

Moving average filter for spur reduction in subsampling fractional PLLs

A mono-bit digital receiver circuit for instantaneous frequency measurement is presented. The circuit is co-designed with Indium Phosphide Double Heterojunction Bipolar Transistor and complementary metal oxide semiconductor (CMOS) devices. The chip is fabricated by InP/CMOS three-dimensional (3D) heterogeneous integration using the wafer-level bonding technique. The measurable signal frequency within?+?15 to???25 dBm power is up to 7.5 GHz with a 14-GHz clock. Compared to an integrated circuit (IC) with a traditional InP or CMOS technologies, the proposed chip could benefit from both InP and CMOS technology. In the heterogeneous integration, InP devices provide high operating frequency, broad signal bandwidth, and large input signal dynamic range, while CMOS devices achieve complex function with low power consumption. In this way, the system FoM is improved for a mono-bit digital receiver while the system power consumption is kept the same. This work also shows the great potential of the 3D heterogeneous integration for the high-performance mixed-signal and multifunction radio-frequency ICs.

     

Design of 10 GHz eight-phase voltage controlled oscillator in 90 nm CMOS

A novel 10 GHz eight-phase voltage-controlled oscillator(VCO) architecture applied in clock and data recovery(CDR) circuit for 40 Gbit/s optical communications system is proposed.Compared with the traditional eight-phase oscillator,a new ring CL ladder filter structure with four inductors is proposed.The VCO is designed and fabricated in IBM 90nm complementary metal-oxide-semiconductor transistor(CMOS) technology.Measurement results show the tuning range is 9.2 GHz～11.0 GHz and the phase noise of-108.85 dBc/Hz at 1 MHz offset from the carrier frequency of 10 GHz.The chip area of VCO is 500 μm× 685 μm and the power dissipation is 17.4 mW with the 1.2 V supply voltage.     

BiCMOS circuit technology for a 704 MHz ATM switch LSI

This paper describes BiCMOS level-converter circuits and clock circuits that increase VLSI interface speed to 1 GHz, and their application to a 704 MHz ATM switch LSI. An LSI with a high speed interface requires a BiCMOS multiplexer/demultiplexer (MUX/DEMUX) on the chip to reduce internal operation speed. A MUX/DEMUX with minimum power dissipation and a minimum pattern area can be designed using the proposed converter circuits. The converter circuits, using weakly cross-coupled CMOS inverters and a voltage regulator circuit, can convert signal levels between LCML and positive CMOS at a speed of 500 MHz. Data synchronization in the high speed region is ensured by a new BiCMOS clock circuit consisting of a pure ECL path and retiming circuits. The clock circuit reduces the chip latency fluctuation of the clock signal and absorbs the delay difference between the ECL clock and data through the CMOS circuits. A rerouting-Banyan (RRB) ATM switch, employing both the proposed converter circuits and the clock circuits, has been fabricated with 0.5 μm BiCMOS technology. The LSI, composed of CMOS 15 K gate logic, 8 Kb RAM, I Kb FIFO and ECL 1.6 K gate logic, achieved an operation speed of 704-MHz with power dissipation of 7.2 W     

A Self-Calibrated On-Chip Phase-Noise Measurement Circuit With −75 dBc Single-Tone Sensitivity at 100 kHz Offset

An on-chip clock phase-noise measurement circuit is presented. Unlike previously reported monolithic measurement techniques that measure jitter in the time domain, the proposed module measures the phase-noise spectrum. The proposed circuit is fully integrated and does not require a spectrally clean reference clock or any external calibration. The module can be integrated as part of a built-in self-test (BIST) scheme for PLL clock synthesizers. The proposed circuit uses a low-noise voltage-controlled delay-line (VCDL) and mixer-based frequency discriminator to extract the phase-noise fluctuations at baseband. A self-calibration circuit is used to operate the measurement circuit at its highest sensitivity point. The proposed circuit is fabricated using a 0.25 mum digital CMOS process and operates up to a 2 GHz carrier frequency. It achieves a single-tone measurement sensitivity of -75 dBc and an equivalent phase-noise sensitivity of -124 dBc/Hz at 100 kHz offset frequency.     

9.3-10.4-GHz-band cross-coupled complementary oscillator with low phase-noise performance

A fully integrated 10-GHz-band voltage-controlled oscillator (VCO) has been designed and fabricated using commercial 0.18-/spl mu/m CMOS technology. The complementary cross-coupled differential topology is adopted in the design. The measured phase-noise is around -89 dBc/Hz at the offset frequency of 100 kHz from the center frequency of 9.83 GHz, the output frequency tuning range of the fabricated VCO is 1.1 GHz ranging from 9.3 to 10.4 GHz, and the power consumption of the core VCO circuit is 5.8 mW. The design is the first one that adopts the complementary cross-coupled circuit structure for 10-GHz-band oscillators, and whose performances of the VCO are the best ones for 10-GHz-band oscillators, compared with the 10-GHz-band CMOS oscillators reported earlier.     

A Fully Integrated CMOS Phase-Locked Loop with 30 MHz to 2 GHz Locking Range and ±35 ps Jitter

A fully integrated phase-locked loop (PLL) fabricated in a 0.24 m, 2.5 v digital CMOS technology is described. The PLL is intended for use in multi-gigabit-per-second clock recovery circuits in fiber-optic communication chips. This PLL first time achieved a very large locking range measured to be from 30 MHz up to 2 GHz in 0.24 m CMOS technologies. Also it has very low peak-to-peak jitter less than ±35 ps at 1.25 GHz output frequency.     

Demonstration of RSFQ digitizer on a multichip module

A 1-b slice of a rapid single-flux quantum (RSFQ) digitizer with interchip communications on a multichip module (MCM) has been successfully designed, fabricated using 3-μm Nb technology, and tested. We placed a flash comparator followed by an enable switch and an MCM transmitter circuit on one side of the chip, and an MCM receiver circuit followed by a memory buffer on the other side. The 5 × 5 mm chip was flip-chip mounted on a 10 × 10 mm carrier chip by a solder bump technique. During circuit operation, the comparator output signal and the clock signal left the chip, moved to the carrier chip, and returned back to the chip into the memory buffer. We operated the circuit with a beat frequency technique where the data input frequency was slightly off from the clock frequency by the beat frequency of 10 kHz. The circuit operated correctly up to 10 GHz. The critical circuit operation margin was observed to be the bias current to the SQUID in the MCM receiver circuit and was about ±6% at 10 GHz     

Jitter Characteristic in Charge Recovery Resonant Clock Distribution

This paper is focused on analysis and suppression of clock jitter in charge recovery resonant clock distribution networks. In the presented analysis, by considering the data-dependent nature of the generated jitter, the reason for the undesired jitter-peaking phenomenon is investigated. The analysis has been verified by measurements on a test chip fabricated in 0.13-mum standard CMOS process. The chip includes a fully integrated 1.5-GHz LC clock resonator with a passive (bufferless) clock distribution network, which directly drives the clocked devices in pipelined data path circuits. Furthermore, a jitter suppression technique based on injection locking is presented. Measurement results show about 50% peak-to-peak clock jitter reduction from 28.4 ps down to 14.5 ps after injection locking.     

A 50 to 94-GHz CMOS SPDT Switch Using Traveling-Wave Concept

A fully integrated single-pole-double-throw transmit/receive switch has been designed and fabricated in standard bulk 90-nm complementary metal-oxide semiconductor (CMOS) technology. Traveling wave concept was used to minimize the insertion loss at higher frequency and widen the operating bandwidth. The switch exhibits a measured insertion loss of 2.7 -dB, an input 1-dB compression point (input P_{1 dB}) of 15 dBm, and a 29-dB isolation at the center frequency of 77 GHz. The total chip size is only 0.57 times 0.42 mm ² including all testing pads. To our knowledge, this is the first CMOS switch demonstrated beyond 50 GHz, and the performances rival those monolithic microwave integrated circuit switches using standard GaAs PHEMTs     

A 2-ns detecting time, 2-μm CMOS built-in current sensingcircuit

Built-in current testing is known to enhance the defect coverage in CMOS VLSI. An experimental CMOS chip containing a high-speed built-in current sensing (BICS) circuit design is described. This chip has been fabricated through MOSIS 2-μm p-well CMOS technology. The power bus current of an 8×8 parallel multiplier is monitored. This BICS detects all implanted short-circuit defects and some implanted open-circuit defects at a clock speed of 30 MHz (limited by the test setup). SPICE3 simulations indicate a defect detection time of about 2 ns