A new method of determination of the I-Vcharacteristics of negative differential conductance devices

A method for mapping the complete I-V characteristic of a negative differential conductance (NDC) device has been investigated. This method employs the measurable positive differential conductance (PDC) portions of the DC I-V curve together with the measured conductances at a fixed DC bias voltage in the PDC region with different RF signal levels using a standard semiconductor analyzer. The NDC regime of the I-V curve is numerically constructed from the measured conductances at a fixed DC bias voltage in the PDC region with different signal levels using a large-signal nonlinear-circuit analysis     

Light-to-input nonlinearities in an R-LED series network

The light-to-current (L-I) and light-to-voltage (L-V) differential nonlinearities in the simple network of a customary LED and an external resistor R in series are analyzed and calculated theoretically and compared with experimental data. Particular emphasis is placed on the influence of the log-arithmetic slope ν of the L-I characteristic and the bias current I upon the ratio of the corresponding nonlinearity parameters. It is thus deduced that, for a given optical power P, over superlinear portions of the L-I curve (ν>1) the L-I linearity is typically better than its corresponding L-V linearity. On the contrary, when the L-I dependence is sublinear (ν<1) the voltage driving scheme may ensure for the R-LED network, or the LED alone, a local L-V response much more linear than the L-I response, provided that appropriate (optimum) I and/or R values are chosen     

Low-frequency noise characteristics of lattice-matched(x=0.53) and strained (x>0.53) In0.52Al0.48As/InxGa1-xAs HEMT's

Extensive bias-dependent and temperature-dependent low-frequency (LF) noise measurements were performed on lattice-matched and strained In_0.52Al_0.48As/In_xGa_1-x As(0.53<x<0.70) HEMTs. The input-noise voltage spectra density is insensitive to V_DS bias and shows a minimum at V_GS corresponding to the peak g_m condition. The corresponding output-noise voltage spectral density, which depends strongly on the gain of the devices, increases with V_DS. The input noise was rather insensitive to indium (In) content. Temperature-dependent low-frequency noise measurements on these devices reveal shallow traps with energies of 0.11, 0.15, and 0.18 eV for 60%, 65%, and 70% In HEMTs. Noise transition frequencies for these devices were on the order of 200-300 MHz and remain almost the same for different channel In content and V_DS bias     

Interpretation and control of C-V measurementsusing pattern recognition and expert system techniques

The authors demonstrate how a pattern-recognition system can be applied to the interpretation of capacitance-voltage (C-V ) curves on an MOS test structure. By intelligently sequencing additional measurements it is possible to accurately extract the maximum amount of information available from C-V and conductance-voltage (G-V) measurements. The expert system described, (CV-EXPERT), is completely integrated with the measurement, instrumentation, and control software and is thus able to call up a sequence of individually tailored tests for the MOS test structure under investigation. The prototype system is able to correctly identify a number of process faults, including a leaky oxide, as shown. Improvements that could be gained from developing rules to coordinate G-V, capacitance-time, and doping profile measurements simply by recognizing the important factors in the initial C- V measurement are illustrated     

PV module characterization using Q-Rdecomposition based on the least square method

The determination of solar cell parameters (I-V characteristic) from experimental data was achieved by using the Q -R decomposition technique based on the least squares method, where all data points were considered. The algorithm used a three-parameter equation transformed from the original cell equation of five parameters. This method could be used to analyze the I-V characteristics of photovoltaic (PV) modules of various technologies under the natural conditions of implementation, and to help to establish the best sizing of a PV system and the best adaptation of a PV system to its environment     

An analytical model for I-V and small-signalcharacteristics of planar-doped HEMTs

An analytical current-voltage (I-V) model for planar-doped HEMTs is developed. This compact model covers the complete range of I-V characteristics, including the current saturation region and parasitic conduction in the electron-supplying layer. Analytical expressions for the small-signal parameters and current-gain cutoff frequency are derived from the I-V model. Modeling results for a 0.1-μm-gate planar-doped AlInAs-GaInAs HEMT show excellent agreement with measured characteristics. Threshold voltages and parasitic conduction in planar-doped and uniformly doped HEMTs are also compared and discussed     

Anomalous C-V characteristics of implanted polyMOS structure in n+/p+ dual-gate CMOS technology

The C-V characteristics of arsenic-doped polysilicon show a gate-bias dependence of the inversion capacitance and a reduction in the expected value of the inversion capacitance. The characteristics have been investigated with quasistatic and high-frequency C-V as well as conductance measurements of various capacitors that have been subjected to annealing times and temperatures ranging from 900°C/30 min to rapid thermal annealing at 1050°C. The results can be explained by assuming that there is a depletion region forming in the polysilicon due to insufficient activation of the dopant at the polysilicon/oxide surface. The impact of this condition on the device characteristics is shown to be a 20-30% reduction in the G_m of NMOS transistors with 125-Å Gate oxide thickness     

Input I-V and sampling time characteristics ofthe ACT device

The input I-V and sampling-time characteristics of the acoustic charge transport (ACT) device are presented for ohmic-contact charge injection and Schottky-gate-modulated charge injection. A computationally efficient analysis technique is developed to calculate the I-V and sampling-time data from two-dimensional potential and carrier-density distributions. Device physics and architecture are incorporated into the analysis through a numerical charge-injection model which is used to compute the potential and carrier-density distributions. Theoretical results are presented to demonstrate the charge injection characteristic of some typical device structures. The effects that the injection method, the epitaxial layer structure and the acoustic wave amplitude have on device performances are discussed. The physical basis of the analysis enables it to be used to study several other design parameters. Experimental measurements of a device I-V and input transconductance show good agreement with calculated data. This analysis technique provides a means of assessing the performance potential of new device designs     

Threshold voltage and C-V characteristics of SOIMOSFET's related to Si film thickness variation on SIMOX wafers

C-V characteristics of fully depleted SOI MOSFETs have been studied using a technique for measuring silicon-film thickness using a MOSFET. The technique is based on C-V measurements between the gate and source/drain at two different back-gate voltages, and only a large-area transistor is required. Using this technique, SOI film thickness mapping was made on a finished SIMOX wafer and a thickness variation of ±150 Å was found. This thickness variation causes as much as a 100-mV variation in the device threshold voltage. The silicon-film thickness variation and threshold-voltage variation across a wafer shows a linear correlation dependence for a fully depleted device. C-V measurements of the back-gate device yield the buried-oxide thickness and parasitic capacitances. The effects of GIDL (gate-induced drain leakage) current on C-V characteristics are also discussed     

A complete model of the I-V characteristics fornarrow-gate MOSFETs

A unified and process-independent MOSFET model for accurate prediction of the I-V characteristics and the threshold voltages of narrow-gate MOSFETs is discussed. It is based on several enhancements of the SPICE2 LEVEL3 MOS model and the author's previous subthreshold I-V model. The expressions achieved for the drain current hold in the subthreshold, transition, and strong inversion regions. A continuous model is proposed for the transition region, using a scheme that ensures that both the current and conductance are continuous and will not cause convergence problems for circuit simulation applications. All of the modeled parameters are taken from experimentally measured I-V characteristics and preserve physical meaning. Comparisons between the measured and modeled I-V characteristics show excellent agreement for a wide range of channel widths and biases. The model is well suited for circuit simulation in SPICE     

SPICE macro model for the simulation of zener diodeI-V characteristics

The problems encountered when using the existing SPICE diode model to represent the I-V characteristics of a Zener diode in the reverse region are examined. A Zener diode macro model that has accurate I-V simulation characteristics and can be easily constructed using SPICE-provided primitives is presented. The static I-V characteristics and temperature response of the diode are reviewed. The performance of the model is discussed, and its main enhancements as compared to the SPICE model are identified     

A new method of determination of the I-Vcharacteristics of negative differential conductance devices bymicrowave reflection coefficient measurements

A technique to map out all of the I-V characteristics of negative differential conductance (NDC) devices is described. This method uses the DC measurable positive conductance portions of the I-V curve together with the measured microwave reflection coefficients at different RF signal levels and fixed DC bias voltage. The advantages of the method for high NDC devices are pointed out in a stability analysis. The complete I-V curve of a tunnel diode has been obtained with an accuracy within 5% in a proof-of-principal test of this method     

A new I-V model for short gate-length MESFET's

An I-V model for short gate-length MESFETs operated in the turn-on region is proposed, in which the two-dimensional potential distributions contributed by the depletion-layer charges under the gate and in the ungated region are separately obtained by conventional 1-D approximation and the Green's function solution technique. Moreover, the bias-dependent parasitic resistances due to the modulation of the depletion layer in the ungated region for non-self-alignment MESFETs are also taken into account in the developed I-V model. It is shown that good agreement is obtained between the I-V model and the results of 2-D numerical analysis. Moreover, comparisons between the proposed analytical model and the experimental data are made, and excellent agreement is obtained     

Temperature dependence of common-emitter I-V andcollector breakdown voltage characteristics in AlGaAs/GaAs andAlInAs/GaInAs HBT's grown by MBE

Temperature-dependent measurements from 25 to 125°C have been made of the DC I-V characteristics of HBTs with GaAs and In_0.53Ga_0.47As collector regions. It was found that the GaAs HBTs have very low output conductance and high collector breakdown voltage BV_CEO>10 V at 25°C, which increases with temperature. In striking contrast, the In_0.53Ga_0.47As HBTs have very high output conductance and low BV_CEO~2.5 V at 25°C, which actually decreases with temperature. This different behavior is explained by the >10⁴ higher collector leakage current, I_CO, in In_0.53Ga_0.47As compared to GaAs due to bandgap differences. It is also shown that device self-heating plays a role in the I-V characteristics     

A new technique for measuring MOSFET inversion layer mobility

An experimental technique for accurately determining both the inversion charge and the channel mobility μ of a MOSFET is presented. With this new technique, the inversion charge is measured as a function of the gate and drain voltages. This improvement allows the channel mobility to be extracted independent of drain voltage V_DS over a wide range of voltages (V_DS=20-100 mV). The resulting μ(V_GS) curves for different V_DS show no drastic mobility roll-off at V _GS near V_TH. This suggests that the roll-off seen in the mobility data extracted using the split C- V method is probably due to inaccurate inversion charge measurements instead of Coulombic scattering     

Electrical transport properties of crystalline siliconcarbide/silicon heterojunctions

The electrical transport properties of β-SiC/Si heterojunctions were investigated using current-voltage (I-V) and capacitance-voltage (C-V) characteristics. The heterojunctions were fabricated by growing n-type crystalline β-SiC films on p-type Si substrates by chemical vapor deposition (CVD). The I-V data measured at various temperatures indicate that at relatively high current, the heterojunction forward current is dominated by thermionic emission of carriers and can be expressed as exp(-qV_bi/kT ) exp(V/ηkT), where V_bi is the built-in voltage of the heterojunction and η(=1.3) is a constant independent of voltage and temperature. At lower current, defect-assisted multitunneling current dominates. The effective density of states and the density-of-states effective mass of electrons in the conduction band of SiC are estimated to be 1.7×10²¹ cm ^-3 and 0.78m₀, respectively. This study indicates that the β-SiC/Si heterojunction is a promising system for heterojunction (HJ) devices such as SiC-emitter heterojunction bipolar transistors (HBTs)     

1/f noise in MODFETs at low drain bias

The 1/f noise in normally-on MODFETs biased at low drain voltages is investigated. The experimentally observed relative noise in the drain current S_I/I² versus the effective gate voltage V_G=V_GS-V_off shows three regions which are explained. The observed dependencies are S_I/I²∝V_G ^m with the exponents m=-1, -3, 0 with increasing values of V_G. The model explains m =-1 as the region where the resistance and the 1/f noise stem from the 2-D electron gas under the gate electrode; the region with m=0 at large V_G or V_GS≅0 is due to the dominant contribution of the series resistance. In the region at intermediate V_G , m=-3, the 1/f noise stems from the channel under the gate electrode, and the drain-source resistance is already dominated by the series resistance     

Automatic VT extractors based on ann×n2 MOS transistor array and theirapplication

The development of incremental and decremental V_T extractors based on the square-law characteristic and an n ×n² transistor array is described. Different implementations have been discussed and the effect of nonidealities such as mobility reduction, channel-length modulation, mismatch, and body effect has been analyzed. Besides automatic V_T extraction, parameter K of an MOS transistor can also be extracted automatically using the V_T extractor, without any need of calculation and delay, and the extracted V_T and K are, respectively, in voltage and current. Experimental results are presented and indicate that the differences between extracted values using the V_T extractor and the most popular numerical method are as small as 0.15% and 0.064%. Additional applications, such as in level shifting, temperature compensation, and temperature measurement, where the V_T extractor can be used either as a PTAT sensor or as a centigrade sensor, are presented     

Yttrium oxide/silicon dioxide: a new dielectric structure forVLSI/ULSI circuits

Electrical characteristics of Al/yttrium oxide (~260 Å)/silicon dioxide (~40 Å)/Si and Al/yttrium oxide (~260 Å)/Si structures are described. The Al/Y₂O₃/SiO₂/Si (MYOS) and Al/Y₂ O₃/Si (MYS) capacitors show very well-behaved I-V characteristics with leakage current density <10^-10 A/cm² at 5 V. High-frequency C- V and quasistatic C-V characteristics show very little hysteresis for bias ramp rate ranging from 10 to 100 mV/s. The average interface charge density (Q_f+Q _it) is ~6×10¹¹/cm² and interface state density D_it is ~10¹¹ cm^-2-eV^-1 near the middle of the bandgap of silicon. The accumulation capacitance of this dielectric does not show an appreciable frequency dependence for frequencies varying from 10 kHz to 10 MHz. These electrical characteristics and dielectric constant of ~17-20 for yttrium oxide on SiO₂/Si make it a variable dielectric for DRAM storage capacitors and for decoupling capacitors for on-chip and off-chip applications     

Importance of source and drain resistance to the maximum fT of millimeter-wave MODFETs

The usual approximate expression for measured f_T =[g_m/2π (C_gs+C _gd)] is inadequate. At low drain voltages just beyond the knee of the DC I-V curves, where intrinsic f _t is a maximum for millimeter-wave MODFETs, the high values of C_gd and G_ds combine with the high g_m to make terms involving the source and drain resistance significant. It is shown that these resistances can degrade the measured f_T of a 0.30-μm GaAs-AlGaAs MODFET from an intrinsic maximum f_T value of 73 GHz to a measured maximum value of 59 GHz. The correct extraction of maximum f_T is essential for determining electron velocity and optimizing low-noise performance