Charge trapping and dielectric reliability of SiO/sub 2/-Al/sub 2/O/sub 3/ gate stacks with TiN electrodes

A detailed study on charge trapping and dielectric reliability of SiO/sub 2/-Al/sub 2/O/sub 3/ gate stacks with TiN electrodes has been carried out. Due to the inherent asymmetry of the dual layer stack all electrical properties studied were found to be strongly polarity dependent. The gate current is strongly reduced for injection from the TiN (gate) electrode compared to injection from the n-type Si substrate. For substrate injection, electron trapping occurs in the bulk of the Al/sub 2/O/sub 3/ film, whereas for gate injection mainly hole trapping near the Si substrate is observed. Furthermore, no significant interface state generation is evident for substrate injection. In case of gate injection a rapid build up of interface states occurs already at small charge fluence (q/sub inj/ /spl sim/ 1 mC/cm/sup 2/). Dielectric reliability is consistent with polarity-dependent defect generation. For gate injection the interfacial layer limits the dielectric reliability and results in low Weibull slopes independent of the Al/sub 2/O/sub 3/ thickness. In the case of substrate injection, reliability is limited by the bulk of the Al/sub 2/O/sub 3/ layer leading to a strong thickness dependence of the Weibull slope as expected by the percolation model.     

SiO/sub 2//AlGaN/InGaN/GaN MOSDHFETs

The characteristics of a novel nitride based field-effect transistor combining SiO/sub 2/ gate isolation and an AlGaN/InGaN/GaN double heterostructure design (MOSDHFET) are reported. The double heterostructure design with InGaN channel layer significantly improves confinement of the two-dimensional (2-D) electron gas and compensates strain modulation in AlGaN barrier resulting from the gate voltage modulations. These decrease the total trapped charge and hence the current collapse. The combination of the SiO/sub 2/ gate isolation and improved carrier confinement/strain management results in current collapse free MOSDHFET devices with gate leakage currents about four orders of magnitude lower than those of conventional Schottky gate HFETs.     

High-k Al/sub 2/O/sub 3/ gate dielectrics prepared by oxidation of aluminum film in nitric acid followed by high-temperature annealing

A simple, cost-effective, and room temperature process was proposed to prepare high-k gate dielectrics. An aluminum oxide (Al/sub 2/O/sub 3/) gate dielectric was prepared by oxidation of ultrathin Al film in nitric acid (HNO/sub 3/) at room temperature then followed by high-temperature annealing in O/sub 2/ or N/sub 2/. The substrate injection current behavior and interface trap-induced capacitance were introduced to investigate the interfacial property between the gate dielectric and Si substrate. Al/sub 2/O/sub 3/ gate dielectric MOS capacitors with and without initial SiO/sub 2/ layers were characterized. It was shown that the Al/sub 2/O/sub 3/ gate dielectrics with initial oxide exhibit better electrical properties than those without. The 650/spl deg/C N/sub 2/-POA Al/sub 2/O/sub 3/-SiO/sub 2/ sample with an equivalent oxide thickness of 18 /spl Aring/ exhibits three orders of magnitude reduction in gate leakage current in comparison with the conventional thermal SiO/sub 2/ sample.     

Low-frequency noise in submicrometer MOSFETs with HfO/sub 2/, HfO/sub 2//Al/sub 2/O/sub 3/ and HfAlO/sub x/ gate stacks

Low-frequency noise measurements were performed on p- and n-channel MOSFETs with HfO/sub 2/, HfAlO/sub x/ and HfO/sub 2//Al/sub 2/O/sub 3/ as the gate dielectric materials. The gate length varied from 0.135 to 0.36 /spl mu/m with 10.02 /spl mu/m gate width. The equivalent oxide thicknesses were: HfO/sub 2/ 23 /spl Aring/, HfAlO/sub x/ 28.5 /spl Aring/ and HfO/sub 2//Al/sub 2/O/sub 3/ 33 /spl Aring/. In addition to the core structures with only about 10 /spl Aring/ of oxide between the high-K dielectric and silicon substrate, there were "double-gate oxide" structures where an interfacial oxide layer of 40 /spl Aring/ was grown between the high-K dielectric and Si. DC analysis showed low gate leakage currents in the order of 10/sup -12/ A(2-5 /spl times/ 10/sup -5/ A/cm/sup 2/) for the devices and, in general, yielded higher threshold voltages and lower mobility values when compared to the corresponding SiO/sub 2/ devices. The unified number-mobility fluctuation model was used to account for the observed 1/f noise and to extract the oxide trap density, which ranged from 1.8 /spl times/ 10/sup 17/ cm/sup -3/ eV/sup -1/ to 1, 3 /spl times/ 10/sup 19/ cm/sup -3/ eV/sup -1/ somewhat higher compared to conventional SiO/sub 2/ MOSFETs with the similar device dimensions. There was no evidence of single electron switching events or random telegraph signals. The aim of this paper is to present a general discussion on low-frequency noise characteristics of the three different high-K/gate stacks, relative comparison among them and to the Si-SiO/sub 2/ system.     

Low-frequency noise in submicrometer MOSFETs with HfO/sub 2/, HfO/sub 2//Al/sub 2/O/sub 3/ and HfAlO/sub x/ gate stacks

Low-frequency noise measurements were performed on p- and n-channel MOSFETs with HfO/sub 2/, HfAlO/sub x/ and HfO/sub 2//Al/sub 2/O/sub 3/ as the gate dielectric materials. The gate length varied from 0.135 to 0.36 /spl mu/m with 10.02 /spl mu/m gate width. The equivalent oxide thicknesses were: HfO/sub 2/ 23 /spl Aring/, HfAlO/sub x/ 28.5 /spl Aring/ and HfO/sub 2//Al/sub 2/O/sub 3/ 33 /spl Aring/. In addition to the core structures with only about 10 /spl Aring/ of oxide between the high-/spl kappa/ dielectric and silicon substrate, there were "double-gate oxide" structures where an interfacial oxide layer of 40 /spl Aring/ was grown between the high-/spl kappa/ dielectric and Si. DC analysis showed low gate leakage currents in the order of 10/sup -12/A(2-5/spl times/10/sup -5/ A/cm/sup 2/) for the devices and, in general, yielded higher threshold voltages and lower mobility values when compared to the corresponding SiO/sub 2/ devices. The unified number-mobility fluctuation model was used to account for the observed 1/f noise and to extract the oxide trap density, which ranged from 1.8/spl times/10/sup 17/ cm/sup -3/eV/sup -1/ to 1.3/spl times/10/sup 19/ cm/sup -3/eV/sup -1/, somewhat higher compared to conventional SiO/sub 2/ MOSFETs with the similar device dimensions. There was no evidence of single electron switching events or random telegraph signals. The aim of this paper is to present a general discussion on low-frequency noise characteristics of the three different high-/spl kappa//gate stacks, relative comparison among them and to the Si--SiO/sub 2/ system.     

Physically based quantum-mechanical compact model of MOS devices substrate-injected tunneling current through ultrathin (EOT /spl sim/ 1 nm) SiO/sub 2/ and high-/spl kappa/ gate stacks

Building on a previously presented compact gate capacitance (C/sub g/-V/sub g/) model, a computationally efficient and accurate physically based compact model of gate substrate-injected tunneling current (I/sub g/-V/sub g/) is provided for both ultrathin SiO/sub 2/ and high-dielectric constant (high-/spl kappa/) gate stacks of equivalent oxide thickness (EOT) down to /spl sim/ 1 nm. Direct and Fowler-Nordheim tunneling from multiple discrete subbands in the strong inversion layer are addressed. Subband energies in the presence of wave function penetration into the gate dielectric, charge distributions among the subbands subject to Fermi-Dirac statistics, and the barrier potential are provided from the compact C/sub g/-V/sub g/ model. A modified version of the conventional Wentzel-Kramer-Brillouin approximation allows for the effects of the abrupt material interfaces and nonparabolicities in complex band structures of the individual dielectrics on the tunneling current. This compact model produces simulation results comparable to those obtained via computationally intense self-consistent Poisson-Schro/spl uml/dinger simulators with the same MOS devices structures and material parameters for 1-nm EOTs of SiO/sub 2/ and high-/spl kappa//SiO/sub 2/ gate stacks on (100) Si, respectively. Comparisons to experimental data for MOS devices with metal and polysilicon gates, ultrathin dielectrics of SiO/sub 2/, Si/sub 3/N/sub 4/, and high-/spl kappa/ (e.g., HfO/sub 2/) gate stacks on (100) Si with EOTs down to /spl sim/ 1-nm show excellent agreement.     

Carrier mobility in p-MOSFET with atomic-layer-deposited Si-nitride/SiO/sub 2/ stack gate dielectrics

P/sup +/-poly-Si gate MOS transistors with atomic-layer-deposited Si-nitride/SiO/sub 2/ stack gate dielectrics (EOT=2.50 nm) have been fabricated. Similar to the reference samples with SiO/sub 2/ gate dielectrics (T/sub ox/=2.45 nm), clear saturation characteristics of drain current are obtained for the samples with stack gate dielectrics. Identical hole-effective mobility is obtained for the samples with the SiO/sub 2/ and the stack gate dielectrics. The maximum value of hole-effective mobility is the same (54 cm/sup 2//Vs) both for the stack and the SiO/sub 2/ samples. Hot carrier-induced mobility degradation in transistors with the stack gate dielectrics was found to be identical to that in transistors with the SiO/sub 2/ gate dielectrics. In addition to the suppression of boron penetration, better TDDB characteristics, and soft breakdown free phenomena for the stack dielectrics (reported previously), the almost equal effective mobility (with respect to that of SiO/sub 2/ dielectrics) has ensured the proposed stack gate dielectrics to be very promising for sub-100-nm technology generations.     

Effects of interstitial oxygen defects at HfO/sub x/N/sub y//Si interface on electrical characteristics of MOS devices

Effects of the defects at high-/spl kappa/ dielectric/Si interface on the electrical characteristics of MOS devices are important issues. To study these issues, a low defect (denuded zone) at Si surface was formed by a high-temperature annealing in hydrogen atmosphere in this paper. Our results reveal that HfO/sub x/N/sub y/ demonstrates significant improvement on the electrical properties of MOS devices due to its low amount of the interstitial oxygen [O/sub i/] and the crystal-originated particles defects as well as small surface roughness at HfO/sub x/N/sub y//Si interface. The current-conduction mechanism of the HfO/sub x/N/sub y/ film at the low- and high-electrical field and high-temperature (T>100/spl deg/C) is dominated by Schottky emission and Frenkel-Poole (FP) emission, respectively. The trap energy level involved in FP conduction was estimated to be around 0.5eV. Reduced gate leakage current, stress-induced leakage current and defect generation rate, attributable to the reduction of defects at HfO/sub x/N/sub y//Si interface, were observed for devices with denuded zone. The variable rise and fall time bipolar-pulse-induced current technique was used to determine the energy distribution of interface trap density (D/sub it/). The results exhibit that relatively low D/sub it/ can be attributed to the reduction of defects at Si surface. By using denuded zone at the Si surface, HfO/sub x/N/sub y/ has demonstrated significant improvement on electrical properties as compared to SiO/sub x/N/sub y/.     

Ultrathin Al/sub 2/O/sub 3/ and HfO/sub 2/ gate dielectrics on surface-nitrided Ge

We have studied ultrathin Al/sub 2/O/sub 3/ and HfO/sub 2/ gate dielectrics on Ge grown by ultrahigh vacuum-reactive atomic-beam deposition and ultraviolet ozone oxidation. Al/sub 2/O/sub 3/-Ge gate stack had a t/sub eq//spl sim/23 /spl Aring/, and three orders of magnitude lower leakage current compared to SiO/sub 2/. HfO/sub 2/-Ge allowed even greater scaling, achieving t/sub eq//spl sim/11 /spl Aring/ and six orders of magnitude lower leakage current compared to SiO/sub 2/. We have carried out a detailed study of cleaning conditions for the Ge wafer, dielectric deposition condition, and anneal conditions and their effect on the electrical properties of metal-gated dielectric-Ge capacitors. We show that surface nitridation is important in reducing hysteresis, interfacial layer formation and leakage current. However, surface nitridation also introduces positive trapped charges and/or dipoles at the interface, resulting in significant flatband voltage shifts, which are mitigated by post-deposition anneals.     

Origin of the threshold voltage instability in SiO/sub 2//HfO/sub 2/ dual layer gate dielectrics

The magnitude of the V/sub T/ instability in conventional MOSFETs and MOS capacitors with SiO/sub 2//HfO/sub 2/ dual-layer gate dielectrics is shown to depend strongly on the details of the measurement sequence used. By applying time-resolved measurements (capacitance-time traces and charge-pumping measurements), it is demonstrated that this behavior is caused by the fast charging and discharging of preexisting defects near the SiO/sub 2//HfO/sub 2/ interface and in the bulk of the HfO/sub 2/ layer. Based on these results, a simple defect model is proposed that can explain the complex behavior of the V/sub T/ instability in terms of structural defects as follows. 1) A defect band in the HfO/sub 2/ layer is located in energy above the Si conduction band edge. 2) The defect band shifts rapidly in energy with respect to the Fermi level in the Si substrate as the gate bias is varied. 3) The rapid energy shifts allows for efficient charging and discharging of the defects near the SiO/sub 2//HfO/sub 2/ interface by tunneling.     

La/sub 2/O/sub 3//Si/sub 0.3/Ge/sub 0.7/ p-MOSFETs with high hole mobility and good device characteristics

We have studied high-k La/sub 2/O/sub 3/ p-MOSFETs on Si/sub 0.3/Ge/sub 0.7/ substrate. Nearly identical gate oxide current, capacitance density, and time-dependent dielectric breakdown (TDDB) are obtained for La/sub 2/O/sub 3//Si and La/sub 2/O/sub 3//Si/sub 0.3/Ge/sub 0.7/ devices, indicating excellent Si/sub 0.3/Ge/sub 0.7/ quality without any side effects. The measured hole mobility in nitrided La/sub 2/O/sub 3//Si p-MOSFETs is 31 cm/sup 2//V-s and comparable with published data in nitrided HfO/sub 2//Si p-MOSFETs. In sharp contrast, a higher mobility of 55 cm/sup 2//V-s is measured in La/sub 2/O/sub 3//Si/sub 0.3/Ge/sub 0.7/ p-MOSFET, an improvement by 1.8 times compared with La/sub 2/O/sub 3//Si control devices. The high mobility in Si/sub 0.3/Ge/sub 0.7/ p-MOSFETs gives another step for integrating high-k gate dielectrics into the VLSI process.     

Successful enhancement of lifetime for SiO/sub 2/ on 4H-SiC by N/sub 2/O anneal

Time-dependent dielectric breakdown (TDDB) measurement by constant current stress has been performed to investigate the oxide (SiO/sub 2/) reliability grown on n-type 4H-SiC. At 300K, the intrinsic injected charge to breakdown (Q/sub BD/) of thermally grown SiO/sub 2/ in wet O/sub 2/ ambience is about 0.1 C/cm/sup 2/, whereas N/sub 2/O anneal after the thermal oxidation results in the drastic improvement of the reliability. The intrinsic Q/sub BD/ of N/sub 2/O annealed SiO/sub 2/ is found to be 10 C/cm/sup 2/, which is two orders of magnitude larger than that of the oxide without N/sub 2/O anneal, suggesting that the quality of SiO/sub 2/ and/or SiO/sub 2//SiC interface is improved. TDDB measurement has been also performed at high temperatures up to 423 K. The activation energy of oxide lifetime estimated from time to failure of 80% is 0.35 and 0.10 eV for the oxide with and without N/sub 2/O anneal, respectively.     

Film Properties of MoSi/sub 2/ and Their Application to Self-Aligned MoSi/sub 2/ Gate MOSFET

Molybdenum silicide (MoSi/sub 2/) gate technology has been extensively investigated in conjunction with MOS device performance and reliability. Features of the MoSi/sub 2/) gate technology are to realize a low resistivity of 1 X 10/sup -4/ Omega · cm for both gate and interconnection, and to give rise to higher reliability under both positive and negative bias stress of 2 MV/cm at 250/spl deg/C. Problems on the ohmic contact between MoSi/sub 2/ and single-crystal substrates are not completely solved yet, particularly when the device is processed at high temperature after MoSi/sub 2/ deposition.     

Memory characterization of SiGe quantum dot flash memories with HfO/sub 2/ and SiO/sub 2/ tunneling dielectrics

In this study, we have developed a SiGe dot floating-gate flash memory with high-K dielectric (HfO/sub 2/) tunneling oxide. Using SiGe dots and HfO/sub 2/ tunneling oxide, a low program/erase voltage can be achieved, along with good endurance and charge retention characteristics as compared to the SiGe dots with a SiO/sub 2/ tunneling oxide. We have also examined the impact of Ge concentration in the SiGe dots on charge retention time. This demonstrates that the SiGe dots with HfO/sub 2/ tunneling oxide can be used as the floating gate to replace SiGe dots with SiO/sub 2/ tunneling oxide and have a high potential for further scaling of floating gate memory devices.     

The electrical properties of HfO/sub 2/ dielectric on germanium and the substrate doping effect

MOS devices built on various germanium substrates, with chemical vapor deposited (CVD) or physical vapor deposited (PVD) HfO/sub 2/ high-/spl kappa/ dielectric and TaN gate electrode, were fabricated. The electrical properties of these devices, including the capacitance equivalent thickness (CET), gate leakage current density (J/sub g/), slow trap density (D/sub st/), breakdown voltage (V/sub bd/), capacitance-voltage (C-V) frequency dispersion, and thermal stability, are investigated. The process conditions such as surface nitridation treatment, O/sub 2/ introduction in CVD process and postdeposition anneal temperature in PVD process, exhibit significant impacts on the devices' electrical properties. The devices built on germanium substrates with different dopant types and doping concentrations show remarkable variations in electrical characteristics, revealing the role of the substrate doping in the reactions occurring at the dielectric/Ge interface, which can significantly affect the interfacial layer formation and Ge updiffusion. A possible mechanism is suggested that two competing processes (oxide growth and desorption) take place at the interface, which govern the formation of the interfacial layer. Doped p-type (Ga) and n-type (Sb) impurities may enhance the different process at the interface and cause the variations in the interfacial layer formation and so on in electrical properties. The high diffusivities of impurities and Ge atoms in Ge and the induced structural defects near the substrate surface could be one possible cause for this doping effect. As another behavior of the substrate doping effect, Ge n-MOS and p-MOS stacks show quite different C-V characteristics after high temperature postmetallization anneal treatments, which can be explained by the same mechanism.     

ScN/sub x/ gate on atomic layer deposited HfO/sub 2/ and effect of high-pressure wet post deposition annealing

For nMOS devices with HfO/sub 2/, a metal gate with a very low workfunction is necessary. In this letter, the effective workfunction (/spl Phi//sub m,eff/) values of ScN/sub x/ gates on both SiO/sub 2/ and atomic layer deposited (ALD) HfO/sub 2/ are evaluated. The ScN/sub x//SiO/sub 2/ samples have a wide range of /spl Phi//sub m,eff/ values from /spl sim/ 3.9 to /spl sim/ 4.7 eV, and nMOS-compatible /spl Phi//sub m,eff/ values can be obtained. However, the ScN/sub x/ gates on conventional post deposition-annealed HfO/sub 2/ show a relatively narrow range of /spl Phi//sub m,eff/ values from /spl sim/ 4.5 to /spl sim/ 4.8 eV, and nMOS-compatible /spl Phi//sub m,eff/ values cannot be obtained due to the Fermi-level pinning (FLP) effect. Using high-pressure wet post deposition annealing, we could dramatically reduce the extrinsic FLP. The /spl Phi//sub m,eff/ value of /spl sim/ 4.2 eV was obtained for the ScN/sub x/ gate on the wet-treated HfO/sub 2/. Therefore, ScN/sub x/ metal gate is a good candidate for nMOS devices with ALD HfO/sub 2/.     

Thermal stability of Hf/sub x/Ta/sub y/N metal gate electrodes for advanced MOS devices

In this letter, the composition effects of hafnium (Hf) and tantalum (Ta) in Hf/sub x/Ta/sub y/N metal gate on the thermal stability of MOS devices were investigated. The work function of the Hf/sub x/Ta/sub y/N metal gate can reach a value of /spl sim/4.6 eV (midgap of silicon) by suitably adjusting the Hf and Ta compositions. In addition, with a small amount of Hf incorporated into a TaN metal gate, excellent thermal stability of electrical properties, including the work function, the equivalent oxide thickness, interface trap density and defect generation rate characteristics, can be achieved after a post-metal anneal up to 950/spl deg/C for 45 s. Experimental results indicate that Ta-rich Hf/sub x/Ta/sub y/N is a promising metal gate for advanced MOS devices.     

Low-frequency noise in TaSiN/HfO/sub 2/ nMOSFETs and the effect of stress-relieved preoxide interfacial layer

Low-frequency noise characteristics are reported for TaSiN-gated n-channel MOSFETs with atomic-layer deposited HfO/sub 2/ on thermal SiO/sub 2/ with stress-relieved preoxide (SRPO) pretreatment. For comparison, control devices were also included with chemical SiO/sub 2/ resulting from standard Radio Corporation of America clean process. The normalized noise spectral density values for these devices are found to be lower when compared to reference poly Si gate stack with similar HfO/sub 2/ dielectric. Consequently, a lower oxide trap density of /spl sim/4/spl times/10/sup 17/ cm/sup -3/eV/sup -1/ is extracted compared to over 3/spl times/10/sup 18/ cm/sup -3/eV/sup -1/ values reported for poly Si devices indicating an improvement in the high-/spl kappa/ and interfacial layer quality. In fact, this represents the lowest trap density values reported to date on HfO/sub 2/ MOSFETs. The peak electron mobility measured on the SRPO devices is over 330 cm/sup 2//V/spl middot/s, much higher than those for equivalent poly Si or metal gate stacks. In addition, the devices with SRPO SiO/sub 2/ are found to exhibit at least /spl sim/10% higher effective mobility than RCA devices, notwithstanding the differences in the high-/spl kappa/ and interfacial layer thicknesses. The lower Coulomb scattering coefficient obtained from the noise data for the SRPO devices imply that channel carriers are better screened due to the presence of SRPO SiO/sub 2/, which, in part, contributes to the mobility improvement.     

Lateral nonuniformity of effective oxide charges in MOS capacitors with Al/sub 2/O/sub 3/ gate dielectrics

The high-frequency Terman's method for interface-trap-density (D/sub it/) extraction is used to examine the lateral nonuniformity (LNU) of effective oxide charges in MOS capacitors. The two-parallel-subcapacitor model is constructed to simulate LNU charges, and it was shown that the value of the found effective D/sub it/ appears negative as the LNU occurs in the gate oxide. This technique was first used to examine the effective oxide charge distribution in Al/sub 2/O/sub 3/ high-k gate dielectrics prepared by anodic oxidation and nitric-acid oxidation. It was found that the LNU effect in Al/sub 2/O/sub 3/ is sensitive to oxidation mechanisms and can be avoided by using an appropriate oxidation process. The proposed technique is useful for the preparation and reliability improvement of high-k gate dielectrics.     

Characteristics of Al/sub 2/O/sub 3//AllnN /GaN MOSHEMT

InAlN/GaN is a new heterostructure system for HEMTs with thin barrier layers and high channel current densities well above 1 A/mm. To improve the leakage characteristics of such thin-barrier devices, AlInN/GaN MOSHEMT devices with a 11 nm InAlN barrier and an additional 5 nm Al₂O₃ barrier (deposited by ALD) were fabricated and evaluated. Gate leakage in reverse direction could be reduced by one order of magnitude and the forward gate voltage swing increased to 4 V without gate breakdown. Compared to HEMT devices of similar geometry, no degradation of the current gain cutoff frequency was observed. The results showed that InAlN/GaN FETs with high channel current densities can be realised with low gate leakage characteristics and high structural aspect ratio by insertion of a thin Al₂O ₃ gate dielectric layer