Performance analysis of 20 nm gate-length In0.2Al0.8N/GaN HEMT with Cu-gate having a remarkable high ION/IOFF ratio

Abstract： We propose a new structure of InxAll-xN/GaN high electron mobility transistor （HEMT） with gate length of 20 nm. The threshold voltage of this HEMT is achieved as -0.472 V. In this device the InA1N barrier layer is intentionally n-doped to boost the ION/IOFF ratio. The InAlN layer acts as donor barrier layer for this HEMT which exhibits an ION = 10-4.3 A and a very low IOFF = 10-14.4 A resulting in an ION/IoFF ratio of 1010.1. We compared our obtained results with the conventional InAlN/GaN HEMT device having undoped barrier and found that the proposed device has almost l0s times better ION/IOFF ratio. Further, the mobility analysis in GaN channel of this proposed HEMT structure along with DC analysis, C-V and conductance characteristics by using small-signal analysis are also presented in this paper. Moreover, the shifts in threshold voltage by DIBL effect and gate leakage current in the proposed HEMT are also discussed. InAlN was chosen as the most preferred barrier layer as a replacement of AlGaN for its excellent thermal conductivity and very good scalability.     

蓝宝石衬底上槽栅型X波段增强型AlGaN/GaN HEMT

研制了一款X波段增强型AlGaN/GaN高电子迁移率晶体管(HEMT)。在3英寸(1英寸=2.54 cm)蓝宝石衬底上采用低损伤栅凹槽刻蚀技术制备了栅长为0.3μm的增强型AlGaN/GaN HEMT。所制备的增强型器件的阈值电压为0.42 V,最大跨导为401 mS/mm,导通电阻为2.7Ω·mm。器件的电流增益截止频率和最高振荡频率分别为36.1和65.2 GHz。在10 GHz下进行微波测试,增强型AlGaN/GaN HEMT的最大输出功率密度达到5.76 W/mm,最大功率附加效率为49.1%。在同一材料上制备的耗尽型器件最大输出功率密度和最大功率附加效率分别为6.16 W/mm和50.2%。增强型器件的射频特性可与在同一晶圆上制备的耗尽型器件相比拟。     

标准氟离子注入实现增强型GaN基功率器件

介绍了一种直接利用离子注入机对AlGaN/GaN高电子迁移率晶体管(HEMT)器件的栅下进行氟(F)离子注入的方法,成功实现了增强型HEMT器件,阈值电压从耗尽型器件的-2.6V移动到增强型器件的+1.9V.研究了注入剂量对器件性能的影响,研究发现随着注入剂量的不断增加,阈值电压不断地正向移动,但由于存在高能F离子的注入损伤,器件的正向栅极漏电随着注入剂量的增加而不断上升,阈值电压正向移动也趋于饱和.因此,提出采用在AlGaN/GaN异质结表面沉积栅介质充当能量吸收层,降低离子注入过程中的损伤,成功实现了阈值电压为+3.3 V,饱和电流密度约为200 mA/mm,同时具有一个较高的开关比109的增强型金属-绝缘层-半导体HEMT (MIS-HEMT)器件.     

30 nm T-gate enhancement-mode InAlN/AlN/GaN HEMT on SiC substratesfor future high power RF applications

The DC and RF performance of 30 nm gate length enhancement mode (E-mode) InAlN/AlN/GaN high electron mobility transistor (HEMT) on SiC substrate with heavily doped source and drain region have been investigated using the Synopsys TCAD tool. The proposed device has the features of a recessed T-gate structure, InGaN back barrier and Al₂O₃ passivated device surface. The proposed HEMT exhibits a maximum drain current density of 2.1 A/mm, transconductance g_m of 1050 mS/mm, current gain cut-off frequency f_t of 350 GHz and power gain cut-off frequency f_max of 340 GHz. At room temperature the measured carrier mobility (μ), sheet charge carrier density (n_s) and breakdown voltage are 1580 cm²/(V·s), 1.9×10¹³ cm^-2, and 10.7 V respectively. The superlatives of the proposed HEMTs are bewitching competitor or future sub-millimeter wave high power RF VLSI circuit applications.     

一种P-GaN栅结合混合帽层结构的HEMT器件

为了进一步提升P-GaN栅HEMT器件的阈值电压和击穿电压,提出了一种具有P-GaN栅结合混合掺杂帽层结构的氮化镓高电子迁移率晶体管(HEMT)。新器件利用混合掺杂帽层结构,调节整体极化效应,可以进一步耗尽混合帽层下方沟道区域的二维电子气,提升阈值电压。在反向阻断状态下,混合帽层可以调节栅极右侧电场分布,改善栅边电场集中现象,提高器件的击穿电压。利用Sentaurus TCAD进行仿真,对比普通P-GaN栅增强型器件,结果显示,新型结构器件击穿电压由593 V提升至733 V,增幅达24%,阈值电压由0.509 V提升至1.323 V。     

Dual-Gate E/E- and E/D-Mode AlGaAs/InGaAs pHEMTs for Microwave Circuit Applications

In this paper, we developed dual-gate enhancement/enhancement-mode (E/E-mode) and enhancement/depletion-mode (E/D-mode) AlGaAs/InGaAs pHEMTs for high-voltage and high-power device applications. These dual-gate devices had a higher breakdown voltage (V_br) and maximum oscillation frequency (f_max). This could be obtained because there were two depletion regions, and the total electrical field was shared between the two regions, leading to lower output conductance (g_o) and lower gate-to-drain capacitance (C_gd). The dual-gate device can be operated at a higher drain-to-source voltage (V_ds), resulting in better linear gain and output power performance, as compared to a conventional single-gate E-mode GaAs pHEMT device. The maximum oscillation frequency obtained using the dual-gate E/E-mode device increased from 78 to 123 GHz. When operated at 2.4 GHz, the maximum RF output power of the single-gate E-mode and dual-gate E/D-mode devices increased from 636 to 810 mW/mm, respectively. We also produced a 2.4-GHz high-gain and high-power density two-stage power amplifier using dual-gate E/E and E/D-mode transistors. A linear gain of 40 dB and a maximum output power of 24 dBm were obtained.     

Compact analytical model for single gate AlInSb/InSb high electron mobility transistors

We have developed a 2D analytical model for the single gate Al In Sb/In Sb HEMT device by solving the Poisson equation using the parabolic approximation method.The developed model analyses the device performance by calculating the parameters such as surface potential,electric field distribution and drain current.The high mobility of the Al In Sb/In Sb quantum makes this HEMT ideal for high frequency,high power applications.The working of the single gate Al In Sb/In Sb HEMT device is studied by considering the variation of gate source voltage,drain source voltage,and channel length under the gate region and temperature.The carrier transport efficiency is improved by uniform electric field along the channel and the peak values near the source and drain regions.The results from the analytical model are compared with that of numerical simulations(TCAD) and a good agreement between them is achieved.     

具有栅介质电场屏蔽作用的新型GaN纵向槽栅MOSFET器件设计

基于氮化镓(GaN)等宽禁带(WBG)半导体的金氧半场效应晶体管(MOSFET)器件在关态耐压下,栅介质中存在与宽禁带半导体临界击穿电场相当的大电场,致使栅介质在长期可靠性方面受到挑战。为了避免在GaN器件中使用尚不成熟的p型离子注入技术,提出了一种基于选择区域外延技术制备的新型GaN纵向槽栅MOSFET,可通过降低关态栅介质电场来提高栅介质可靠性。提出了关态下的耗尽区结电容空间电荷竞争模型,定性解释了栅介质电场p型屏蔽结构的结构参数对栅介质电场的影响规律及机理,并通过权衡器件性能与可靠性的关系,得到击穿电压为1 200 V、栅介质电场仅0.8 MV/cm的具有栅介质长期可靠性的新型GaN纵向槽栅MOSFET。     

用于功率变换的高击穿增强型AlGaN/GaN HEMTs

首次采用CF4等离子体技术实现可用于功率变换的增强性AlGaN/GaN功率器件。实验结果表明,当AlGaN/GaN器件经功率150W和时间150s等离子体轰击后,器件阈值电压从-4V被调制约为0.5V,表现为增强型。当漂移区LGD从5μm增加到15μm,器件的击穿电压从50V迅速增大到400V,电压增幅达350V。采用长度为3μm源场板结构将器件击穿电压明显地提高,击穿电压增加约为475V,且有着比硅基器件更低的比导通电阻,约为2.9mΩ.cm2。器件模拟结果表明,因源场板在远离栅边缘的漂移区中引入另一个电场强度为1.5MV/cm的电场,从而有效地释放了存在栅边缘的电场,将高达3MV/cm的电场减小至1MV/cm。微波测试结果表明,器件的特征频率fT和最大震荡频率fMAX随Vgs改变,正常工作时两参数均在千兆量级。栅宽为1mm的增强型功率管有较好的交直流和瞬态特性,正向电流约为90mA。故增强型AlGaN/GaN器件适合高压高频大功率变换的应用。     

Performance assessment and sub-threshold analysis of gate material engineered AlGaN/GaN HEMT for enhanced carrier transport efficiency

The present work explores the features of gate material engineered (GME) AlGaN/GaN high electron mobility transistor (HEMT) for enhanced carrier transport efficiency (CTE) and suppressed short channel effects (SCEs) using 2-D sub-threshold analysis and device simulation. The model accurately predicts the channel potential, electric field and sub-threshold current for the conventional and GME HEMT, taking into account the effect of work function difference of the two metal gates. This is verified by comparing the model results with the ATLAS simulation results. Further, simulation study has been extended to reflect the wide range of benefits exhibited by GME HEMT for its on-state and analog performance. The simulation results demonstrate that the GME HEMT exhibits much higher on current, lower conductance and higher transconductance as compared to the conventional HEMT due to improved CTE and reduced SCEs. This in turn has a direct bearing on the device figure of merits (FOMs) such as intrinsic gain, device efficiency and early voltage. Tuning of GME HEMT in terms of the relative lengths of the two metal gates, their work function difference and barrier layer thickness has further been carried out to enhance the drive current, transconductance and the device FOMs illustrating the superior performance of GME HEMT for future high-performance high-speed switching, digital and analog applications.     

Low-conductance drain (LCD) design of InAlAs/InGaAs/InP HEMT's

The concepts of the low-conductance drain (LCD) design approach for lattice-matched InAlAs/InGaAs/InP HEMTs are demonstrated for improved device performance. The tradeoff for LCD HEMT characteristics is a tapered current gain cutoff frequency f_t under high drain-to-source bias. This behavior is, in principle, due to the fact that the LCD approach increases the effective gate length of the HEMTs in exchange for reduced peak channel electric field. Two-dimensional PISCES simulation was used to optimize the improvements while simultaneously minimizing this undesirable effect for an LCD HEMT structure     

具有补偿埋层的槽型埋氧层SOI高压器件新结构

A new silicon-on-insulator(SOI) high-voltage MOSFET structure with a compensation layer on the trenched buried oxide layer(CL T-LDMOS) is proposed.The high density inverse interface charges at the top surface of the buried oxide layer(BOX) enhance the electric field in the BOX and a uniform surface electric field profile is obtained,which results in the enhancement of the breakdown voltage(BV).The compensation layer can provide additional P-type charges,and the optimal drift region concentration is increased in order to satisfy the reduced surface electric field(RESURF) condition.The numerical simulation results indicate that the vertical electric field in the BOX increases to 6 MV/cm and the B V of the proposed device increases by 300%in comparison to a conventional SOI LDMOS,while maintaining low on-resistance.     

High-voltage accumulation-layer UMOSFET's in 4H-SiC

A novel silicon carbide UMOSFET structure is reported. This device incorporates two new features: a self-aligned p-type implantation in the bottom of the trench that reduces the electric field in the trench oxide, and an n-type epilayer under the p-base to promote lateral current spreading into the drift region. This UMOS structure is capable of supporting the full blocking voltage of the pn junction while keeping the electric field in the gate oxide below 4 MV/cm. An accumulation channel is formed on the sidewalls of the trench by epigrowth, and the gate oxide is produced by a polysilicon oxidation process, resulting in a uniform oxide thickness over both the sidewalls and bottom of the trench. The fabricated 4H-SiC devices have a blocking voltage of 1400 V (10 μm drift region), a specific on-resistance of 15.7 mΩ-cm ² at room temperature, and a gate oxide field of 3 MV/cm     

DC and RF Characteristics of AlGaN/GaN/InGaN/GaN Double-Heterojunction HEMTs

We present the detailed dc and radio-frequency characteristics of an Al_0.3Ga_0.7N/GaN/In_0.1Ga_0.9 N/GaN double-heterojunction HEMT (DH-HEMT) structure. This structure incorporates a thin (3 nm) In_0.1Ga_0.9N notch layer inserted at a location that is 6-nm away from the AlGaN/GaN heterointerface. The In_0.1Ga_0.9N layer provides a unique piezoelectric polarization field which results in a higher potential barrier at the backside of the two-dimensional electron gas channel, effectively improving the carrier confinement and then reducing the buffer leakage. Both depletion-mode (D-mode) and enhancement-mode (E-mode) devices were fabricated on this new structure. Compared with the baseline AlGaN/GaN HEMTs, the DH-HEMT shows lower drain leakage current. The gate leakage current is also found to be reduced, owing to an improved surface morphology in InGaN-incorporated epitaxial structures. DC and small- and large-signal microwave characteristics, together with the linearity performances, have been investigated. The channel transit delay time analysis also revealed that there was a minor channel in the InGaN layer in which the electrons exhibited a mobility slightly lower than the GaN channel. The E-mode DH-HEMTs were also fabricated using our recently developed CF₄-based plasma treatment technique. The large-signal operation of the E-mode GaN-based HEMTs was reported for the first time. At 2 GHz, a 1times100 mum E-mode device demonstrated a maximum output power of 3.12 W/mm and a power-added efficiency of 49% with single-polarity biases (a gate bias of +0.5 V and a drain bias of 35 V). An output third-order interception point of 34.7 dBm was obtained in the E-mode HEMTs     

Novel structure of GaAs-based interdigital-gated HEMT plasma devices for solid-state THz wave amplifier

Theoretical analysis of potential distribution in the interdigital-gated high electron mobility transistor (HEMT) plasma wave device was carried out. The dc I–V characteristics of capacitively coupled interdigital structure showed that uniformity of electric field under the interdigital gates was improved compared to the dc-connected interdigital gate structure. Admittance measurements of capacitively coupled interdigital gate structure in the microwave region of 10–40 GHz showed the conductance modulation by drain–source voltage. These results indicate the existence of plasma wave interactions.     

High breakdown GaN HEMT with overlapping gate structure

GaN high electron mobility transistors (HEMTs) were fabricated using an overlapping-gate technique in which the drain-side edge of the metal gate overlaps on a high breakdown and high dielectric constant dielectric. The overlapping structure reduces the electric field at the drain-side gate edge, thus increasing the breakdown of the device. A record-high three-terminal breakdown figure of 570 V was achieved on a HEMT with a gate-drain spacing of 13 μm. The source-drain saturation current was 500 mA/mm and the extrinsic transconductance 150 mS/mm     

High-Performance Inversion-Type Enhancement-Mode InGaAs MOSFET With Maximum Drain Current Exceeding 1 A/mm

High-performance inversion-type enhancement- mode (E-mode) n-channel In_0.65Ga_0.35As MOSFETs with atomic-layer-deposited Al₂O₃ as gate dielectric are demonstrated. A 0.4-mum gate-length MOSFET with an Al₂O₃ gate oxide thickness of 10 nm shows a gate leakage current that is less than 5 times 10^-6 A/cm² at 4.0-V gate bias, a threshold voltage of 0.4 V, a maximum drain current of 1.05 A/mm, and a transconductance of 350 mS/mm at drain voltage of 2.0 V. The maximum drain current and transconductance scale linearly from 40 mum to 0.7 mum. The peak effective mobility is ~1550 cm²/V ldr s at 0.3 MV/cm and decreases to ~650 cm²/V ldr s at 0.9 MV/cm. The obtained maximum drain current and transconductance are all record-high values in 40 years of E-mode III-V MOSFET research.     

Influences of structure around gate-edge on high electric field strength in MISFETs with high-k gate dielectrics

In this paper, dependences of electric field strength around gate-edge in gate dielectrics of MISFETs with high-k gate dielectrics on design parameters are studied. It is newly found that locations of sidewall/gate dielectric interfaces relative to gate electrode edges are critical to electric field strength of high-k MISFETs. Electric field can be as high as 4 MV/cm, which could have large influences on the yield of large scale integrated circuits (LSIs) with high-k gate dielectrics. An explanation of this phenomenon is given by considering discontinuity in electric field at interfaces between two materials with different dielectric constants. It is clarified that an electrical potential of side and top surfaces of gate dielectrics is strongly affected by the discontinuity of electric field strength at interfaces. As a result, electric field strength around gate electrode edges critically depends on locations of sidewall/gate dielectrics interfaces relative to gate electrode edges. Based on the physical considerations, a structure, in which gate sidewalls are also made of high-k materials, is studied from the viewpoint of electric field strength around gate electrode edges. It is shown that this structure effectively suppresses electric field strength around gate edges.     

Undoped-Body Extremely Thin SOI MOSFETs With Back Gates

We present a detailed study of gate length scalability and device performance of undoped-body extremely thin silicon-on-insulator (ETSOI) MOSFETs with back gates. We show that short channel control improves with the application of back bias via a decrease in the electrostatic scaling length as the subthreshold charges move toward the front gate. We demonstrate that, even for undoped ETSOI devices with ~8-nm SOI thickness, the improvement in short channel control with the application of a back bias translates to 10% higher drive current, 10% shorter gate lengths, and, consequently, 20% lower extrinsic gate delay at a fixed off-state current of 100 nA/mum and a back oxide electric field of 1.5 MV/cm (0.5 MV/cm SOI field).     

RESURF AlGaN/GaN HEMT for high voltage power switching

A novel HEMT configuration based on the RESURF technique is proposed for very high voltage power switching applications. It employs a p-n junction below the 2-DEG channel and two field plates, one extending from the gate and the other from the drain, to distribute the electric field over the gate to drain separation. 2-D simulations indicate a breakdown voltage >1 KV at on-resistance of ~1 mΩ·cm² (neglecting contact resistances) for the device