Substrate noise coupling through planar spiral inductor

While precious studies on substrate coupling focused mostly on noise induced through drain-bulk capacitance, substrate coupling from planar spiral inductors at radiofrequency (RF) via the oxide capacitance has not been reported. This paper presents the experimental and simulation results of substrate noise induced through planar inductors. Experimental and simulation results reveal that isolation between inductor and noise source is less than -30 dB at 1 GHz. Separation by distance reduces coupling by less than 2 dB in most practical cases. Practical examples reveal an obstacle in integrating RF tuned-gain amplifier with sensitive RF receiver circuits on the same die. Simulation results indicate that hollow inductors have advantages not only in having a higher self-resonant frequency, but also in reducing substrate noise as compared to conventional inductors. The effectiveness of using a broken guard ring in reducing inductor induced substrate noise is also examined     

Reconfigurable SiGe Low-Noise Amplifiers With Variable Miller Capacitance

A new input matching method making use of shunt-shunt feedback capacitance is introduced. Based on the new input matching method, reconfigurable SiGe low-noise amplifiers (LNAs) by varying shunt-shunt feedback capacitance are proposed. Two approaches are used to vary the shunt-shunt feedback capacitance. One approach is to switch between two different bias currents while the other is to use a series combination of a switch and a capacitor. Miniaturized fully monolithic reconfigurable SiGe LNAs without emitter degenerative inductors were realized by the above two approaches. The reconfigurable SiGe LNA achieved by switching bias currents only occupies a very small area of 355 mumtimes155 mum, excluding measurement pads. This LNA achieves an input return losses (S₁₁) of -27.6 dB, a voltage gain (A _v) of 19.8 dB, and a noise figure (NF) of 3.18 dB for 2.4-GHz band when biased at a current of 3.8 mA and can be reconfigured to obtain A_v=20.4/20.3 dB, S₁₁=-47.1/-24.6 dB and NF=3.42/3.21 dB for 5.2/5.7-GHz band when bias current is switched to 3 mA. In addition, a 2.4/4.9/5.2/5.7-GHz reconfigurable SiGe LNAs for WLAN applications, whose variable shunt-shunt feedback capacitance is controlled by a switch and a capacitor, was also realized     

Silicon Bipolar LNAs in the X and Ku Bands

Two fully integrated silicon bipolar LNAs at 8 and 12 GHz are presented. Both circuits provide simultaneous noise and input impedance matching. Resonant loads, designed for 50-Ω output matching, are also included. Moreover, the noise and input impedance self-matching trend of the cascode topology in the X and Ku bands was also explored and the design of integrated spiral inductors was discussed. From an on-wafer test, the 8 and the 12-GHz LNAs exhibit a power gain of 11.5 and 8 dB and a noise figure of 2.6 and 4.7 dB, respectively. This performance was achieved with bias currents as low as 4 mA for each circuit. The two LNAs were fabricated in a 46-GHz-f _T pure bipolar technology.     

ESD-Protected Wideband CMOS LNAs Using Modified Resistive Feedback Techniques With Chip-on-Board Packaging

A novel modified resistive feedback structure for designing wideband low-noise amplifiers (LNAs) is proposed and demonstrated in this paper. Techniques including feedback through a source follower, an R–C feedback network, a gate peaking inductor inside the feedback loop, and neutralization capacitors are used. Bond-wire inductors and electrostatic devices (ESDs) are co-designed to improve the chip performance. Two LNAs, LNA1 and LNA2, were fabricated using a TSMC digital 90-nm CMOS technology. Both chips were tested on board using chip-on-board packages with ESD diodes added at the inputs and outputs. LNA1 achieves a 3-dB bandwidth of 9 GHz with 10 dB of power gain and a minimum noise figure (NF) of 4.2 dB. LNA2 achieves a 3-dB bandwidth of 3.2 GHz with 15.5 dB of power gain and a minimum NF of 1.76 dB. The two LNAs have third-order intermodulation intercept points of $-$8 and $-$9 dBm. Their power consumptions are 20 and 25 mW with a 1.2-V supply, respectively.      

一款基于65nm CMOS工艺的高效率50GHz 压控振荡器及其电感耦合效应的研究

A 50 GHz cross-coupled voltage controlled oscillator(VCO) considering the coupling effect of inductors based on a 65 nm standard complementary metal oxide semiconductor(CMOS) technology is reported.A pair of inductors has been fabricated,measured and analyzed to characterize the coupling effects of adjacent inductors. The results are then implemented to accurately evaluate the VCO’s LC tank.By optimizing the tank voltage swing and the buffer’s operation region,the VCO achieves a maximum efficiency of 11.4%by generating an average output power of 2.5 dBm while only consuming 19.7 mW(including buffers).The VCO exhibits a phase noise of—87 dBc/Hz at 1 MHz offset,leading to a figure of merit(FoM) of-167.5 dB/Hz and a tuning range of 3.8%(from 48.98 to 50.88 GHz).     

SiGe LNAs for UMTS System

Three LNAs at 2 GHz frequency range have been implemented in a SiGe Bipolar process targeted for a universal mobile telecommunications system. The LNAs are operating in two gain modes and they include a power-down mode. Both on-wafer and packaged LNAs were measured. Noise figure below 2 dB with IIP3 of 1 dBm and gain exceeding 15 dB has been achieved. LNAs work from a 2.7–5.5 V power supply. A figure of merit method is used to compare this work to other published LNAs.     

A modified architecture used for input matching in CMOS low-noise amplifiers

An architecture used for input matching in CMOS low-noise amplifiers (LNAs) is investigated in this paper. In the proposed architecture, gate and source inductors, which are essential in the traditional source inductive degeneration CMOS LNAs, are either reduced or removed. The architecture is finally verified by a narrow-band LNA and a wide-band LNA operating at 2.4-2.5 and 5.1-5.9 GHz, respectively. The narrow-band LNA has measured power gain of 24-dB, noise figure (NF) of 2.6-2.8 dB, and power consumption of 15 mW. The wide-band LNA provides 22.6-24.6-dB power gain and 2.85-3.5-dB NF while drawing 6 mA current from a 1.5-V voltage supply. Compared with their traditional counterparts, the proposed LNAs consume less chip area and present better gain performance.     

Design of integrated low noise amplifiers (LNA) using embedded passives in organic substrates

The noise figure of a low noise amplifier (LNA) is a function of the quality factor of its inductors. The lack of high-Q inductors in silicon has prevented the development of completely integrated complementary metal oxide semiconductor (CMOS) LNAs for high sensitivity applications like global system for mobile communications (GSM) (1.9 GHz) and wideband code-division multiple-access (W-CDMA) (2.1GHz). Recent developments in the design of high-Q inductors (embedded in low cost integrated circuit (IC) packages) have made single-package integration of RF front-ends feasible. These embedded passives provide a viable alternative to using discrete elements or low-Q on-chip passives, for achieving completely integrated solutions. Compared to on-chip inductors with low Q values and discrete passives with fixed Q/sub s/, the use of these embedded passives also leads to the development of the passive Q as a new variable in circuit design. However, higher Q values also result in new tradeoffs, particularly with respect to device size. This paper presents a novel optimization strategy for the design of completely integrated CMOS LNAs using embedded passives. The tradeoff of higher inductor size for higher Q has been adopted into the LNA design methodology. The paper also presents design issues involved in the use of multiple embedded components in the packaging substrate, particularly with reference to mutual coupling between the passives and reference ground layout.     

EM and substrate coupling in silicon RFICs

An investigation of coupling between inductors and resonators fabricated in silicon substrates is presented and the effects on RF systems and components are discussed. A novel experimental technique to measure inductor and resonator coupling is presented. The experiment is extremely sensitive, fast, accurate, and unique in that no matching, probe de-embedding, or calibration is necessary as the ratio of two on-chip signals is measured to yield the results.     

Experimental characterization of coupling effects between two on-chip neighboring square inductors

Comprehensive experimental results on the coupling effects between two on-chip symmetric and asymmetric neighboring inductors on GaAs substrates are presented. These pairs of inductors are fabricated with the same track width, turn number, and spacing. Based on the S parameters measured using the de-embedding technique, we show the effects of edge distance between these two neighboring inductors on the return and transfer losses, and on self-resonance frequency. Certain ways to reduce the transfer loss are explored.     

A Compact, ESD-Protected, SiGe BiCMOS LNA for Ultra-Wideband Applications

Two 3.65-mW, ESD-protected, BiCMOS ultra-wideband low-noise amplifiers (LNAs) for operation up to 10 GHz are presented. These common-base LNAs achieve significant savings in die area over more widely used cascoded common-emitter LNAs because they do not use an LC input matching network. A design with a shunt peaked load achieves a high S₂₁ (17-19 dB) and low noise figure (NF) (4-5 dB) across the band. A resistively loaded design exhibits a lower S₂₁ (15-16 dB) and higher NF (4.5-6 dB), but also utilizes 20% less silicon area. Both LNAs achieve a 1.5 kV ESD protection level and an acceptable S₁₁ (<-10 dB) across the band. Current source noise reduction is critical in common base topologies. Therefore, detailed noise analyses of MOS- and HBT-based current sources are provided     

Two-port noise figure optimization of source-degenerated cascode CMOS LNAs

This paper presents a noise figure optimization technique for source-degenerated cascode CMOS LNAs with lossy gate inductors. The optimization technique, based on two-port theory, takes into account second order parasitic components. The effect of inductive source degeneration on LNA noise parameters is discussed. Measured noise figures agree well with the simulations confirming the accuracy of the noise model and allowing us to investigate the contributions of various components to the overall noise figure. A 0.18-μm CMOS LNA with an integrated inductor (Q = 7.5) achieves a noise figure of 1.16 dB and a return loss of 20 dB at 1.4 GHz, drawing 39 mA from a 1.8-V voltage supply, having gain (S ₂₁) of 14.5 dB, input P1dB of ?17.5 dBm, and input IP3 of ?13 dBm. LNAs with external inductors having quality factor of Q = 170 and Q = 40 achieve noise figures of 0.65 dB and 0.68 dB and a return loss of 20 dB at 1.4 GHz, drawing 37 mA from a 1.8-V voltage supply, having gain (S ₂₁) of 17 dB, input P1dB of ?22 dBm, and input IP3 of ?14 dBm. The large power consumption of the presented designs was intentionally selected in order to reduce the noise figure, an acceptable trade-off for LNA’s targeted for radio telescope applications, and to assess the impact of the large currents flowing through interconnect metals on the noise figure     

Figure of merit for narrowband,wideband and multiband LNAs

In software defined radio, the same radio front end is used to accommodate different wireless standards operating in different frequency bands. The use of wideband or multiband low noise amplifiers (LNAs) is mandatory in such situations. There are several figures of merit (FoMs) proposed for narrowband LNAs. These FoMs are modified for wideband/multiband LNAs just by the inclusion of 3?dB bandwidth, and designers tend to use the one that favours their own design. In this article, a review of the existing FoMs for narrowband LNAs is presented. Based on this analysis, we propose two different FoMs for fair comparison of improvement in LNA parameters due to complementary metal oxide semiconductor (CMOS) technology advancement and circuit optimisation (irrespective of transistor technology), separately. The empirical technology scaling factor for gain, noise figure (NF), f _T and linearity is used to differentiate between these FoMs for different types of LNAs.     

基于改进的垂直型同轴微带转换的Ku频段平衡低噪声放大器

提出了一种垂直型同轴微带转换的宽带补偿方法,并应用于一款Ku频段平衡低噪声放大器(LNA)的研制。放大器包含波导同轴转换、同轴微带转换、由2级pHEMT 管芯及分支线耦合桥组成的前级放大器以及由MMIC 放大器实现的后级放大器。在13.5 ~14.5 GHz 频率范围内,2 批次累计55 套低噪声放大器的噪声系数小于1.5 dB、增益分布在44.5 ~46.5 dB之间,增益平坦度小于0.6 dB,批次间性能一致性良好。     

Amplificateurs GaAs monolithiques à large bande et gain élevé

A series of two, three and four stage monolithic GaAs amplifiers has been realized. The voltage gains lie from 15 to 42 dB with an upper 3 dB cut off frequency between 2 and 4.7 GHz. A selective load has been designed to define the lower 3 dB frequency less than 80 MHz and to offer the advantage of easy biasing of the circuit. Avoiding the use of inductors and coupling capacitors in the design allowed the achievement of a very high density of integration (active surface area equal to 0.2 mm²).     

基于LTCC的小型化中频带通滤波器设计

采用LTCC技术实现滤波器时,大电感值会引起加工复杂、寄生参数多等问题。文中通过部分电路等效法(PEEC)、三角形和星形联结等效变换法,将二阶直接耦合滤波器中的三角形连接电感等效为两个并联的耦合电感,减少了电感数量及感值。使得滤波器的设计复杂程度降低,标准化程度及一致性更高,封装更小。最终实现了一个中心频率70 MHz、相对带宽14.28%、插入损耗1.83 dB、回波损耗＜-15 dB的小型化中频滤波器。     

Using magnetic coupling to eliminate right half-plane zeros in boost converters

A dynamic analysis of the boost converter with an output filter reveals that magnetic coupling between inductors allows transfer of the zeros to the left half-plane of the control-to-output transfer function. Similar results requiring smaller magnetic components are obtained by combining magnetic coupling with damping of the output filter. The analysis is based on the application of the Routh-Hurtwitz's criterion to the numerator of the transfer function in order to derive the design conditions for the converter parameters. A design example illustrates the procedure, and experimental results verify the theoretical predictions. The application of these techniques will allow the design of high efficiency voltage boost-based regulators with dynamic behavior similar to buck-derived structures.     

K-band low-noise amplifiers using 0.18 /spl mu/m CMOS technology

Two K-Band low-noise amplifiers (LNAs) are designed and implemented in a standard 0.18 /spl mu/m CMOS technology. The 24 GHz LNA has demonstrated a 12.86 dB gain and a 5.6 dB noise figure (NF) at 23.5 GHz. The 26 GHz LNA achieves an 8.9 dB gain at the peak gain frequency of 25.7 GHz and a 6.93 dB NF at 25 GHz. The input referred third-order intercept point (IIP3) is >+2 dBm for both LNAs with a current consumption of 30 mA from a 1.8 V power supply. To our knowledge, the LNAs show the highest operation frequencies ever reported for LNAs in a standard CMOS process.     

A mutual coupling study of linear and circular polarized microstrip antennas for diversity wireless systems

In this paper, an analysis of mutual coupling is presented to examine the benefits of orthogonal polarizations and patterns for adjacent microstrip antennas. The mutual coupling between two linear polarized antennas orientated in parallel polarizations (E and H plane) is reduced using low dielectric constant materials. The mutual coupling can be reduced an additional 20-35dB at the same inter-element spacing when adjacent elements are orientated in orthogonal polarizations, O plane. Similarly, the mutual coupling between two circular polarized antennas orientated in the parallel polarization is reduced using low dielectric constant materials. However, the reduction in mutual coupling between two circular polarized antenna elements orientated in the O plane is only an additional 1-6 dB. The mutual coupling between a linear polarized sum beam (1/2/spl lambda/) and difference beam (1/spl lambda/) antenna is reduced 20-35 dB below the case when using identical antennas only in the H- and O-planes. Compact two- and four-element multielement antennas with inter-element spacings less than 0.15/spl lambda/ are fabricated and the S parameters and radiation patterns are measured.     

110-120-GHz monolithic low-noise amplifiers

The authors discuss the development of 110-120-GHz monolithic low-noise amplifiers (LNAs) using 0.1-mm pseudomorphic AlGaAs/InGaAs/GaAs low-noise HEMT technology. Two 2-stage LNAs have been designed, fabricated, and tested. The first amplifier demonstrates a gain of 12 dB at 112 to 115 GHz with a noise figure of 6.3 dB when biased for high gain, and a noise figure of 5.5 dB is achieved with an associated gain of 10 dB at 113 GHz when biased for low-noise figure. The other amplifier has a measured small-signal gain of 19.6 dB at 110 GHz with a noise figure of 3.9 dB. A noise figure of 3.4 dB with 15.6-dB associated gain was obtained at 113 GHz. The authors state that the small-signal gain and noise figure performance for the second LNA are the best results ever achieved for a two-stage HEMT amplifier at this frequency band