微电子所成功研制出4GS/s 8位ADC和3GS/s 12位DAC芯片

近日,中科院微电子所微波器件与集成电路研究室(四室)超高速数模混合电路研发团队在超高速模数/数模转换器(ADC/DAC)、直接数字频率合成器(DDS)相关芯片研制上取得重要进展,成功研制出多款高性能芯片。研制成功的芯片包括:4GS/s8位ADC,该芯片由两路ADC交织而成,每路集成宽带采样保持电路并采用优化的折叠内插结构实现。芯片内部集成SPI编程接口,可以有效校准两     

微电子所研制成功8GS/s 4bit ADC和10GS/s 8bit DAC芯片

近日,中科院微电子所微波器件与集成电路研究室(四室)超高速电路课题组在超高速ADC/DAC芯片研制上取得突破性进展,成功研制出8GS/s 4bit ADC和10GS/s 8bit DAC芯片。ADC芯片采用带插值平均的Flash结构,集成约1250只晶体管,测试结果表明芯片可以在8GHz时钟频率下稳定工作,最高采样频率可达9GHz。超高速DAC芯片采用基于R-2R的电流开关结构,同时集成了     

8bit 1.4GS/s模数转换器

超高速模数转换器(ADC)是软件无线电、高速数据采集和宽带数字化雷达的关键组成部分.附带校准技术的折叠内插ADC具有等同快闪(FLASH)ADC的高转换速度,是设计超高速ADC的最佳选择,但仍需综合考虑各项指标来时行校准方法设计及芯片架构优化.     

6 bit 1.8GS/s模数转换器

超高速模数转换器(ADC)是软件无线电、高速数据采集和宽带数字化雷达的关健组成部分.快闪(SLASH)ADC具有最高的转换速度,是设计超高速ADC的最佳选择,但是其功耗、面积都随分辨率指数增长,且对工艺离散敏感,因此需要综合考虑各项指标来进行芯片架构优化.     

基于40 nm工艺的单比特超宽带ADC

采用TSMC 40 nm工艺实现了一款宽带高速ADC。芯片采用时间交织的结构,单通道采用Flash结构,采样率为5 GS/s,8个子通道交织达到40 GS/s的采样率。测试结果表明,芯片的采样率可以达到38.4 GS/s,且在该采样率下,输入信号带宽可达18 GHz,灵敏度小于-20 dBm,可以满足单比特超宽带收发系统的需求。     

一种速度可扩展的时间交织复位运放流水线ADC的设计

本文提出了一种采用0.18mm CMOS工艺和金属-绝缘体-金属电容器选择的1.2V、10位、60~360MS/s六通道的时间交织复位运放流水线ADC的设计.具体实现包括:采用一种前端电阻-解复用技术来实现6个时间交织通道和低压增益以及偏移补偿技术来减轻时间交织通道间的偏移失配;设计了反馈电流偏置来确保工艺变化过程中电流源偏置的精确性;设计了低电压电流模式子ADC来降低静态功耗;设计了一种可编程时序偏差不敏感时钟发生器来减轻不同通道之间的时序失配;芯片测试结果表明,对于全部速度选项来说,ADC的微分非线性/积分非线性优于0.8/1.1 LSB,且信噪失真比在55 dB以上,而在60 MS/s和360 MS/s时分别消耗83.2 mW和406 Mw,整个ADC核面积仅为12.6mm2.     

超高速模数转换器研究进展

光通讯、5G和毫米波通信等应用系统的快速发展对ADC的采样速率和输入信号带宽提出了更高的要求。受到功耗和工艺器件的限制,传统流水线型高速高精度ADC的采样速率和精度已接近瓶颈,无法满足高速通信系统的信号采样需求,需要更新颖的超高速ADC结构和设计技术。文章介绍了近年来超高速ADC在工艺和设计技术方面的研究进展,详细分析了近年来基于时域交织技术和FinFET工艺进行超高速ADC设计的研究成果和发展动态。     

一种流水线型ADC的时序改进技术研究

对一种流水线型模数转换器(ADC)的时序电路进行了改进研究。改进时序延长了余量增益单元MDAC部分加减保持相位的时长,可以在不增加功耗与面积的情况下,将一种10位流水线型ADC在20 MS/s采样率下的有效位(ENOB)从9.3位提高到9.8位,量化精度提高了5%;将该ADC有效位不低于9.3位的最高采样率从21 MS/s提高到29 MS/s,转换速度提高了35%。ADC的采样频率越高,改进时序带来的效果越显著。该项技术特别适用于高速高精度流水线型ADC,也为其他结构ADC的高速高精度设计提供思路。     

8位CMOS双通道流水线ADC仿真设计

设计了一种8位1.2V,1GS/s双通道流水线A/D转换器(ADC)。所设计ADC对1.5位增益D/A转换电路(MDAC)中的流水线双通道结构进行改进,其中设置有双通道流水线时分复用运算放大器和双/单通道快闪式ADC,以简化结构并提高速度;在系统前置采样/保持器中加设由单一时间信号驱动的开关线性化控制(SLC)电路,以解决两条通道之间的采样歪扭和时序失调问题。用90nm标准CMOS工艺对所设计的流水线ADC进行仿真试验,结果表明,室温下所设计ADC的信噪比SNR为32.7dB,无杂散动态范围SFDR为42.3dB,它的分辨率、功耗PD和采样速率SR分别为8位、23mW和1GS/s,从而满足了高速、高精度和低功耗的应用需要。     

一种超高速宽带运算放大器的设计北大核心

介绍了一种采用高速双极工艺研制的超高速宽带运算放大器电路。运算放大器内部采用高速电流反馈结构进行信号传输和放大,通过带宽提升、电压/电流信号转换以及稳定性补偿等设计技术,获得了要求的速度和带宽。研究了高速宽带运放性能的影响因素,并结合高速双极工艺进行了电路仿真设计和流片制作。测试结果表明:在±5 V电源电压下,运算放大器的电源电流≤6 mA,-3 dB带宽≥500 MHz,转换速率≥1 500 V/μs。     

Low-power pipeline ADC for wireless LANs

In this paper, a 10-bit 40-MS/s analog-to-digital converter (ADC) is presented. A power consumption of 12 mW was achieved by using a time-interleaved and pipelined architecture with shared operational amplifiers. This circuit was fabricated in a 2.5-V 0.25-/spl mu/m technology with metal-oxide-metal capacitors. Experimental results are within design ranges and are in good agreement with simulation data. It turns out that the proposed Nyquist-rate ADC provides a potential solution for low-power high-speed applications, e.g., wireless LANs.     

一种10bit双通道流水线SAR ADC设计

为了提高模数转换器的采样频率并降低其功耗,提出一种10 bit双通道流水线逐次逼近型（SAR）模数转换器（ADC）。提出的ADC包括两个高速通道,每个通道都采用流水线SAR结构以便低功率和减小面积。考虑到芯片面积、运行速度以及电路复杂性,提出的处于第二阶段的SAR ADC由1 bit FLASH ADC和6 bit SAR ADC组成。提出的ADC由45 nm CMOS工艺制作而成,面积为0.16 mm2。ADC的微分非线性和积分非线性分别小于0.36 最低有效位（LSB）和0.67 LSB。当电源为1.1 V时,ADC的最大运行频率为260 MS/s。运行频率为230 MS/s和260 MS/s的ADC的功率消耗分别为13.9 mW和17.8 mW。     

A 6-bit 800-MS/s Pipelined A/D Converter With Open-Loop Amplifiers

A 6-bit 800-MS/s pipelined A/D converter (ADC) achieves SNDR and SFDR of 33.7 dB and 47.5 dB, respectively. Employing voltage-mode open-loop amplifiers in gain stages, global gain control techniques, and two-bank-interleaved architecture, the proposed pipelined A/D converter relaxes stringent design tradeoffs between speed and power. Fabricated in a 0.18-mum CMOS technology, the ADC consumes 105 mW from a 1.8-V power supply while the active area is only 0.5 mm²     

A 1-GS/s 11-bit ADC With 55-dB SNDR, 250-mW Power Realized by a High Bandwidth Scalable Time-Interleaved Architecture

A time-interleaved ADC architecture that eliminates the need to correct timing offsets and is yet scalable to high sampling rates is presented. To eliminate timing skews, a Nyquist rate sampling switch is used, which is followed by subsampled, double-sampled time-interleaved sample-and-hold (S/H) stages. This circuit is configured with a special clocking scheme that reduces the loading of the interleaved S/Hs on the Nyquist rate sampling switch, making this scalable to high sampling rates. The subsampled ADCs (sub-ADCs) in this design use a 3.5-bit/stage pipelined architecture. This 1-GS/s 11-bit ADC achieves 55-dB peak SNDR, 58.6-dB SNR, consumes 250-mW core power, and occupies a core area of 3.5 mm². This circuit is implemented in a dual-gate 1.2 V/2.5 V, 0.13-mum logic CMOS process     

A 150-MS/s 8-b 71-mW CMOS time-interleaved ADC

A pipelined analog-to-digital converter (ADC) architecture suitable for high-speed (150 MHz), Nyquist-rate A/D conversion is presented. At the input of the converter, two parallel track-and-hold circuits are used to separately drive the sub-ADC of a 2.8-b first pipeline stage and the input to two time-interleaved residue generation paths. Beyond the first pipeline stage, each residue path includes a cascade of two 1.5-b pipeline stages followed by a 4-b "backend" folding ADC. The full-scale residue range at the output of the pipeline stages is half that of the converter input range in order to conserve power in the operational amplifiers used in each residue path. An experimental prototype of the proposed ADC has been integrated in a 0.18-/spl mu/m CMOS technology and operates from a 1.8-V supply. At a sampling rate of 150 MSample/s, it achieves a peak SNDR of 45.4 dB for an input frequency of 80 MHz. The power dissipation is 71 mW.     

A Background Sample-Time Error Calibration Technique Using Random Data for Wide-Band High-Resolution Time-Interleaved ADCs

Sample-time error among the channels of a time-interleaved analog-to-digital converter (ADC) is the main reason for significant degradation of the effective resolution of the high-speed time-interleaved ADC. A calibration technique for sample-time mismatches has been proposed and implemented at a low level of complexity. The calibration method uses random data and is especially suitable for ADCs used in digital data communication systems. An 800-MS/s four-channel, time-interleaved ADC system has been implemented to evaluate the performance of the technique. The experimental results show that the spurious-free dynamic range of the ADC system is improved to 58.1 dB at 350 MHz. The ADC system achieves a signal-to-noise and distortion ratio of 59.6 dB at 5 MHz and 50.1 dB at 350 MHz after calibration.     

High performance 14-bit pipelined redundant signed digit ADC

A novel architecture of a pipelined redundant-signed-digit analog to digital converter(RSD-ADC) is presented featuring a high signal to noise ratio(SNR), spurious free dynamic range(SFDR) and signal to noise plus distortion(SNDR) with efficient background correction logic. The proposed ADC architecture shows high accuracy with a high speed circuit and efficient utilization of the hardware. This paper demonstrates the functionality of the digital correction logic of 14-bit pipelined ADC at each 1.5 bit/stage. This prototype of ADC architecture accounts for capacitor mismatch, comparator offset and finite Op-Amp gain error in the MDAC(residue amplification circuit) stages. With the proposed architecture of ADC, SNDR obtained is 85.89 dB, SNR is 85.9 dB and SFDR obtained is 102.8 dB at the sample rate of 100 MHz. This novel architecture of digital correction logic is transparent to the overall system, which is demonstrated by using 14-bit pipelined ADC. After a latency of 14 clocks, digital output will be available at every clock pulse. To describe the circuit behavior of the ADC, VHDL and MATLAB programs are used. The proposed architecture is also capable of reducing the digital hardware. Silicon area is also the complexity of the design.     

An 11b 70-MHz 1.2-mm/sup 2/ 49-mW 0.18-/spl mu/m CMOS ADC with on-chip current/voltage references

This work proposes an 11b 70-MHz CMOS pipelined analog-digital converter (ADC) as one of core circuit blocks for very high speed digital subscriber line system applications. The proposed ADC for the internal use has the strictly limited number of externally connected I/O pins while the ADC employs on-chip CMOS current/voltage references and a merged-capacitor switching technique to improve ADC performances. The ADC implemented in a 0.18-/spl mu/m 1P4M CMOS technology shows the maximum signal-to-noise distortion ratio (SNDR) of 60 dB at 70 MSample/s. The ADC maintains the SNDR of 58 dB and the spurious-free dynamic resistance of 68 dB for input frequencies up to the Nyquist rate at 60 MSample/s. The measured differential and integral nonlinearities of the ADC are within /spl plusmn/0.63 and /spl plusmn/1.21 LSB, respectively. The active chip area is 1.2 mm/sup 2/ and the ADC consumes 49 mW at 70 MSample/s at 1.8 V.     

A background calibration technique for multibit/stage pipelined and time-interleaved ADCs

A digital background calibration technique to compensate for the nonlinearity and gain error in the sub-digital-to-analog converter (SDAC), and the operational amplifier finite dc gain in multibit/stage pipelined analog-to-digital converter (ADC) is proposed. By injecting subtractive calibration voltages in a modified conventional multibit multiplying DAC and performing correlation based successive coefficient measurements, a background calibration is performed. This calibration technique does not need an accurate reference voltage or an increasing in the SDAC resolution. A global gain correction essential for time-interleaved ADCs is presented. Simulation results show that in the presence of realistic capacitor and resistance mismatch and finite op-amp gain, this technique improves the linearity by several bits in single and multi-channel pipelined ADC.     

0.13 μm CMOS 60 dB SFDR的8 bit 250 MS/s模数转换器

论述了一种高速度低功耗的8位250 MHz采样速度的流水线型模数转换器(ADC).在高速度采样下为了实现大的有效输入带宽,该模数转换器的前端采用了一个采样保持放大器(THA).为了实现低功耗,每一级的运放功耗在设计过程中具体优化,并在流水线上逐级递减.在250 MHz采样速度下,测试结果表明,在1.2 V供电电压下,所有模块总功耗为60 mw.在19 MHz的输入频率下,SFDR达到60.1 dB,SNDR为46.6 dB,有效比特数7.45.有效输入带宽大于70 MHz.该ADC采用TSMC 0.13μm CMOS 1P6M工艺实现,芯片面积为800 μm×700μm.