A CMOS compatible lateral emitter switched thyristor with enhancedturn-on capability

A new Lateral Emitter Switched Thyristor structure (LEST) is proposed and experimentally verified. The structure differs from the conventional LEST in that it embeds a floating ohmic contact between the n^- drift region and the n⁺ floating emitter. Both simulation and experimental results show that the device has an enhanced turn-on capability compared with the conventional LEST without deteriorating its other characteristics. The device is fabricated using a 3 μm CMOS process to have a 320 V breakdown voltage and a 0.7 V threshold voltage. Thyristor turn-on is observed at an anode voltage below 2 V. The maximum MOS controllable current density is in excess of 200 A/cm² with 5 V gate voltage     

Lateral junction-isolated emitter switched thyristor

The operation of a 600-V junction-isolated lateral emitter switched thyristor (JI-LEST) is demonstrated. These devices exhibit an on-state voltage drop of 2.6 V at a current density of 100 A/cm² , a turn-off time of 20 μs, and a maximum controllable current density of about 200 A/cm²     

Theoretical and experimental characteristics of the base resistancecontrolled thyristor (BRT)

Described are the characteristics of a new MOS gated thyristor structure called the base resistance controlled thyristor (BRT), in which the turn-off of a thyristor built with an N drift region is achieved by reducing the resistance of the p-base region under MOS gate control. A p-channel MOSFET used to achieve turn-off is formed in the N drift region. The device is designed so that, when the p-channel MOSFET is switched on, holes are diverted from the p-base region of the thyristor into the adjacent p⁺ region, raising the holding current of the thyristor above the operating current level, and turning off the thyristor. Results of extensive 2-D numerical simulations that have been performed to demonstrate operation of this new device concept are discussed. Experimental results on 600-V devices fabricated with an IGBT process have corroborated theoretical predictions. Current densities above 900 A/cm² have been turned off at room temperature with a gate bias of -10 V     

Performance of a CMOS compatible lateral bipolar photodetector onSOI substrate

The performance of a photodetector fabricated using a standard CMOS process on SOI substrate has been studied. The photodetector is basically a floating gate SOI NMOSFET operating in the lateral bipolar mode. The depletion region induced by the floating gate separates the optically generated electron-hole pairs in the direction perpendicular to the current. This results in an extra current amplification beyond that of a normal lateral bipolar transistor. A high responsivity of 289 A/W has been measured with an operating voltage as low as 0.1 V. The impacts of technology scaling on the performance of the photodetector are also studied     

Floating base thyristor

The floating base thyristor (FBT) is a new thyristor structure in which its p-base region, containing a p⁺ region is not shorted to the n⁺ emitter. Using the DMOS process, an n-channel and a p-channel MOSFET are integrated with the thyristor structure. The device operates in the thyristor mode with a low ON-state voltage drop at even high current densities when a positive bias is applied to, both gates. When a negative bias is applied to the OFF gate, the device operates in the IGBT mode with the saturated current controlled by the positive bias applied to the ON gate     

A SPICE compatible subcircuit model for lateral bipolar transistorsin a CMOS process

This paper describes a SPICE compatible subcircuit model of a lateral pnp transistor, which was fabricated in a 0.6 μm CMOS process. The extraction of a dc parameter set for the lateral device is more complicated than for a vertical device because of the presence of two parasitic vertical bipolar transistors which are formed by the emitter/collector, the base and the substrate regions. The SPICE Gummel-Poon model does not predict the substrate current accurately. This paper proposes a method which involves the use of a subcircuit incorporating three SPICE Gummel-Poon models [representing one lateral and two parasitic vertical bipolar junction transistors (BJT's)]. The development of this model, its implementation and the results obtained are outlined and discussed. This circuit model is SPICE compatible and can thus be used in commercial simulators. The model provides good agreement over a wide range of measured dc data including substrate current prediction     

A new lateral MOS-controlled thyristor

A lateral MOS-controlled thyristor (LMCT) structure that uses an MOS gate to turn it both on and off is presented. The device structure offers improved maximum turn-off current capability and forward voltage drop. The former is achieved by using a DMOS transistor and a parasitic vertical p-n-p transistor, while the latter is achieved by eliminating a parasitic lateral p-n-p transistor in the conventional structure. The device utilizes the resurf technique to achieve high area efficiency, breakdown voltage, and reliability. Devices that have more than 250-V forward blocking capability were fabricated in dielectrically isolated silicon tubs using the standard bipolar-CMOS-DMOS process     

Fully differential operational amplifiers using CMOS compatible lateral bipolar transistors with improved common-mode regulation

A new bias circuit for a CMOS compatible lateral bipolar transistor differential pair is presented. The circuit compensates for all process and bias dependent variations of the lateral collector current to emitter current ratio alpha . Experimental results show that its application to a fully differential amplifier improves the precision of the common-mode output voltage regulation by at least an order of magnitude.<>     

Base current reversal phenomenon in a CMOS compatible high gainn-p-n gated lateral bipolar transistor

Base current reversal phenomenon is newly observed in a CMOS compatible high gain n-p-n gated lateral bipolar transistor. We attribute this phenomenon to avalanche generation as verified experimentally and by two-dimensional device simulation. Detailed investigation reveals that: (i) the multiplication ratio increases exponentially with the collector voltage or equivalently the peak field at the surface collector corner; and (ii) the multiplication ratio is independent of not only the low level base-emitter forward biases applied but also the base width of the transistors fabricated by the same process. Design guideline for suppression of the base current reversal has been established such as to fully realize the potential of the gated lateral bipolar transistors, i.e., a very high current gain of 11,600 can be maintained as long as the power supply voltage is less than the critical value of 1.78 V. On the other hand, new application directly employing this phenomenon has been suggested. Comparisons between the base current reversal phenomenon in the gated lateral bipolar transistor and that in the vertical bipolar transistor have also been performed and significant differences between the two have been drawn and have been adequately explained     

CMOS compatible thermoelectric infrared sensors

A new structure for CMOS compatible thermoelectric infrared sensors is proposed. By using micro-link structures to connect several floating membranes, the largest floating membrane area yet obtained and large output voltages have been realised. The characteristics of the sensors have been measured, and are compared with those of existing devices     

Dielectrically isolated lateral emitter switched thyristor

The operation of a 500 V dielectrically isolated lateral emitter switched thyristor (DI-LEST) is described for the first time. Experimental devices exhibit an on-state voltage drop of 2.35 V at a current density of 100 A/cm/sup 2/, and a maximum controllable current density of about 200 A/cm/sup 2/. The on-state voltage drop decreases with increasing drift layer thickness consistent with the uniform lateral current flow observed in two-dimensional numerical simulations.<>     

The dual gate base resistance controlled thyristor

A new device concept, called the dual gate base resistance controlled thyristor (DG-BRT), is introduced for simultaneously obtaining the low on-state voltage drop of a thyristor together with a good forward biased safe operating area. The two gates are used to control an N-channel and a P-channel MOSFET integrated with a thyristor structure using the DMOS process. When a positive bias is applied to both gates, the device operates in the thyristor-mode with a low on-state voltage drop at even high current densities. When a negative bias is applied to the OFF-gate, the device operates in the IGBT-mode with the saturated current controlled by the positive bias applied to the ON-gate. The results of two-dimensional numerical simulations and measurements performed on devices with 600 V forward blocking capability are reported     

Predictions of CMOS compatible on-chip optical interconnect

Interconnect has become a primary bottleneck in the integrated circuit design process. As CMOS technology is scaled, the design requirements of delay, power, bandwidth, and noise due to the on-chip interconnects have become more stringent. New design challenges are continuously emerging, such as delay uncertainty induced by process and environmental variations. It has become increasingly difficult for conventional copper interconnect to satisfy these design requirements. On-chip optical interconnect has been considered as a potential substitute for electrical interconnect. In this paper, predictions of the performance of CMOS compatible optical devices are made based on current state-of-the-art optical technologies. Electrical and optical interconnects are compared for various design criteria based on these predictions. The critical dimensions beyond which optical interconnect becomes advantageous over electrical interconnect are shown to be approximately one-tenth of the chip edge length at the 22 nm technology node.     

CMOS兼容的中红外多通道光子晶体传感器

我们提出了一种基于光子晶体的二维多通道光学化学传感器。该器件由中心波长为3.3 μm的四个腔组成,各通道工作波长间隔为10 nm。该传感器采用800 nm厚的绝缘体上硅材料,可利用标准CMOS技术加工。我们通过三维时差有限差分法对微腔结构的光学特性进行模拟。每个通道的传输效率为39％,通道之间的传输效率不一致性小于0.25dB。该传感器的功能为检测四氯化碳和苯溶液浓度,其灵敏度为209.2 nm/RIU。     

A new lateral MOS-gated thyristor with controlling base-current

A new lateral MOS-gated thyristor, called the Base-Current-Controlled Thyristor, is described. This device is designed so that most holes at the on-stage reach the P base through the floating P⁺ region adjacent to the P base and the on-state MOSFET. At the turn-off stage, the interruption of the hole current to the P base due to switching off the above MOSFET occurs simultaneously with the conventional turn-off operation. The concept of this device is verified experimentally by using the fabricated lateral device with the external MOSFET. This device exhibits a better trade-off relation between the on-state voltage and the turn-off time compared uith the conventional MOS-gated thyristor     

An emitter switched thyristor with base resistance control

An MOS-gated emitter-switched thyristor structure with base resistance control, which combines the best features of both the emitter-switched thyristor (EST) and the base-resistance-controlled thyristor (BRT), is reported. With this structure, it is possible to obtain turn-off (dynamic) current densities above the static latch-up current density of the parasitic thyristor in the EST, while preserving its unique current saturation capability. It has been experimentally demonstrated for 600 V forward blocking devices that the maximum controllable current density under dynamic conditions is a function of both the gate bias and the dimensions of the N⁺ floating emitter. Turn-off measurements have demonstrated that the new structure has a maximum controllable current density of over 2.5 times that for the EST structure without base resistance control     

一种新型的CMOS集成湿度传感器

利用MEMS技术 ,对一种新型CMOS湿度传感器进行理论分析、模拟以及结果讨论。该湿度传感器采用标准CMOS工艺制造 ,采用梳状铝电极结构、梳状多晶硅加热结构 ,衬底接地 ,感湿介质采用聚酰亚胺 ,利用商业软件Coventor进行模拟绘制出敏感电容与相对湿度的曲线图。接口电路采用开关电容电路 ,输出可测电压信号 ,利用Microsim公司的Pspice模拟电路得到相对湿度与输出电压曲线关系     

A compatible NMOS, CMOS metal gate process

An MOS LSI technology is presented, which allows the efficient fabrication of n-MOS and CMOS circuits on the same chip, a capability, which has become highly desirable in view of recent advances in circuit design, particularly analog-digital interfaces. The process starts from a p-type substrate. An n-well is formed by ion implantation. An additional implantation simultaneously sets the p-channel and n-channel threshold voltages as well as the field threshold above the substrate. The implanted field provides high density and simple processing. A third implantation step adjusts the threshold voltage of the n-channel depletion load transistor. Supply voltages up to 20 V are possible. Process modeling data are presented both by theoretical consideration and the measurement of actual profiles of the well and threshold dependence on energy, dose, and drive-in conditions. Distributions of the electrical parameters are rather narrow with standard deviations of thresholds <150 mV. Transconductance constants are typically 9 and 29 µA . V^-2for p-and n-channel transistors, respectively. CMOS inverter gain is 250 for channel lengths of 10 and 25 µm, respectively.     

CMOS compatible fully integrated Mach-Zehnder interferometer in SOItechnology

We present a fully integrated Mach-Zehnder interferometer in silicon-on-insulator technology. Modulation of the index of refraction is achieved through the plasma dispersion effect resulting in a bandwidth in the 10 MHz range. A particular and innovative design makes this device completely compatible with CMOS technology allowing electronic functions to be integrated on the same substrate. Measurement results, limitations due to thermooptic effect and absorption related to charge injection together with further improvements are discussed