On-line fault detection for bus-based field programmable gatearrays

We introduce a technique for on-line built-in self-testing (BIST) of bus-based field programmable gate arrays (FPGAs). This system detects deviations from the intended functionality of an FPGA without using special-purpose hardware, hardware external to the device, and without interrupting system operation. Such a system would be useful for mission-critical applications with resource constraints. The system solves these problems through an on-line fault scanning methodology. A device's internal resources are configured to test for faults. Testing scans across an FPGA, checking a section at a time. Simulation on a model FPGA supports the viability and effectiveness of such a system     

Flexibility of interconnection structures for field-programmablegate arrays

The relationship between the routability of a field-programmable gate array (FPGA) and the flexibility of its interconnection structures is examined. The flexibility of an FPGA is determined by the number and distribution of switches used in the interconnection. While good routability can be obtained with a high flexibility, a large number of switches will result in poor performance and logical density because each switch has significant delay and area. The minimum number of switches required to achieve good routability is determined by implementing several industrial circuits in a variety of interconnection architectures. These experiments indicate that high flexibility is essential for the connection block that joins the logic blocks to the routing channel, but a relative low flexibility is sufficient for switch blocks at the junction of horizontal and vertical channels. Furthermore, it is necessary to use only a few more routing tracks than the absolute minimum possible with structures of surprisingly low flexibility     

Inductance and resistance computations for three-dimensionalmulticonductor interconnection structures

A computer-aided analysis system has been established to calculate the equivalent inductance and resistance matrices for three-dimensional multiconductor interconnection structures. Based on partial element equivalent circuit theory, the interconnection structures are first decomposed into many straight segments which are of circular or rectangular cross sections but can be in arbitrary orientation. The resistances and partial inductances between all these segments are calculated using analytical integration and quadrature formulae. They are assembled into the desired equivalent impedance matrix by general network theory. Illustrative examples include the analysis for nonuniformly coupled transmission lines and the calculation for skin-effect impedances of transmission lines and three-dimensional structures. The numerical results are in good agreement with the measurement data and results in the literature     

Synthesis method for field programmable gate arrays

Logic synthesis algorithms and methods for field-programmable gate arrays (FPGAs) are reviewed. The three most popular types of FPGA architectures are considered, namely, those using logic blocks based on lookup-tables, multiplexers, and wide AND/OR arrays, respectively. The emphasis is on tools that attempt to minimize the area of the combinational logic part of a design, since little work has been done on optimizing performance or routability, or on synthesis of the sequential part of a design. The different tools surveyed are compared using a suite of benchmark designs     

Antifuse field programmable gate arrays

An antifuse is an electrically programmable two-terminal device with small area and low parasitic resistance and capacitance. Field-programmable gate arrays (FPGAs) using antifuses in a segmented channel routing architecture now offer the digital logic capabilities of an 8000-gate conventional gate array and system speeds of 40-60 MHz. A brief survey of antifuse technologies is provided. the antifuse technology, routing architecture, logic module, design automation, programming, testing and use of ACT antifuse FPGAs are described. Some inherent tradeoffs involving the antifuse characteristics, routing architecture and logic module are illustrated     

A multiplexer-based architecture for high-density, low-power gatearrays

This paper presents a novel architecture that provides higher density and lower power dissipation than conventional basecells. The layout of transistors in this small basecell allows the efficient construction of multiplexers with minimal use of programmable layers. The multiplexer can be used to create any 2 input and some 3 input functions in one basecell. Internal fanout, rather than typical output load, defines the size of driver and multiplexer transistors, which can be independently tailored for the desired speed/area/power target. This basecell, which is well suited for implementing datapath elements, has been used to create a 16×16-b multiplier operating at 50 MHz in 314500 μm² in 0.6 μm technology     

A comparison of homogeneous hierarchical interconnection structures

Among the various proposal advanced to build massive parallel systems in which the number of computing units ranges in the thousands, hierarchical topologies share a number of interesting properties. The authors review these architectures and their applicability and reliability, with particular attention to connections complexity and the ability to exchange messages. The usual assumption of the multiple instruction multiple data (MIMD) computational paradigm is as follows: autonomous but cooperating tasks execute on different processing units in the system. The overall complexity of the systems is measured with the analysis of the diameter and of the increasing law that states the number of interconnections against the number of nodes in the system. The various architectures are compared in terms of links load and average internode distance     

Hierarchical vector finite elements for analyzing waveguiding structures

In this paper, we extend the finite-element method into hierarchical higher order bases and the inexact Helmholtz decomposition. With the help of hierarchical basis functions, the approach can adopt well into the p version adaptive process. On the other hand, the inexact Helmholtz decomposition enhances the stability of the finite-element procedure when the operating frequency is low or the element size is very small compared to the wavelength. This approach can also enhance the h version adaptive mesh refinement process since the process may cause very small elements near a singular region. To accomplish the inexact Helmholtz decomposition for the edge elements, the lowest order curl conforming basis functions, the tree-cotree splitting, is utilized, and the general procedure is presented. As a result, a combination of hierarchical higher order basis functions with the inexact Helmholtz decomposition can improve the efficiency and the stability of the hp adaptive mesh refinement process. The accuracy and stability of the proposed approach are also discussed through numerical examples.     

Mixed-grained CMOS field programmable analog array for smart sensory applications

The drive towards shorter design cycles for analog integrated circuits has given impetus to the development of Field Programmable Analog Arrays （FPAAs）, which are the analogue counterparts of Field Programmable Gate Arrays （FPGAs）. In this paper, we present a new design methodology which using FPAA as a powerful analog front-end processing platform in the smart sensory micro- system. The proposed FPAA contains 16 homogeneous mixed-grained Configurable Analog Blocks （CABs） which house a variety of processing elements especially the proposed fine-grained Core Con- figurable Amplifiers （CCAs）. The high flexible CABs allow the FPAA operating in both continu- ous-time and discrete-time approaches suitable to support variety of sensors. To reduce the nonideal parasitic effects and save area, the fat-tree interconnection network is adopted in this FPAA. The functionality of this FPAA is demonstrated through embedding of voltage and capacitive sensor signal readout circuits and a configurable band pass filter. The minimal detectable voltage and capacitor achieves 38 uV and 8.3 aF respectively within 100 Hz sensor bandwidth. The power consumption comparison of CCA in three applications shows that the FPAA has high power efficiency. And the simulation results also show that the FPAA has good tolerance with wide PVT variations.     

A field programmable analog array for CMOS continuous-time OTA-Cfilter applications

A programmable high-frequency operational transconductance amplifier (OTA) is proposed and analyzed. A general configurable analog block (CAB) is presented, which consists of the proposed programmable OTA, programmable capacitor and MOSFET switches. Using the CABs, the universal tunable and field programmable analog array (FPAA) can be constructed, which can realize many signal-processing functions, including filters. A tuning circuit is also discussed. The proposed OTA has been simulated and fabricated in CMOS technology. The results show that the OTA has the transconductance tunable/programmable in a wide range of 700 times and the -3-dB bandwidth larger than 20 MHz. A universal 5×8 CAB array has been fabricated. The chip has also been configured to realize OTA-C 60-kHz and 500-kHz bandpass filters based on ladder simulation and biquad cascade     

Implementing division with field programmable gate arrays

This article presents a method to map digit-recurrence arithmetic algorithms to lookup-table based Field Programmable Gate Arrays (FPGAs). By reducing the number of binary inputs to combinational logic and merging algorithm steps, the strategy creates new simplified functions to decrease logic depth and area. To illustrate this method, a radix-2 digit-recurrence division algorithm is mapped to the Xilinx XC4010, a lookup-table based FPGA. The mapping develops a linear sequential array design that avoids the common problem of large fanout delay in the critical path. This approach has a cycle time independent of precision while requiring approximately the same number of logic blocks as a conventional design.     

Wiring requirement and three-dimensional integration technology for field programmable gate arrays

In this paper, analytical models for predicting interconnect requirements in field-programmable gate arrays (FPGAs) are presented, and opportunities for three-dimensional (3-D) implementation of FPGAs are examined. The analytical models for two-dimensional FPGAs are calibrated by routing and placement experiments with benchmark circuits and extended to 3-D FPGAs. Based on system-level modeling, we find that in FPGAs with more than 20 K four-input look-up tables, the reduction in channel width, interconnect delay and power dissipation can be over 50% by 3-D implementation.     

Structure and applications of field programmable logic arrays

The recent surge in design activity involving microprocessors and microprogramming techniques reflects the growing trend to replace hardwired logic with microcode for gaining system flexibility at lower cost. In this respect, designers have come to rely on ever larger and denser PROMs to fit the demands of their applications, and today PROMs as large as 4K-bits, organized as 512X8 or 1KX4 are readily available. However, a PROM solution in general forces the user to allocate storage for all possible logic combinations of the input variables, whether needed or not. As a result, when dealing with the type of problem requiring the manipulation of more than about 10 logic variables (or Addresses), several IC packages are usually necessary. This quickly renders a PROM solution marginal at best in terms of speed, power, and cost, and in most cases impractical.Fortunately, many combinational and sequential logic designs involve logic functions which are True for only a small subset of the total logic states generated by the controlling variables. It is here that we step in the basic domain of Field Programmable Logic Arrays which, when viewed as Associative memories, exhibit Selective, Concurrent and Multiple addressing modes that enable compressing a set of logic functions to the minimum required states, at substantial savings in hardware. Also, since FPLAs can be programmed in the field by the user, they are more economical and easier to use than mask programmable PLAs, and should find their way quickly in a wider variety of design situations     

Circuits and architectures for field programmable gate array with configurable supply voltage

Field programmable gate arrays (FPGAs) with supply voltage (Vdd) programmability have been proposed recently to reduce FPGA power, where the Vdd-level can be customized for FPGA circuit elements and unused circuit elements can be power-gated. In this paper, we first design novel Vdd-programmable and Vdd-gateable interconnect switches with minimal number of configuration SRAM cells. We then evaluate Vdd-programmable FPGA architectures using the new switches. The best architecture in our study uses Vdd-programmable logic blocks and Vdd-gateable interconnects. Compared to the baseline architecture similar to the leading commercial architecture, our best architecture reduces the minimal energy-delay product by 54.39% with 17% more area and 3% more configuration SRAM cells. Our evaluation results also show that LUT size 4 gives the lowest energy consumption, and LUT size 7 leads to the highest performance, both for all evaluated architectures.     

A TLM-SPICE interconnection framework for coupled field and circuit analysis in the time domain

A general SPICE-transmission-line matrix (TLM) interconnection framework has been developed. The connection algorithm is based on the representation of the TLM network by equivalent Thevenin and/or Norton sources. Fundamental issues such as source equivalence and SPICE-TLM interconnection options have been examined. The framework opens new and far-reaching possibilities for hybrid global microwave and high-speed digital circuit modeling in the time domain because it combines the extensive circuit and device models of SPICE with general three-dimensional field solutions.     

Long term storage reliability of antifuse field programmable gate arrays

Field Programmable Gate Arrays (FPGA) with antifuse elements are preferred in aerospace applications due to their non-volatility and demonstrated radiation hardness. Because aerospace applications typically involve long operating life, there is a requirement to store un-programmed antifuse FPGA parts for long periods and program them when necessary to support the system. No study on the long term reliability of un-programmed antifuse FPGAs in the storage environment is reported in literature. In this paper, antifuse structures, programming process, and failure mechanisms of antifuse FPGAs are discussed. A failure modes, mechanisms and effects (FMMEA) analysis was performed for storage conditions and critical failure mechanisms were identified. High temperature storage tests of a select number of antifuse FPGAs were performed to accelerate the identified failure mechanisms. These parts were subsequently programmed and yield data was analyzed to determine the effects of high temperature storage.     

Built-in self-test of global interconnects of field programmable analog arrays

Strategies for the test of Field Programmable Analog Arrays (FPAAs) have been devised based on testing separately their main three components: configurable analog blocks, I/O pads and interconnection network. In this work, a scheme for testing the interconnection network, in particular the global wiring, is presented. As long as analog wiring is considered, catastrophic faults at the switches and wires are considered, as well as parametric capacitive or resistive defects in interconnects. Similarly to FPGAs, critical path search is based on a graph model, so that known algorithms are reused, yielding a minimum number of Test Configurations. Then, a near-zero area overhead BIST procedure is proposed, in which Analog Built-in Block Observers are implemented as oscillators and integrators, respectively, generating test stimuli and analyzing output responses, using internal configurable resources of the FPAA.     

Optimal interconnection circuits for VLSI

The propagation delay of interconnection lines is a major factor in determining the performance Of VLSI circuits because the RC time delay of these lines increases rapidly as chip size is increased and cross-sectional interconnection dimensions are reduced. In this paper, a model for interconnection time delay is developed that includes the effects of scaling transistor, interconnection, and chip dimensions. The delays of aluminum, WSi2, and polysilicon lines are compared, and propagation delays in future VLSI circuits are projected. Properly scaled multilevel conductors, repeaters, cascaded drivers, and cascaded driver/ repeater combinations are investigated as potential methods for reducing propagation delay. The model yields optimal cross-sectional interconnection dimensions and driver/repeater configurations that can lower propagation delays by more than an order of magnitude in MOSFET circuits.     

Hierarchical scale-based multiobject recognition of 3-D anatomical structures

Segmentation of anatomical structures from medical images is a challenging problem, which depends on the accurate recognition (localization) of anatomical structures prior to delineation. This study generalizes anatomy segmentation problem via attacking two major challenges: 1) automatically locating anatomical structures without doing search or optimization, and 2) automatically delineating the anatomical structures based on the located model assembly. For 1), we propose intensity weighted ball-scale object extraction concept to build a hierarchical transfer function from image space to object (shape) space such that anatomical structures in 3-D medical images can be recognized without the need to perform search or optimization. For 2), we integrate the graph-cut (GC) segmentation algorithm with prior shape model. This integrated segmentation framework is evaluated on clinical 3-D images consisting of a set of 20 abdominal CT scans. In addition, we use a set of 11 foot MR images to test the generalizability of our method to the different imaging modalities as well as robustness and accuracy of the proposed methodology. Since MR image intensities do not possess a tissue specific numeric meaning, we also explore the effects of intensity nonstandardness on anatomical object recognition. Experimental results indicate that: 1) effective recognition can make the delineation more accurate; 2) incorporating a large number of anatomical structures via a model assembly in the shape model improves the recognition and delineation accuracy dramatically; 3) ball-scale yields useful information about the relationship between the objects and the image; 4) intensity variation among scenes in an ensemble degrades object recognition performance.     

Hierarchical estimation of a dense deformation field for 3-D robust registration

A new method for medical image registration is formulated as a minimization problem involving robust estimators. We propose an efficient hierarchical optimization framework which is both multiresolution and multigrid. An anatomical segmentation of the cortex is introduced in the adaptive partitioning of the volume on which the multigrid minimization is based. This allows to limit the estimation to the areas of interest, to accelerate the algorithm, and to refine the estimation in specified areas. At each stage of the hierarchical estimation, we refine current estimate by seeking a piecewise affine model for the incremental deformation field. The performance of this method is numerically evaluated on simulated data and its benefits and robustness are shown on a database of 18 magnetic resonance imaging scans of the head.