具有交叉耦合结构的能量恢复型电路

本文从改变能量传输方式的观点出发讨论了ＣＭＯＳ电路中的绝热开关原理,并对如何实现恢复进行了分析。本言语重点对具有交 耦合结构的绝热电路的特性作了分析比较,并在ＰＡＬ电路诉基础上提出了一种与之相补的绝热电路－ＰＡＬ－１电路。     

三值绝热多米诺加法器开关级设计

通过对绝热多米诺电路和加法器的研究,该文提出一种新颖低功耗三值加法器的开关级设计方案。该方案首先利用开关-信号理论,结合绝热多米诺电路结构特点,推导出三值加法器本位和电路与进位电路的开关级结构式,由此得到一位三值加法器单元电路;然后通过单元电路的级联得到四位三值绝热多米诺加法器;最后,利用Spice软件对所设计的电路进行模拟,结果显示所设计的四位三值绝热多米诺加法器具有正确的逻辑功能,与四位常规多米诺三值加法器相比,能耗节省约61%。     

低功耗绝热SRAM

文章提出了一种新的绝热电路,并以该绝热电路为驱动,设计了一种低功耗绝热SRAM.由于所提出的绝热电路能以完全绝热的方式回收位线和字线上大开关电容的电荷,因此使该SRAM的功耗大大减小.我们采用0.25μm TSMC工艺,在时钟频率25～200MHz范围内对绝热SRAM进行了能耗和功能的HSPICE仿真,结果显示,与用传统的CMOS电路设计的SRAM相比,可节能80%左右.     

三值绝热多米诺文字运算电路开关级设计

通过对绝热多米诺电路和多值电路的研究,提出一种新颖的低功耗三值文字运算电路的开关级设计方案。该方案首先通过开关—信号理论推导出逻辑0和2的文字运算电路开关级结构式及电路;然后利用三种文字运算之间互斥与互补的约束关系得到逻辑1的文字运算输出信号,同时通过波形转换电路使电路的输出转换为较规则的缓变梯形波;最后利用Spice软件对所设计的电路进行仿真,结果显示所设计的三值绝热多米诺文字运算电路具有正确的逻辑功能,与常规多米诺三值文字运算电路相比,能耗节省约39%。     

三值低功耗多米诺JKL触发器设计及应用

通过对三值触发器和绝热多米诺电路的研究,提出一种新颖低功耗多米诺JKL触发器开关级设计方案。该方案首先利用开关—信号理论,根据三值JKL触发器真值表,推导出三值绝热多米诺JKL触发器开关级结构式;然后利用三值JKL触发器实现三值正循环门电路和三值反循环门电路的设计;最后,经Spice软件模拟证明所设计的三值绝热多米诺JKL触发器逻辑功能正确,与常规三值多米诺JKL触发器相比,能耗节省约69%。     

AC/DC开关电源建模与仿真研究

文章对全桥型开关电源结构进行分析,对关键元器件的作用、参数计算方法进行阐述。在Multisim仿真软件中搭建整体电路模型,研究改变电路参数对于电路性能的影响,验证开关电源仿真的可行性。针对"硬开关"产生的开关损耗问题,建立ZVS-移相全桥变换器的简化模型,仿真研究开关管的软开关过程。     

Boost变换电路的损耗分析

分析了开关器件、电感在硬开关Boost PFC电路中的损耗,并对Boost PFC变换器电路的开关损耗进行了计算,给出了其功率损耗的计算方法.同时通过对有源功率因数校正集成电路UC3854实现Sever Computer的600W开关电源的分析计算,用实验验证了Boost PFC电路功率损耗计算方法的正确性.     

PEEC结合有理缩减技术分析高速集成电路中同步开关噪声

利用部分元件等效电路（ＰＥＥＣ）方法分析高速集成电路系统中同步开关噪声,该方法相对其它等效电路方法及全波分析方法,具有简单、效率高,并可以和无源电路阶数缩减方法结合,进行大规模缩减,从而进一步提高计算速度。通过对电路中两种典型结构体（电源／接地板,电源板／信号线／接地板）上同步开关噪声的分析,表明这种方法是分析高速集成电路中同步开关噪声的高效方法。     

基于开关信号理论的控阈技术与三值ECL施密特电路

基于开关信号理论，本文对ＥＣＬ电路中的阈值控制进行了研究，建立了用于描述旋密特电路中阈值可控开关工作过程听数学表示式。在此基础上设计了具有二次跳阈反应的三值ＥＣＬ旋密特电路。对所设计电路的ＰＳＰＩＣＥ模拟表明它具有理想的施密特电路特性。     

利用开关电容技术的50Hz抑制滤波器及其PSpice仿真研究

文中对 2 912PCM双信道滤波电路进行了讨论 ,应用开关电容电路技术 ,将其进行变换和必要的简化。设计了集成 5 0Hz抑制滤波器电路 ,运用LM 12 4运算放大器及开关电容时域宏模型 ,开关电容的时钟频率选为 12 8kHz进行计算机模拟 ,其结果与理论计算值一致     

Low-power digital systems based on adiabatic-switching principles

Adiabatic switching is an approach to low-power digital circuits that differs fundamentally from other practical low-power techniques. When adiabatic switching is used, the signal energies stored on circuit capacitances may be recycled instead of dissipated as heat. We describe the fundamental adiabatic amplifier circuit and analyze its performance. The dissipation of the adiabatic amplifier is compared to that of conventional switching circuits, both for the case of a fixed voltage swing and the case when the voltage swing can be scaled to reduce power dissipation. We show how combinational and sequential adiabatic-switching logic circuits may be constructed and describe the timing restrictions required for adiabatic operation. Small chip-building experiments have been performed to validate the techniques and to analyse the associated circuit overhead     

Investigating the influence of adiabatic load on the 4-phase adiabatic system design

This paper investigates the power-clock generation using Step Charging Circuits (SCC). In particular, the impact of the adiabatic load on the energy dissipation of the 4-phase Power-Clock Generator (PCG) and on the overall adiabatic system is investigated. The adiabatic implementations are compared with their conventional CMOS counterparts based on energy dissipation, the number of transistors and operation time. The simulation results show that the area (number of transistors) influences the energy dissipation of SCC. Operation time affects the energy dissipation of the controller and degrades the energy benefits obtained in the energy dissipation of SCC and adiabatic core. Lastly, the impact of a number of steps on the energy efficiency of the 4-phase PCG is investigated. We compare the energy efficiency of the 4-phase PCG using 2-step, 3-step and 4-step charging circuit with the energy efficiency of the existing 4-phase PCG with and without resonant inductors.     

Study of Scaling Trends in Energy Recovery Logic: An Analytical Approach

This paper presents an analytical model to study the scaling trends in energy recovery logic. The energy performance of conventional CMOS and energy recovery logic are compared with scaling the design and technology parameters such as supply voltage, device threshold voltage and gate oxide thickness. The proposed analytical model is validated with simulation results at 90 nm and 65 nm CMOS technology nodes and predicts the scaling behavior accurately that help us to design an energy-efficient CMOS digital circuit design at the nanoscale. This research work shows the adiabatic switching as an ultra-low-power circuit technique for sub-100 nm digital CMOS circuit applications.     

A comprehensive analysis on the resilience of adiabatic logic families against transient faults

With the emergence of various battery operated technologies in different computing domains and the challenge of heating in such technologies, the issue of energy dissipation has become more critical than ever before. In such systems, energy constraints in one hand, and heat generation, on the other hand, necessitates the employment of energy efficient technologies in the fabrication of digital circuits. One possible solution for mitigating the energy dissipation in digital circuits is the use of adiabatic families in the process of designing computing devices. Adiabatic circuits are designed mainly based on the principles of thermodynamics and provide a paradigm shift in the design of digital systems. Nevertheless, their impact on the reliability of digital circuits due to susceptibility to soft errors has not been explored comprehensively. In this paper, we first try to survey some existing adiabatic logic families. Then we attempt to evaluate their reliability by validating their functionality under the effect of soft errors. Our evaluations which were conducted on a set of SPICE simulations have shown that amongst SCRL, 2LAL, RERL, PFAL, 2N2N2P and ECRL families the ECRL family is able to tolerate more than 90% of the injected transient faults and the applications with a high demand of reliability can use this family of adiabatic circuits. Furthermore, we will propose some suggestions for establishing reliable computations through adiabatic circuits.     

Energy Efficient Adiabatic Multiplier-Accumulator Design

This paper presents a strategy for minimizing non-adiabatic dissipation in adiabatic arithmetic units. The non-adiabatic dissipation is minimized by architectural design involving a small number of complex logic gates. Circuit design of complex adiabatic gates, based on ordered binary decision diagrams (OBDD), is introduced. An optimized architecture for adiabatic parallel multipliers is proposed and savings in energy dissipation over competing architectures are estimated. Experimental results obtained from implementation of an adiabatic multiply-accumulate (MAC) unit suggest that the proposed strategy provides substantial improvement in energy efficiency over equivalent non-adiabatic and alternative adiabatic implementations, while achieving a competitive operating speed.     

A Low-Power Stand-Alone Adaptive Circuit for Harvesting Energy From a Piezoelectric Micropower Generator

An adaptive energy-harvesting circuit with low power dissipation is presented and demonstrated, which is useful for efficient ac/dc voltage conversion of a piezoelectric micropower generator. The circuit operates stand-alone, and it extracts the piezoelectric strain energy independent of the load and piezoelectric parameters without using any external sensor. The circuit consists of a voltage-doubler rectifier, a step-down switching converter, and an analog controller operating with a single supply voltage in the range of 2.5–15 V. The controller uses the piezoelectric voltage as a feedback and regulates the rectified voltage to adaptively improve the extracted power. The nonscalable power dissipation of the controller unit is less than 0.05 mW, and the efficiency of the circuit is about 60% for output power levels above 0.5 mW. Experimental verifications of the circuit show the following: 1) the circuit notably increases the extracted power from a piezoelectric element compared to a simple full-bridge diode rectifier without control circuitry, and 2) the efficiency of the circuit is dominantly determined by its switching converter. The simplicity of the circuit facilitates the development of efficient piezoelectric energy harvesters for low-power applications such as wireless sensors and portable devices.      

单沟道传输门绝热触发器和相对绝热计算原理

该文从动态功耗在工程上有界限的观点出发,讨论单沟道传输门的相对绝热计算原理。在此基础上设计单沟道和双沟道传输门动态绝热锁存器,使其保存信息时,存储介质与外界隔离。将两种绝热锁存器进行比较、分析,并用计算机模拟程序检验其结果。     

A Novel Low-Power Logic Circuit Design Scheme

This brief proposes a novel low-power digital logic design scheme based on the energy exchange in the switched inductor-capacitor (SLC) circuit. It presents a design paradigm which in ideal case may lead to a circuit capable of performing logic operations with no switching losses. In traditional integrated circuit design, the energy is stored in the output load capacitor through a pull-up path (corresponding to storing a logic 1). When the output changes its logic value, this stored energy is dissipated through the pull down path to the ground. In order to reduce this switching energy dissipation each time the load capacitor is discharged, we store its energy in the magnetic field of the inductor in the proposed SLC architecture. Whenever the output load needs to be charged again, we transfer the energy back from the inductor to the load capacitor. This significantly reduces the switching energy. We illustrated the operation of the SLC architecture through SPICE simulation. A brief discussion of some practical considerations for this architecture is also presented     

Adiabatic dynamic logic

With adiabatic techniques for capacitor charging, theory suggests that it should be possible to build gates with arbitrarily small energy dissipation. In practice, the complexity of adiabatic approaches has made them impractical. We describe a new CMOS logic family-adiabatic dynamic logic (ADL)-that is the result of combining adiabatic theory with conventional CMOS dynamic logic. ADL gates are simple, general, readily cascadable, and may be fabricated in a standard CMOS process. A chain of 1000 ADL inverters has been constructed in 0.9 μm CMOS and successfully tested at 250 MHz. This result, together with comprehensive circuit simulation, suggest that ADL offers an order of magnitude reduction in power consumption over conventional CMOS circuitry