Reliable synthesis of logic circuits

The paper considers the construction of arbitrarily reliable logic circuits from unreliable components under more general fault assumptions than those of von Neumann and subsequent authors.Translated from Kibernetika i Sistemnyi Analiz, No. 3, pp. 167–172, May–June, 1992.     

Understanding yield losses in logic circuits

Yield improvement requires understanding failures and identifying potential sources of yield loss. We focus on diagnosing random logic circuits and classifying faults. We introduce an interesting scan-based diagnosis flow, which leverages the ATPG patterns originally generated for fault coverage. This flow shows an adequate link between the design automation tools and the testers and correlation between the ATPG patterns and the tester failure reports.     

Adaptive parallel logic networks

This paper presents a novel class of special purpose processors referred to as ASOCS (adaptive self-organizing concurrent systems). Intended applications include adaptive logic devices, robotics, process control, system malfunction management, and in general, applications of logic reasoning. ASOCS combines massive parallelism with self-organization to attain a distributed mechanism for adaptation. The ASOCS approach is based on an adaptive network composed of many simple computing elements (nodes) which operate in a combinational and asynchronous fashion. Problem specification (programming) is obtained by presenting to the system if-then rules expressed as Boolean conjunctions. New rules are added incrementally. In the current model, when conflicts occur, precedence is given to the most recent inputs. With each rule, desired network response is simply presented to the system, following which the network adjusts itself to maintain consistency and parsimony of representation. Data processing and adaptation form two separate phases of operation. During processing, the network acts as a parallel hardware circuit. Control of the adaptive process is distributed among the network nodes and efficiently exploits parallelism.     

Design of reversible logic based full adder in current-mode logic circuits

Demand of Very Large Scale Integration (VLSI) circuits with very high speed and low power are increased due to communication system's transmission speed increase. During computation, heat is dissipated by a traditional binary logic or logic gates. There will be one or more input and only one output in irreversible gates. Input cannot be reconstructed using those outputs. In low power VLSI, reversible logic is commonly preferred in recent days. Information is not lost in reversible gates and back computation is possible in reversible circuits with reduced power dissipation. Reversible full adder circuits are implemented in the previous work to optimize the design and speed of the circuits. Reversible logic gates like TSG, Peres, Feynman, Toffoli, Fredkin are mostly used for designing reversible circuits. However it does not produced a satisfactory result in terms of static power dissipation. In this proposed research work, reversible logic is implemented in the full adder of MOS Current-Mode Logic (MCML) to achieve high speed circuit design with reduced power consumption. In VLSI circuits, reliable performance and high speed operation is exhibited by a MCML when compared with CMOS logic family. Area and better power consumption can be produced implementing reversible logic in full adder of MCML. Minimum garbage output and constant inputs are used in reversible full adder. The experimental results shows that the proposed designed circuit achieves better performance compared with the existing reversible logic circuits such as Feynman gate based FA, Peres gate based FA, TSG based FA in terms of average power, static power dissipation, static current and area.     

Parsing electronic circuits in a logic grammar

Understanding circuits is a prerequisite for circuit design and trouble shooting. Circuit understanding by engineers is described as a process that starts with a structural analysis and then proceeds to a causal analysis. As a step toward automatic circuit understanding, a method for analyzing circuit structures is presented. In this method, a circuit is reviewed as a sentence and its elements as words. Circuit structures are defined by rules written in a logic grammar called definite clause set grammar (DCSG). Given circuits are decomposed into parse trees by the DCSG top-down parsing mechanism. These parse trees represent hierarchical structures of functional blocks. This representation is presented as one step in the process of automatic understanding of circuit structures     

Simulating logic circuits: A multiprocessor application

Circuits, especially logic circuits, are highly concurrent structures: signals flow along many parallel paths at once. This native concurrency, a function of both circuit size and topology, can be exploited in simulating these circuits on parallel machines. Simulation efficiency is affected by machine, language, and simulator implementation parameters like cycle speed, parallelism overhead, and partitioning of the circuit within the simulator, as well as by the amount of native concurrency. The experimental logic simulatorconsim, written in Multilisp and implemented on a 34 element shared-memory multiprocessor, was used to investigate these issues.     

A generalized fault simulator for combinational logic circuits

A generalized approach to the design of fault simulator using a library of simulation primitives is presented in this paper. A comprehensive set of simulation primitives has been developed using C programming language on the IBM PC. This library of simulation primitives has been used in realizing a fault simulator for automatic test pattern generation in combinational logic circuits. The fault simulator employs a combination of random pattern generation, concurrent fault simulation and the FAN algorithm for generating the complete set of test vectors to cover all the faults in the fault dictionary of the circuit under test. The library of simulation primitives is general enough to facilitate the development of fault simulators using any other test algorithms such as DALG or PODEM.     

Advanced fault collapsing [logic circuits testing]

The partitioning of faults into equivalence classes so that only one representative fault per class must be explicitly considered in fault simulation and test generation, called fault collapsing, is addressed. Two types of equivalence, which are relevant to the work reported, are summarized. New theorems on fault equivalence and dominance, forming the basis of an algorithm that collapses all the structurally equivalent faults in a circuit, plus many of the functionally equivalent faults, are presented. Application of the algorithm to a set of benchmark circuits establishes that identification of functionally equivalent faults is feasible, and that, in some cases, they are a large fraction of the faults in a circuit. The collapsing algorithm applies not only to combinational designs but to synchronous sequential circuits as well     

组合电路中逻辑错误诊断方法研究

介绍了近些年出现的几种错误诊断方法,它们在传统方法的基础上利用启发式对原有方法进行了不同程度的改进和提高,产生了较好的诊断结果.     

Complexity and synthesis of minimal logic circuits using multiplexers

A method is proposed for transforming the state table of a logic function into a minimum disjunction-conjunction formula of a multiplexer followed by its decomposition into standard multiplexer formulas.Translated from Kibernetika i Sistemnyi Analiz, No. 5, pp. 169–172, September–October, 1992.     

A comprehensive fault diagnosis technique for reversible logic circuits

Fault diagnosis is a complex and challenging problem in reversible logic circuits. The paper proposes a novel fault diagnosis technique for missing control faults in reversible logic circuits. The main focus of this technique is to extract the unique fault signature for each missing control fault in the circuit. The fault signatures are the sequences of test vectors to identify the location of the faults. Based on these fault signatures a unique fault diagnosis tree is built. Our proposed fault diagnosis algorithm is used to traverse the fault diagnosis tree to find the presence and location of the fault. The traversal process is simple and fast. The algorithm executes in linear time and experimental results for benchmark circuits show the reduction of test patterns compared to earlier works.     

使用逻辑锥分割的组合电路等价性验证

为了提高等价性验证在数字电路中的验证效率,提出一种逻辑锥分割和可满足性相结合的方法。通过划分规则把参照电路和实现电路划分成若干个逻辑锥,利用匹配技术对两者的逻辑锥进行匹配,将已匹配的两个逻辑锥的输出用一个异或门连接,从而得到Miter电路,将该结构转换成相应的合取范式,用可满足性引擎来验证Miter电路是否功能等价。在ISCAS’85基准电路的实验结果表明该方法的可行性。     

Neural net and Boolean satisfiability models of logic circuits

Two recently proposed models of digital circuits that are useful in parallel test-generation methods are described. In the neural net model, the input and output signal states of a logic gate are related through an energy function. In the Boolean satisfiability model, a logic gate is represented by a truth expression. How the equivalence of these models offers the flexibility of using the same algorithm in two different environments is shown. The models can be used in parallel methods for solving CAD problems such as simulation and test generation