一种基于扫描链阻塞技术的低费用测试方法

为进一步降低测试功耗及测试应用时间,提出一种基于扫描链阻塞技术且针对非相容测试向量的压缩方法.该方法考虑前后2个测试向量之间不相容的扫描子链,后一个测试向量可以由扫描输入移入若干位以及前一个测试向量的前若干位组合而成.实验结果表明,该方法能够有效减少测试应用时间,提升效率.     

SoC测试中低成本、低功耗的芯核包装方法

提出一种SoC测试中新颖的并行芯核包装方法（parallel core wrapper design,pCWD）,该包装方法利用扫描切片重叠这一特点,通过缩短包装扫描链长度来减少测试功耗和测试时间．为了进一步减少测试时间,还提出了一种测试向量扫描切片划分和赋值算法．实验结果表明,针对ITC2002基准SoC集中d695芯片,应用并行包装方法和测试向量切片划分及赋值算法,能够减少50％的测试时间及95％的测试功耗．     

基于树形解压缩器的低测试数据量方法

提出一种由异或门按照完全二叉树形状排列而成的树形向量解压缩器。该解压缩器的少数输出端需要由大部分的输入端来确定,而且该结构对其输出值的确定关系类似于扫描链中确定位的分布概率,可有效降低测试数据量。实验结果表明,对于ISCAS’89基准电路,该结构最高将测试数据量压缩了77倍。     

基于多扫描链的内建自测试技术中的测试向量生成

针对基于多扫描链的内建自测试技术,提出了一种测试向量生存方法。该方法用一个线性反馈移位寄存器（LFSR）作为伪随机测试向量生成器,同时给所有扫描链输入测试向量,并通过构造具有最小相关度的多扫描链克服扫描链间的相关性对故障覆盖率的影响。此外该方法经过模拟确定难测故障集,并针对这外难测故障集利用ATPG生成最小确定性测试向量集。最后丙依据得到的最小测试向量集来设计位改变逻辑电路,利用们改变逻辑电路控制改变扫描链上特定的值来实现对难测故障的检测,从而实现被测电路和故障完全检测。     

基于折叠计算的多扫描链BIST方案

为了减少测试数据的存储需求并降低测试应用时间,提出一种以折叠计算为理论的多扫描链BIST方案.首先利用输入精简技术在水平方向上压缩测试集,确定相容扫描链,在测试过程中对相容扫描链中的数据进行广播;然后利用折叠计算理论对测试集进行垂直方向上的压缩,使得同一折叠种子生成的相邻测试向量仅有1位不同,且在测试过程中测试向量并行移人多扫描链,在ISCAS标准电路上的实验结果表明,该方案的平均测试数据压缩率为95.07％,平均测试应用时间为之前方案的13.35％.     

基于TSP的低功耗低费用测试方法

扫描链阻塞技术可以有效地降低电路测试时的峰值和平均功耗,但是扫描测试应用时间有所增加。为了解决这一问题,通过有效利用测试向量之间的相容性,提出一种基于TSP问题的降低测试应用时间的方法。实验结果表明,该方法能够较大幅度地降低测试应用时间。     

扫描设计中扫描链的优化

提出了扫描法可测性设计中扫描链的优化方法。采用交迭测试体制和区间法能快速求出最优解。对于确定的测试向量集，用该方法构造的扫描链能使电路总的测试时间最少。     

单链扫描可测性设计中存储元件的排序

本文提出了扫描设计中存储元件在扫描链中的最优排序方法，采用交迭测试体制和区间法能快速求出最优解，对于确定的测试向量集，用该方法的构造的扫描链能使电路总的测试时间最少。     

基于边界扫描的板级测试向量自动生成

针对现有测试向量存在的不足,提出一种可施加到电路板扫描链上的测试向量自动生成方法,该方法利用被测电路的网络表文件和边界扫描描述语言文件,获取器件互连关系、边界扫描信息及扫描链路结构,结合测试算法生成板级测试向量,根据扫描链数目及连接关系将其扩展并生成可施加到扫描链上的链路级测试向量。实验结果表明,该方法能检测被测电路中多条扫描链的固定0、固定1、短路和开路故障,为测试系统提供了实用高效的测试向量。     

部分向量奇偶位切分的LFSR重新播种方法

提出一种基于部分测试向量奇偶位切分的LFSR重新播种测试方法.针对确定测试集中各个测试向量包含确定位的位数有较大差异以及测试向量所含的确定位大多连续成块的特点,通过奇偶切分部分确定位较多的向量,使得编码压缩的LFSR度数得到有效降低,从而提高了测试数据压缩率.其解压缩电路仍然采用单个LFSR进行解码与切分向量的合并.与目前国际同类编码压缩方法相比,具有测试数据压缩率高、解压硬件开销低、测试数据传输协议简单等特点.     

On Test Data Compression Using Selective Don't-Care Identification

This paper proposes an effective method for reducing test data volume under multiple scan chain designs. The proposed method is based on reduction of distinct scan vectors using selective don't-care identification. Selective don't-care identification is repeatedly executed under condition that each bit of frequent scan vectors is fixed to binary values (0 or 1). Besides, a code extension technique is adopted for improving compression efficiency with keeping decompressor circuits simple in the manner that the code length for infrequent scan vectors is designed as double of that for frequent ones. The effectiveness of the proposed method is shown through experiments for ISCAS'89 and ITC'99 benchmark circuits.     

On Test Data Compression Using Selective Don t-Care Identification

This paper proposes an effective method for reducing test data volume under multiple scan chain designs. The proposed method is based on reduction of distinct scan vectors using selective don‘t-care identification. Selective don‘t-care identification is repeatedly executed under condition that each bit of frequent scan vectors is fixed to binary values (0 or1). Besides, a code extension technique is adopted for improving compression efficiency with keeping decompressor circuits simple in the manner that the code length for infrequent scan vectors is designed as double of that for frequent ones. The effectiveness of the proposed method is shown through experiments for ISCAS‘89 and ITC‘99 benchmark circuits.     

Scan BIST with biased scan test signals

The conventional test-per-scan built-in self-test （BIST） scheme needs a number of shift cycles followed by one capture cycle. Fault effects received by the scan flipflops are shifted out while shifting in the next test vector like scan testing. Unlike deterministic testing, it is unnecessary to apply a complete test vector to the scan chains. A new scan-based BIST scheme is proposed by properly controlling the test signals of the scan chains. Different biased random values are assigned to the test signals of scan flip-flops in separate scan chains. Capture cycles can be inserted at any clock cycle if necessary. A new testability estimation procedure according to the proposed testing scheme is presented. A greedy procedure is proposed to select a weight for each scan chain. Experimental results show that the proposed method can improve test effectiveness of scan-based BIST greatly, and most circuits can obtain complete fault coverage or very close to complete fault coverage.     

VirtualScan: Test Compression Technology Using Combinational Logic and One-Pass ATPG

IC testing based on a full-scan design methodology and ATPG is the most widely used test strategy today. However, rapidly growing test costs are severely challenging the applicability of scan-based testing. Both test data size and number of test cycles increase drastically as circuit size grows and feature size shrinks. For a full-scan circuit, test data volume and test cycle count are both proportional to the number of test patterns N and the longest scan chain length L. To reduce test data volume and test cycle count, we can reduce N, L, or both. Earlier proposals focused on reducing the number of test patterns N through pattern compaction. All these proposals assume a 1-to-1 scan configuration, in which the number of internal scan chains equals the number of external scan I/O ports or test channels (two ports per channel) from ATE. Some have shown that ATPG for a circuit with multiple clocks using the multicapture clocking scheme, as opposed to one-hot clocking, generates a reduced number of test patterns.     

低成本的两级扫描测试结构

提出了一种两级扫描测试结构：根据电路结构信息对时序单元进行分组,同组的时序单元在测试生成电路中共享同一个伪输入;将时序单元划分到不同的时钟域,在测试向量的置入过程中只有很小一部分时序单元发生逻辑值的翻转;引入新的异或网络结构,消除了故障屏蔽效应.实验结果表明,该两级测试结构与以往的方法相比,在保证故障覆盖率的同时,大大降低了测试时间、测试功耗和测试数据量.     

UMC-Scan Test Methodology: Exploiting the Maximum Freedom of Multicasting

Industry has used scan-based designs widely to promote test quality. However, for larger designs, the growing test data volume has significantly increased test cost because of excessively long test times and elevated tester memory and external test channel requirements. To address these problems, researchers have proposed numerous test compression architectures. In this article, we propose a flexible scan test methodology called universal multicasting scan (UMC scan). It has three major features: First, it provides a better than state-of-the-art test compression ratio using multicasting. Second, it accepts any existing test patterns and doesn't need ATPG support. Third, unlike most previous multicasting schemes that use mapping logic to partition the scan chains into hard configurations, UMC scan's compatible scan chain groups are defined by control bits, as in the segmented addressable scan (SAS) architecture. We have developed several techniques to reduce the extra control bits so that the overall test compression ratio can approach that of the ideal multicasting scheme.     

Scan Cell Positioning for Boosting the Compression of Fan-Out Networks

Ensuring a high manufacturing test quality of an integrated electronic circuit mandates the application of a large volume test set. Even if the test data can be fit into the memory of an external tester, the consequent increase in test application time reflects into elevated production costs. Test data compression solutions have been proposed to address the test time and data volume problem by storing and delivering the test data in a compressed format, and subsequently by expanding the data on-chip. In this paper, we propose a scan cell positioning methodology that accompanies a compression technique in order to boost the compression ratio, and squash the test data even further. While we present the application of the proposed approach in conjunction with the fan-out based decompression architecture, this approach can be extended for application along with other compression solutions as well. The experimental results also confirm the compression enhancement of the proposed methodology.     

使用双重种子压缩的混合模式自测试

提出了一种基于扫描混合模式的内建自测试的新颖结构，为了减少确定测试模式的存储需求，它依赖一个双重种子压缩方案，采用编码折叠计数器种子作为一个LFSR种子，压缩确定测试立方体的个数以及它的宽度．这种建议的内建自测试结构是完全相容于标准的扫描设计，简单而具有柔性，并且多个逻辑芯核可以共享．实验结果表明，这种建议的方案比先前所公布方法需要更少的测试数据存储，并且具有相同的柔性和扫描相容性。     

Not every domain of a plain decompressor contains the domain of a prefix-free one

C. Calude, A. Nies, L. Staiger, and F. Stephan posed the following question about the relation between plain and prefix Kolmogorov complexities (see their paper in DLT 2008 conference proceedings): does the domain of every optimal decompressor contain the domain of some optimal prefix-free decompressor? In this paper we provide a negative answer to this question.