纳瓦级低功耗CMOS基准源研究与实现

工作在亚阈值区的2个MOS管栅压差值与温度成正比,基于这一理论,本文设计了一种纳瓦级功耗的带隙基准源电路.整体电路包括启动电路,一个纳安级电流源电路,一只双极晶体管和一个与绝对温度成正比(PTAT)的电压发生器.与传统CMOS带隙基准源相比,本文采用的结构具有更低的功耗.电路性能基于SMIC 0.18μm混合CMOS工艺仿真验证,结果显示此电路在1.8V电压下工作时,整体功耗120nW.     

0.18μm CMOS 5.1GHz低噪声放大器的设计

一种基于TSMC 0.18μm CMOS工艺的5.1GHz频率下的CMOS低噪声放大器。采用源极电感负反馈共源共栅电路结构,使放大器具有较高的增益和反相隔离度,保证较高的品质因数和信噪比。利用ADS对电路进行调试和优化,设计出低功耗、低噪声、高增益、高稳定性的低噪声放大器。通过ADS软件仿真得到较好的结果:在1.8V电压下,输入输出匹配良好,电路增益为16.12dB,噪声系数为1.87 dB,直流功耗为9.84mA*1.8V。     

CMOS 3～5GHz超宽带低噪声放大器的设计

设计了一个应用于超宽带(UWB)系统的3~5 GHz超宽带低噪声放大器.电路由二阶切比雪夫滤波器,电阻并联反馈,两级共源共栅结构,源级跟随器组成.低噪声放大器采用0.18 mCMOS工艺进行设计,利用ADS 2006 A进行仿真.结果表明,低噪声放大器在3~5 GHz带宽范围内噪声系数(NF)小于2dB,功率增益在23.9~24.8 dB之间,输入端口反射系数小于-10dB,输出端口反射系数小于-15dB,IIP3为-11dBm在1.8 V的电源电压下,核心电路功耗为10 mW.     

一种高电源抑制比带隙基准电压源的设计

采用共源共栅运算放大器作为驱动,设计了一种高电源抑制比和低温度系数的带隙基准电压源电路,并在TSMC 0.18μm CMOS工艺下,采用HSPICE进行了仿真.仿真结果表明:在-25～115℃温度范围内电路的温漂系数为9.69×10-6/℃,电源抑制比达到-100 dB,电源电压在2.5～4.5 V之间时输出电压Vref的摆动为0.2 mV,是一种有效的基准电压实现方法.     

一种用电流基准核作温度互补性补偿的基准电压源

为克服传统带隙基准源在温度性能上的缺陷,设计了一种低温度系数的带隙基准电路。该电路在传统电流模基准结构的基础上,引入一个工作在亚阈值区电流基准核产生的电流来达到高阶补偿的目的。在一阶补偿的基础上,补偿电流的进一步补偿,大大降低了基准输出的温度系数。电路设计采用0.18μm的CMOS工艺,利用Cadence软件的Spectre仿真工具对电路进行仿真,仿真结果表明,在2.7V电源电压下,基准输出电压为1.265V,温度在-40～125℃变化时,基准输出电压仅变化0.2mV,相比一阶补偿的变化（约为2.5mV）,精度提升了10多倍;电源电压在1.8～3.5V变化时,基准输出电压变化4.5mV;在出色的温度性能下有良好的抗干忧性,满足了高性能基准源的要求。     

一种新颖自偏置带隙基准电压源的设计

基于0.6μm BCD工艺参数,设计了一种新颖的低温漂、低功耗、高电源抑制比的自偏置带隙基准电压源.电路仿真结果表明:其工作电源电压低至1.7V,输出基准电压为1.24 V,温度系数仅6.68×10-6V/℃,电流消耗22 μA,电源抑制比高达82 dB.该电压源可广泛应用于模/数、数/模转换电路和电源管理芯片中.     

一种新型低压高精度CMOS电流源

采用低压与温度成正比基准源和衬底驱动低压运算放大器电路,设计了一种新型的低压高精度CMOS电流源电路,并采用TSMC 0.25μm CMOS Spice模型进行了电源特性、温度特性及工艺偏差的仿真．在室温下,当电源电压处于1.0～1.8V时,低压电流源输出电流I_out约为12.437～12.497μA;当温度在0～47℃范围内,输出电流为12.447μA;各种工艺偏差条件下的最大绝对偏差为0.54μA,与典型工艺模型下的相对偏差为4.34%．     

适用于802.11a的低噪声放大器设计

为实现802.11a接收单元,设计一款适用于802.11a协议具有镜像抑制功能的低噪声放大器(LNA).电路采用源简并结构,对有源陷波滤波器加以优化,可极大地减小了滤波网络的功耗和芯片面积,提高镜像抑制比,替代传统超外差接收机片外实现滤波器方式.电路采用Jazz 0.18μm SiGe BiCMOS进行工艺仿真,结果表明:在5.15~5.35GHz的工作频段和3.5~3.7GHz镜像频段下,电路可以实现18.52dB的功率增益,小于-13dB的反射系数,3.1~3.4dB的噪声系数和33.75dB的镜频抑制比;5.2GHz频率下的输入3阶交调点为-9.58dBm,电源电压为1.8V,总功耗为13mW,有源滤波器功耗仅为0.57mW.     

非线性补偿的低温漂低功耗CMOS带隙基准源的设计

设计了一种基于电流模式的具有非线性补偿的低温漂低功耗带隙基准电压源,在传统电路的基础上增加一个三极管和两个电阻达到对双极型晶体管的发射结电压VBE中与温度相关的非线性项的补偿。电路采用CSMC0.5μmDPTM CMOS工艺制造。该电路结构简单,在室温下的输出电压为1.217V,在?40℃～125℃的范围内温度系数为4.6ppm/,℃在2.6～4V之间的电源调整率为1.6mV/V。在3.3V的电源电压下整个电路的功耗仅为0.21mW。     

基于IEEE802.11a全集成低噪声放大器的设计

针对传统的宽带LNA普遍存在噪声系数大、芯片面积相对较大等不足,采用0.18 μm CMOS工艺设计了一种基于IEEF802.11a的全集成低噪声放大器(LNA),选用源级电感负反馈电路,实现了良好的输入匹配.调整偏置电压和MOS管的宽长比进行了噪声优化.后仿真结果表明,在5.15～5.825 GHz的频带范围内,增益S21大于16.03 dB,增益平坦度为1.51 dB,最大噪声系数和输入三阶截点分别为2.565 dB、-2.15 dBm.采用1.8V电源供电,电路总功耗约为13.29mW.     

高性能分段温度曲率补偿基准电压源设计

针对带隙基准电压源温漂高、电源抑制比(PSRR)低的问题,提出一种新颖的分段曲率补偿技术.该电路将基准源工作的全温度范围划分为3个区间,对各段温度区间进行不同的温度补偿,同时引入电流环负反馈结构,提高电路在低频时的电源抑制比,实现在-40～150℃内,温度系数为1.24×10-6,在DC时电源抑制比为-137dB.该电路采用TSMC0.6μmBCD工艺设计实现,芯片面积为0.5mm2,关断电流小于0.1μA,工作静态功耗为125μW.投片测试结果验证了电路设计的正确性,当电源电压为2.5～6.0V时,该基准源输出电压摆幅仅为0.220mV.     

Design of a low temperature coefficient bandgap reference with a wide temperature range

In order to meet the requirements of different applications and markets for the accuracy and reliability of IoT chips,a low temperature coefficient bandgap reference with a wide temperature range is proposed.On the basis of the traditional Banba bandgap reference structure,the circuit utilizes high-order temperature compensation technology and piecewise temperature compensation technology to improve the curvature of the output reference voltage.The temperature coefficient of the circuit is reduced.At the same time,the operating temperature range of the circuit is extended.The circuit performances are verified in the TSMC 180 nm CMOS process.Test results show that the temperature coefficient of the circuit is as low as 7.2×10^-6/℃ in the range of-40 ℃ to 160 ℃.The power supply rejection ratio at a low frequency is -48.52 dB.The static current under the 1.8 V power supply voltage is 68.38 μA,and the core area of the chip is 0.025 mm².     

Robust power-on reset circuit with brown-out detection

An on-chip power-on reset circuit with a brown-out detection capability is implemented in a0.18μm CMOS.A pF-order capacitor is charged with a proportional-to-absolute-temperature(PTAT)current from a bandgap reference with limited loop bandwidth and slow start-up feature,to generate a reset signal with high robustness and wide-range supply rise time.An embedded brown-out detector based on complementary voltage-to-current(V-to-I)conversion and current comparison can accurately respond to the brown-out event with high robustness over process and temperature when the supply is lower than 1.5V and the brown-out duration is longer than 0.1ms.The presented design with embedded offset voltage cancellation consumes a quiescent current of 8.5μA from a 1.8Vsupply and works over ambient temperature of-40°to 120°.     

Low-offset high-PSRR bandgap voltage reference

Based on the problem that the accuracy of the bandgap affects the performance of the integrated circuit, a novel BGR (bandgap voltage reference) is proposed. It utilizes a feedback compensation network to enhance PSRR and reduce the offset voltage, which improves the system stability and precision. Cadence spectre simulation has been done by the SMIC 018μm 1.8V CMOS process for validation. The results show that the achieved temperature coefficient is 34.6×10^-6/℃ over -30℃ to 100℃ and that the PSRR is -63.5dB at a low frequency. The power assumption is only 1.5μW. The circuit is suitable for a low-voltage low-power energy harvesting system.     

一种高精度低温漂带隙基准源的设计

该文参考了带隙基准电压源领域的现阶段技术,结合自偏置共源共栅电流镜以及适当的启动电路、补偿电路,设计了一种高精度、低温漂的多输出带隙基准电路。首先简述了传统带隙电压基准的基本原理,然后详细阐述了具体的各电路设计过程。该基准电压源可广泛应用于电源管理芯片等对能耗要求极高的芯片中。     

一种二阶曲率补偿的高精度带隙基准电压源

提出了一种输出电压可调的带隙基准电路．通过对双极晶体管基极-发射极电压的二阶温度补偿,大大改善了带隙基准的温度特性,并增加嵌套密勒补偿,进一步提高了系统的稳定性．基于0.6μm CMOS工艺,利用Hspice进行了仿真验证,结果表明,在-40～120℃温度范围内,0.8V基准电压的温度系数为6.1×10^-6／℃,低频时电源抑制比为-82dB,正常工作时静态工作电流小于6.5μA．     

A band-gap voltage reference for interface circuit of microsensor

A high performance CMOS band-gap voltage reference circuit that can be used in interface integrated circuit of microsensor and compatible with 0. 6 μm ( double poly) mix process is proposed in this paper. The circuit can be employed in the range of 1. 8 - 8 V and carry out the first-order PTAT ( proportional to absolute temperature) temperature compensation. Through using a two-stage op-amp with a NMOS input pair as a negative feedback op-amp,the PSRR ( power supply rejection ratio) of the entire circuit is increased,and the temperature coefficient of reference voltage is decreased. Results from HSPICE simulation show that the PSRR is - 72. 76 dB in the condition of low-frequency,the temperature coefficient is 2. 4 × 10 -6 in the temperature range from - 10 ℃ to 90 ℃ and the power dissipation is only 14 μW when the supply voltage is 1. 8 V.