Characterization of subthreshold MOS mismatch in transistors for VLSI systems

MOS transistor mismatch is revisited in the context of subthreshold operation and VLSI systems. We report experimental measurements from large transistor arrays with device sizes typical for digital and analog VLSI systems (areas between 9 and 400μm²). These are fabricated at different production qualified facilities in 40-nm gate oxide,n-well andp-well, mask lithography processes. Within the small area of our test-strips (3 mm²), transistor mismatch can be classified into four categories: random variations, “edge,” “striation,” and “gradient” effects. The edge effect manifests itself as a dependence of the transistor current on its position with reference to the surrounding structures. Contrary to what was previously believed, edge effects extend beyond the outer most devices in the array. The striation effect exhibits itself as a position-dependent variation in transistor current following a sinusoidal oscillation in space of slowly varying frequency. The gradient effect is also a position-dependent spatial variation but of much lower frequency. When systematic effects are removed from the data, the random variations follow an inverse linear dependence on the square root of transistor area.     

Translinear circuits using subthreshold floating-gate MOS transistors

We describe a family of current-mode circuits with multiple inputs and multiple outputs whose output currents are products and/or quotients of powers of the input currents. These circuits are made up of multipleinput floating-gate MOS (FGMOS) transistors operating in the subthreshold regime. The powers are set by capacitor ratios; hence, they can be quite accurate. We analyze the general family of such circuits and present experimental data from several members that we fabricated in a standard 2m double-poly p-well process through MOSIS.     

Characterisation and modeling of mismatch in MOS transistors for precision analog design

A characterization methodology is presented that accurately predicts the mismatch in drain current over a wide operating range using a minimum set of measured data. The physical causes of mismatch are discussed in detail for both p- and n-channel devices. Statistical methods are used to develop analytical models that relate the mismatch to the device dimensions. It is shown that these models are valid for small-geometry devices only. Extensive experimental data from a 3-/spl mu/m CMOS process are used to verify the models. The application of the transistor matching studies to the design of a high-performance digital-to-analog converter (DAC) is discussed. A circuit design methodology is presented that highlights the close interaction between the circuit yield and the matching accuracy of devices. It has been possible to achieve a circuit yield of greater than 97% as a result of the knowledge generated regarding the matching behavior of transistors and due to the systematic design approach.     

Impact of anomalous short-channel MOS transistors on VLSI circuit reliability

In VLSI and ULSI circuits, a major reliability concern is that completed, fully functional, in-specification integrated circuits may contain one or more anomalous transistors with substantially closer source-to-drain spacing than the minimum-design-rule devices, and that such transistors will be more susceptible to degradation or failure due to hot-carrier effects, total-dose-radiation effects or other instabilities. A further concern is that such vulnerable transistors will not be detected during conventional electrical testing or during typical high-reliability integrated circuit burn-in procedures such as static or dynamic burn-in at 125°C, since hot carrier effects tend to anneal out at elevated temperatures, as well as having a negative temperature acceleration factor.Experimental studies have shown that fully functional nMOS transistors with shorter-than-normal channel lengths can have many orders of magnitude greater susceptibility to hot-electron-induced threshold voltage shifts, compared to transistors with minimum-design-rule dimensions of 1.2μm. Total-dose radiation tests showed that anomalous n-channel MOS transistors can have orders-of magnitude higher post-total-dose radiation leakage than nominal devices made by the same process.Several possible types of screening techniques that can be considered for detecting integrated circuits containing anomalous transistors are discussed, including a low-dissipation dynamic stress test at room temperature or at −55°C, with parts electrically characterized before and after the stress test. A large change (delta) of certain critical parameters would be used to predict future failure. Quiescent CMOS supply-current testing could also be used to detect the presence of anomalous transistors in some types of integrated circuits.     

Influence of multi-finger layout on the subthreshold behavior of nanometer MOS transistors

This work studies the effects of number of gate finger on the DC subthreshold characteristics of multi-finger nanoscale MOS transistors. We found in not optimally-tempered nanoscale (gate length = 90 nm) MOS transistors that the significantly deteriorated subthreshold characteristics can be effectively improved by increasing the number of gate finger. This observation was explained with a modified subthreshold slope model based on voltage-doping transformation theory. Hence, the multi-finger structure does not only enhance the operation frequency, it also improves the subthreshold DC characteristics of the nanoscale MOS transistors.     

The accuracy and validity of the simulation of VLSI MOS transistors

Corrections of the concepts of the accuracy and validity of compact models of deep submicron MOS transistors are suggested for the circuit design of VLSIs.     

Optical subthreshold current method for extracting the interface states in MOS systems

Optical subthreshold current method (OSCM) is proposed for characterizing the interface states in MOS systems using the current-voltage characteristics under a photonic excitation. An optical source with a subbandgap (E/sub ph/相似文献   

MOS technology for VLSI

The scaling laws for MOS transistors are reviewed and the optimum performance predicted for both n-channel and p-channel devices are discussed. The physical and technological limitations for MOS VLSI are then described and some important technological challenges such as the implementation of new isolation techniques are pointed out. The mobility degragation effect due to velocity saturation is explained and illustrated by experimental data. The various limitations to the maximum operating voltage of scaleg devices are discussed. Finally, some considerations about speed and power consumption of scaled technologies are made.     

Translinear circuits in subthreshold MOS

In this paper we provide an overview of translinear circuit design using MOS transistors operating in subthreshold region. We contrast the bipolar and MOS subthreshold characteristics and extend the translinear principle to the subthreshold MOS ohmic region through a drain/source current decomposition. A front/back-gate current decomposition is adopted; this facilitates the analysis of translinear loops, including multiple input floating gate MOS transistors. Circuit examples drawn from working systems designed and fabricated in standard digital CMOS oriented process are used as vehicles to illustrate key design considerations, systematic analysis procedures, and limitations imposed by the structure and physics of MOS transistors. Finally, we present the design of an analog VLSI translinear system with over 590,000 transistors in subthreshold CMOS. This performs phototransduction, amplification, edge enhancement and local gain control at the pixel level.     

A surface potential and quasi-Fermi potential based drain current model for pocket-implanted MOS transistors in subthreshold regime

A subthreshold drain current model for pocket-implanted MOS transistors, incorporating both the drift and diffusion currents, is presented in this paper. In this model, the concept of splitting of the quasi-Fermi energy levels under nonequilibrium condition is used. It is well known that the surface potential based drain current models strongly depend on the potential profile of the channel. For short-channel devices, the end effect at the source and drain ends on the surface potential, and consequently on the drain current, cannot be ignored. The end effect gives rise to a position dependent potential profile, in contrast to a flat 1D profile in a long-channel device; which implies that both the drift and diffusion components are required to be considered for an accurate drain current. The concept of the gradient in the quasi-Fermi level is a convenient way to do so. In this work, a pseudo 2D potential profile which takes into account the vertical field due to the gate and the lateral field due to the source and drain junctions in addition to the difference in the flat-band voltage along the channel is used. Moreover, the mobility and the effective conduction layer depth used are also position dependent since the channel doping varies along the channel. Model predictions are compared with the results predicted by the 2D numerical device simulator DESSIS, and a very good agreement between the two are observed.     

Characterization of low 1/f noise in MOS transistors

By careful processing MOS transistors have been fabricated with a low value of the interface states density (2 × 10¹⁰/cm²eV). Consequently the1/fnoise in these devices is low and in the same order of magnitude as for junction FETs. The experimental values of the equivalent noise voltage and the equivalent noise current are compared to an expression derived from straight physical arguments. From the comparison it is concluded that the noise equivalent voltage in saturated operation is proportional to the effective gate voltage, the interface state density, and inversely proportional to the gate input capacitance. Moreover, it is concluded that a proper heat treatment not only reduces the number of states but also removes the near bandedge peaks, which usually appear in the trap distribution function.     

Bulk-drain connected load for subthreshold MOS current-mode logic

Bulk-drain connected PMOS transistors are proposed as loads for subthreshold MOS current-mode logic gates. Such loads exhibit an approximately linear dependence of the subthreshold drain-source current on the drain-source voltage, guaranteeing robust gate operation. The design and performance of an inverter gate and ring oscillator in a 0.25 mum CMOS technology are presented     

Modeling silicon emitters for VLSI transistors

The accuracy and reliability of predictions from numerical simulations of advanced bipolar transistors for VLSI applications depend on model input parameters. These parameters include the variations with doping and carrier concentrations in both n-type and p-type silicon of (1) the valance and conduction band edges, (2) the effective intrinsic carrier concentrations, (3) the minority carrier mobilities, and (4) the minority carrier lifetimes. This paper reviews recent advances in device physics for modeling the emitters of bipolar transistors with submicrometer dimensions and high concentrations of dopant ions and carriers.     

Statistical analysis of subthreshold leakage current for VLSI circuits

We develop a method to estimate the variation of leakage current due to both intra-die and inter-die gate length process variability. We derive an analytical expression to estimate the probability density function (PDF) of the leakage current for stacked devices found in CMOS gates. These distributions of individual gate leakage currents are then combined to obtain the mean and variance of the leakage current for an entire circuit. We also present an approach to account for both the inter- and intra-die gate length variations to ensure that the circuit leakage PDF correctly models both types of variation. The proposed methods were implemented and tested on a number of benchmark circuits. Comparison to Monte Carlo simulation validates the accuracy of the proposed method and demonstrates the efficiency of the proposed analysis method. Comparison with traditional deterministic leakage current analysis demonstrates the need for statistical methods for leakage current analysis.     

Modeling MOS VLSI circuits for transient analysis

Modeling plays a significant role in the efficient simulation of VLSI circuits. By simplifying the models used to analyze these circuits, it is possible to perform transient analyses with reasonable accuracy at speeds of one or two orders of magnitude faster than in conventional circuit simulation programs. The author discusses the models that are used in the second-generation MOTIS timing simulator. The methods used have been applied to a wide variety of MOS digital integrated circuits. All MOS transistors are modeled as voltage-controlled current sources using multidimensional tables. The actual currents are computed by approximation using variation-diminishing tensor splines. Nonlinear device capacitances in the circuit are approximated using linear models which are derived from experimental simulations using a circuit simulator. At the subcircuit level, special structures in the circuit are identified automatically by a preprocessor and are modeled using macro-models. Driver-load MOS transistor gates and bootstrapped circuits are examples of these structures. Their modeling is achieved by an experimental process before implementation in the preprocessor. The simplifications in the device and circuit models presented here have provided a significant improvement in the speed of transient analysis for large MOS digital circuits with relatively little loss in accuracy. This has resulted in a viable design verification environment using MOTIS.     

Conductance of MOS transistors in saturation

The output conductance of MOS transistors operating in the saturation region is studied theoretically and experimentally. A simple physical model is described which accounts for the modification of the electric field in the drain depletion region near the Si-SiO2interface, due to the presence of the gate electrode. The saturation conductance is shown on the basis of this model to be a sensitive function of the oxide thickness as well as the substrate impurity concentration. Good agreement is obtained between theory and experiment over a wide range of device parameters. The characteristics of lowly doped very-short-channel devices, which depart from this theory, are also discussed. The departure is shown to be due to a "punch-through"-type phenomenon.     

Design calculations for MOS field effect transistors

Design equations for the Metal-Oxide-Semiconductor Field Effect Transistor are developed. Approximate solutions for static characteristics, transconductance, and frequency cutoff are presented for the case of a very high resistivity substrate. Specific sets of static characteristics from computer calculations are presented graphically to illustrate the effects of oxide thickness and various substrate resistivities.     

v-E dependence in small-sized MOS transistors

It is demonstrated that the hyperbolic relation for the v-E dependence which is usually used in transistor modeling, does not hold in short-channel MOSFET's (L_{eff} < 5µm). A new v-E relation is proposed, which is a surface modification of the Scharfetter-Gummel formula and which takes into account the pronounced role of warm electrons. The analysis shows that the lateral electric field at the source determines the transport properties in the channel. A comparison of theoretical results with experimental data is given.