Scanning tunneling microscopy investigation of the microtopography of SiO2 and Si surfaces at the Si/SiO2 interface in SIMOX structures

The microtopography of silicon and silicon oxide surfaces in SIMOX structures is investigated by scanning tunneling microscopy. A method of using scanning tunneling microscopy to study Si/SiO₂ interfacial roughness is developed for this purpose. It is shown that the relief of the silicon surface in SIMOX structures is smoother than that of the oxide surface. The observed Si/SiO₂ interfacial roughness is due to oxygen ion implantation in the silicon single crystal. The roughness of the SiO₂ and Si surfaces at the Si/SiO₂ interface is compared for the standard and high-temperature oxidation of the silicon single crystal. Fiz. Tekh. Poluprovodn. 33, 708–711 (June 1999)     

Characterization of interface state density of three-dimensional Si nanostructure by charge pumping measurement

Adopting the gated p–i–n diode configuration, the interface state density (D_it) at the Si/SiO₂ interface of Si fin structures on Silicon-on-Insulator (SOI) wafers has been systematically studied using charge pumping method. The optimal forming gas annealing temperature for the three-dimensional (3D) surface is extracted. A new methodology for separately quantifying the local D_it at different regions of the 3D surfaces (i.e., the top/side walls and the corners) is also derived by characterizing the fins with various widths and the planar counterparts. The results validate the necessity to independently consider the corner regions, at which substantially high local D_it situates, and thus further clarify the origin of high D_it at 3D surfaces.     

Use of electron cyclotron resonance plasmas to prepare CdZnTe (211)B substrates for HgCdTe molecular beam epitaxy

Without any additional preparation, Cd_1−yZn_yTe (211)B (y∼3.5%) wafers were cleaned by exposure to an electron cyclotron resonance (ECR) Ar/H₂ plasma and used as substrates for HgCdTe molecular beam epitaxy. Auger electron spectra were taken from as-received wafers, conventionally prepared wafers (bromine: methanol etching, followed by heating to 330–340°C), and wafers prepared under a variety of ECR process conditions. Surfaces of as-received wafers contained ∼1.5 monolayers of contaminants (oxygen, carbon, and chlorine). Conventionally prepared wafers had ∼1/4 monolayer of carbon contamination, as well as excess tellurium and/or excess zinc depending on the heating process used. Auger spectra from plasma-treated CdZnTe wafers showed surfaces free from contamination, with the expected stoichiometry. Stoichiometry and surface cleanliness were insensitive to the duration of plasma exposure (2–20 s) and to changes in radio frequency input power (20–100 W). Reflection high energy electron diffraction patterns were streaked indicating microscopically smooth and ordered surfaces. The smoothness of plasma-etched CdZnTe wafers was further confirmed ex situ using interferometric microscopy. Surface roughness values of ∼0.4 nm were measured. Characteristics of HgCdTe epilayers deposited on wafers prepared with plasma and conventional etching were found to be comparable. For these epilayers, etch pit densities on the order of 10⁵ cm⁻² have been achieved. ECR Ar/H₂ plasma cleaning is now utilized at Night Vision and Electronic Sensors Directorate as the baseline CdZnTe surface preparation technique.     

Silicon wafer wettability and aging behaviors: Impact on gold thin-film morphology

This paper reports on the wettability and aging behaviors of the silicon wafers that had been cleaned using a piranha (3:1 mixture of sulfuric acid (H₂SO₄, 96%) and hydrogen peroxide (H₂O₂, 30%), 120 °C), SC1 (1:1:5 mixture of NH₄OH, H₂O₂ and H₂O, at 80 °C) or HF solution (6 parts of 40% NH₄F and 1 part of 49% HF, at room temperature) solution, and treated with gaseous plasma. The silicon wafers cleaned using the piranha or SC1 solution were hydrophilic, and the water contact angles on the surfaces would increase along with aging time, until they reached the saturated points of around 70°. The contact angle increase rate of these wafers in a vacuum was much faster than that in the open air, because of loss of water, which was physically adsorbed on the wafer surfaces. The silicon wafers cleaned with the HF solution were hydrophobic. Their contact angle decreased in the atmosphere, while it increased in the vacuum up to 95°. Gold thin films deposited on the hydrophilic wafers were smoother than that deposited on the hydrophobic wafers, because the numerous oxygen groups formed on the hydrophilic surfaces would react with gold adatoms in the sputtering process to form a continuous thin film at the nucleation stage. The argon, nitrogen, oxygen gas plasma treatments could change the silicon wafer surfaces from hydrophobic to hydrophilic by creating a thin (around 2.5 nm) silicon dioxide film, which could be utilized to improve the roughness and adhesion of the gold thin film.     

Plasma etching of different polydimethylsiloxane elastomers, effects from process parameters and elastomer composition

Plasma etching of three different polydimethylsiloxane elastomers has been studied. One elastomer was a commercially available kit (Sylgard-184) and the other two were made by mixing individual components. The etching was done in a multi-wafer tool. The process gas used in the etching was a mixture of SF₆ and O₂. The etch rate was measured as a function of pressure for all three materials at the centre and the edge of the etched structures. It was found that fillers in the elastomer reduces the etch rate but has little effect on the shape of the etched surface. Second, it was found that excess of chain ends in the elastomer gives larger changes in the shape of the etched surface, as pressure changes. Third, it was found that loading (reduction of etch rate) is significant in the presence of dummy silicon wafers compared to glass wafers.     

Spray coating of PMMA for pattern transfer via electron beam lithography on surfaces with high topography

Spray coating of polymethylmethacrylate (PMMA) as electron beam resist on non planar surfaces is presented as a reliable technique for deposition of uniform resist layers with adjustable thickness at wafer scale. In the experiments a commercial spray coating system with an ultrasonic spray nozzle was used. Parameters which influence the quality of the resist layer with respect to uniformity across a 4 in Si wafer, such as ultrasonic power and dispensed volume, were evaluated. The suitability of spray coated PMMA for the pattern transfer on surfaces with high topography was proven by PMMA spray coating of 8 μm deep trenches etched into Si wafers. The PMMA was then electron beam exposed and chromium line patterns were transferred on the Si surface via a lift-off process.     

Novel abrasive-free planarization of 4H-SiC (0001) using catalyst

A new abrasive-free planarization method for silicon carbide (SiC) wafers was proposed using the catalytic nature of platinum (Pt). We named it catalyst-referred etching (CARE). The setup equipped with a polishing pad made of Pt is almost the same as the lapping setup. However, CARE chemically removes SiC with an etching agent activated by a catalyst in contrast to mechanical removal by the lapping process. Hydrofluoric acid which is well known as an etchant of silicon dioxide (SiO₂) that cannot etch SiC, was used as the source of the etching agent to SiC. The processed surfaces were observed by Nomarski differential interference contrast (NDIC) microscopy, atomic force microscopy (AFM), and optical interferometry. Those observations presented a marked reduction in surface roughness. Moreover, low-energy electron diffraction (LEED) images showed that a crystallographically well-ordered surface was realized.     

Effect of additive N2 and Ar gases on surface smoothening and fracture strength of Si wafers during high-speed chemical dry thinning

In this work, we investigated the changes in the surface roughness and fracture strength of bare or mechanically ground Si wafers caused by high-speed chemical dry etching. High-speed chemical dry thinning was achieved by injecting NO gas and additive N₂ and Ar gases directly into the reactor during the supply of F radicals from NF₃ remote plasmas. With the additional injection of N₂ and Ar gases, together with the direct-injected NO gas, the rough surfaces of the mechanically ground Si wafers could be effectively smoothened while keeping the thinning rate of Si very fast, viz. up to 18.2 μm/min. The additive N₂ gas reduced the wafer surface temperature after thinning. The fracture strength of the Si wafers thinned down to 50 μm by the chemical dry etching process was more highly increased, due to the more effective removal of the mechanical damage and stress generated during the mechanical grinding process, as compared to the other final thinning methods such as lapping or plasma etching. The results indicated that the high-speed dry chemical thinning process could be used for the ultra-thin final thinning of Si wafers for next generation three-dimensional packaging technologies.     

Test Structures for the Characterization of MEMS and CMOS Integration Technology

Test structures have been used to study the feasibility of bonding MEMS to CMOS wafers to create an integrated system. This involves bonding of prefabricated wafers and creating interconnects between the bonded wafers. Bonding of prefabricated wafers has been demonstrated using a chemical–mechanical polishing enabled surface planarization process and an oxygen plasma assisted low temperature wafer bonding process. Two interwafer connection approaches have been evaluated. For an oxide bonding approach, interconnects between wafers are established through contact vias, using a standard multilevel metallization process after the wafer bonding process. Resistances of 3.8–5.2 $Omega $ have been obtained from via chain test structures and an average specific contact resistivity of 1.7$,times ,$10$^{-8} Omega {hbox{cm}}^{2}$ , measured from the single via Kelvin structures. For a direct metal contact approach, electrical connections have been achieved during the bonding anneal stage due to stress relief of the aluminium film.      

GaAs/InP低温晶片键合的研究

将硫脲溶液用于GaAs/InP基材料低温晶片键合的表面处理工艺,实现了GaAs/InP基材料间简单、无毒性的低温(380 ℃)晶片键合.并通过界面形貌,解理后断裂面,键合强度及键合界面I-V特性对键合晶片进行了分析.     

Fabrication and photosensitivity of heterojunctions based on CuIn<Subscript>3</Subscript>Se<Subscript>5</Subscript> crystals

Heterojunctions based on p-CuIn₃Se₅ crystals are fabricated by magnetron sputtering of an n-ZnO:Al target and by putting naturally cleaved n-GaSe thin wafers onto polished surfaces of p-CuIn₃Se₅ wafers. The current-voltage characteristics and mechanisms of current flow in the diodes under study are analyzed. The photovoltaic effect revealed in the fabricated structures is discussed. It is shown that the fabricated photosensitive heterojunctions are promising for the development of selective analyzers of linearly polarized radiation.     

Selective etching of Si,SiGe, Ge and its usage for increasing the efficiency of silicon solar cells

Dependences of the etch rates for KOH and HF:H₂O₂:CH₃COOH solutions on SiGe layer composition were investigated. The obtained results has been proposed to use for formation of the submicron relief on the silicon surface via selective etching of the structures with Ge(Si) self-assembled nanoislands. In the framework of the proposed approach the Ge(Si) nanoislands serve as a mask for selective etching of Si in a mixture of an aqueous solution of KOH with isopropyl alcohol, followed by the islands removal from the surface by the selective etching in HF:H₂O₂:CH₃COOH. It was demonstrated experimentally that such approach allows to produce the submicron relief on a silicon surface, which leads to the significant decrease of the reflectivity in a wide spectral range. It is believed that the proposed method of surface relief formation can be used to improve the efficiency of the thin-film solar cells based on the crystalline silicon.     

Uniformity optimization techniques for rapid thermal processingsystems

This paper presents two efficient robust methods for uniformity optimization of rapid thermal processes. Both of these methods involve the reuse of empirical response surfaces linking zone powers to measured process data created on a baseline system. The first method uses fossilized gain matrices from the baseline system, while the second method involves customization of the baseline response surface for each system. The approaches use the response surfaces for iterative modification of zone powers to reduce the process nonuniformity on successively processed wafers. These methods are applied to the optimization of rapid thermal oxidation processes on several lamp-heated rapid thermal processing systems. Most of the uniformity improvement is obtained with the first two optimization runs; in some instances, the process is optimized to less than 1% 1-sigma nonuniformity with the use of just two wafers. Because the response surfaces from the baseline system can be reused for all similar systems, considerable savings in time and wafers are realized     

X-ray reflectivity of silicon on insulator wafers

The ability of X-ray reflectivity to analyse different silicon on insulator structures is underlined. The standard geometry with first reflection occurring at the surface gives information about the thickness, roughness, and density of the layers. Deeply buried interfaces, i.e. in between thick wafers, are analysed with a non-standard geometry (the first reflection occurs at the buried interface) and with a high-energy radiation. These two methods are, respectively, illustrated by the reflectivity measurements of (SiO₂/Si/SiO₂|bulk Si) and (bulk Si/thermal SiO₂|native SiO₂/bulk Si) bonded structures, and are explained in the framework of kinematic theory of X-ray reflectivity.     

Photosensitivity of a-C:H/c-Si heterojunctions

Layers of a-C:H were grown on c-Si wafers by the glow discharge method in a CH₄ + Ar gaseous mixture. The electrical and photoelectric properties of a-C:H/c-Si heterojunctions were studied. It was found that the heterojunctions display rectification and broad-band photovoltaic effects. It is shown that the polarization sensitivity in these structures occurs at an oblique incidence of linearly polarized light under the illumination of the surface coated with a-C:H layers. The observed oscillations in the spectrum of the coefficient of induced photopleochroism are attributed to the interference of light in these layers.     

沉积在聚合物表面上的金属薄膜自发形成图案的实验研究

用离子溅射法在聚二甲基硅氧（polydimethylsiloxane,PDMS）表面沉积的金膜因金属与聚合物之间热膨胀系数的差异从而导致了具有正弦界面、微米尺度的波长和振幅的复杂而有序的褶皱图案。用光刘技术在硅片制备图形结构作为模板,通过复制模铸得到表面具有浮雕结构的聚二甲基硅氧烷基片。改变浮雕结构可以调控其上沉积的金膜的褶皱图案呈规则有序的排列。这种多尺度的复合结构将光刘技术、复制模铸和物理自组装等有效结合,可广泛应用于微纳制造领域。     

Texturization of silicon wafers with Na2CO3 and Na2CO3/NaHCO3 solutions for heterojunction solar-cell applications

The formation of pyramidal structures by anisotropic etching of 〈1 0 0〉-oriented monocrystalline silicon wafer surfaces is an effective method to reduce reflection losses originating on the front side of conventional silicon solar cells and silicon-heterojunction (SHJ) solar cells. One of the most common methods of texturization used in the solar-cell industry is based on aqueous solutions of NaOH or KOH and isopropyl alcohol (IPA). However, IPA is toxic and relatively expensive, so efforts are being made to replace it. Among the potential alternatives, solutions based on Na₂CO₃ and Na₂CO₃/NaHCO₃ mixtures have been proposed. In the present study, solutions of Na₂CO₃ and Na₂CO₃/NaHCO₃ mixtures were prepared in order to form pyramidal structures on silicon wafer surfaces. It was not possible to obtain uniform and completely textured surfaces by using aqueous solutions consisting only of Na₂CO₃. NaHCO₃ must be added in order to achieve uniform textured surfaces with low hemispherical reflectance suitable for SHJ solar-cell applications. Textured surfaces with good uniformity and low average hemispherical reflectance (15.4%) were prepared from 〈1 0 0〉 silicon substrates with relatively low etching times (25 min). Good surface passivation (lifetime >600 μs and implicit open-circuit voltage of 690±10 mV) on these p-type textured wafers were achieved.     

Biomimetic Pattern Transfer

Biological systems routinely use phenols to construct complex materials with diverse functions. Typically, these phenolic materials are generated using oxidative enzymes to initiate a cascade of uncatalyzed reactions. We mimic these processes to micropattern films of the aminopolysaccharide chitosan. Specifically, we microfabricate silicon wafers to have gold patterns, cast a chitosan film onto the patterned wafers, and commence pattern transfer by polarizing the underlying gold surfaces to electrochemically initiate the phenol reaction cascade. The electrochemically initiated reactions lead to modification of the chitosan film's chemistry, structure, and fluorescence. Further, electrochemically initiated modification of the chitosan film is localized to the interfacial region between the film and the anode, with resolution in the lateral direction of at least 20 μm. These results demonstrate that electrochemical pattern transfer provides a promising new method for micropatterning flexible films.     

Surface gettering of background impurities and defects in GaAs wafers

The first data on surface gettering of background impurities and defects from the bulk of single-crystal undoped GaAs(111) wafers are reported. The wafers were 1.6 mm thick, with an initial electron density of (1–3)×10¹⁵ cm^?3 and a mobility of 1500–2000 cm²/(V s) at room temperature. The wafers were cut from single crystals grown by the Czochralski method from a nonstoichiometric As-enriched Ga-As melt. Gettering was carried out during thermal treatment of the wafers in hydrogen at 400–850°C, with the preliminary deposited layer of Y or SiO₂ 1000 Å thick. As a result of gettering, the charge carrier density decreased to 10⁸–10¹⁰ cm^?3, while the mobility increased to 7000 cm²/(V s).     

Gettering by heat thermal processing: application in crystalline silicon solar cells

The aim of this work is to getter unwanted impurities from solar grade crystalline silicon (Si) wafers and then to enhance their electronic properties. This was done by forming a sacrificial porous silicon (PS) layer on both sides of the Si wafers and by performing infrared (IR) thermal annealing treatments (at around 950 °C) in a SiCl₄/N₂ controlled atmosphere. The process allows concentrating unwanted impurities in the PS layer and near the PS/silicon interface. These treatments reduce the resistivity by about two orders of magnitude at a depth of about 40 μm and improve the minority carrier diffusion length from 75 to 210 μm. This gettering method was also tested on silicon wafers where grooved fingers and back contacts were achieved using a chemical vapor etching (CVE) method. Front buried metallic contacts and small holes for local back surface field were then achieved after the gettering stage in order to realize silicon solar cells. It was shown that the photovoltaic parameters of gettered silicon solar cells were improved as regard to ungettered ones.