Soft-Output BEAST Decoding With Application to Product Codes

A Bidirectional Efficient Algorithm for Searching code Trees (BEAST) is proposed for efficient soft-output decoding of block codes and concatenated block codes. BEAST operates on trees corresponding to the minimal trellis of a block code and finds a list of the most probable codewords. The complexity of the BEAST search is significantly lower than the complexity of trellis-based algorithms, such as the Viterbi algorithm and its list generalizations. The outputs of BEAST, a list of best codewords and their metrics, are used to obtain approximate a posteriori probabilities (APPs) of the transmitted symbols, yielding a soft-input soft-output (SISO) symbol decoder referred to as the BEAST-APP decoder. This decoder is employed as a component decoder in iterative schemes for decoding of product and incomplete product codes. Its performance and convergence behavior are investigated using extrinsic information transfer (EXIT) charts and compared to existing decoding schemes. It is shown that the BEAST-APP decoder achieves performances close to the Bahl–Cocke–Jelinek–Raviv (BCJR) decoder with a substantially lower computational complexity.      

Near-optimum decoding of product codes: block turbo codes

This paper describes an iterative decoding algorithm for any product code built using linear block codes. It is based on soft-input/soft-output decoders for decoding the component codes so that near-optimum performance is obtained at each iteration. This soft-input/soft-output decoder is a Chase decoder which delivers soft outputs instead of binary decisions. The soft output of the decoder is an estimation of the log-likelihood ratio (LLR) of the binary decisions given by the Chase decoder. The theoretical justifications of this algorithm are developed and the method used for computing the soft output is fully described. The iterative decoding of product codes is also known as the block turbo code (BTC) because the concept is quite similar to turbo codes based on iterative decoding of concatenated recursive convolutional codes. The performance of different Bose-Chaudhuri-Hocquenghem (BCH)-BTCs are given for the Gaussian and the Rayleigh channel. Performance on the Gaussian channel indicates that data transmission at 0.8 dB of Shannon's limit or more than 98% (R/C>0.98) of channel capacity can be achieved with high-code-rate BTC using only four iterations. For the Rayleigh channel, the slope of the bit-error rate (BER) curve is as steep as for the Gaussian channel without using channel state information     

Adaptive Channel Estimation Aided Log-Map Turbo Decoder Implementation for DS-CDMA Based Mobile Systems

Practical implementation of convolutional turbo codec is impeded by the difficulty of real-time execution in high transmission rate communication systems due to high computational complexity, iterative block decoding structure, as well as the requirement of accurate on-line channel reliability estimation for maximum-likelihood decoding. Relying on innovative channel estimation techniques involving DS-CDMA specific noise/interference variance estimation and fading channel variation tracking, this paper provides a low-complexity all-digital design of an iterative SISO log-MAP turbo decoder for DS-CDMA based mobile communication systems. The issues of quantization and data flow in both pre-decoder processing module and iterative trellis decoding module are prudently addressed to ensure highly efficient hardware implementation. The efficient design strategies applied confine the decoding complexity while leading to an excellent performance within 0.2 dB of the software decoder.     

一种改善Turbo乘积编码OFDM系统性能的新方法

本文提出一种利用对译码器软信息限幅来改善多径衰落信道中Turbo乘积编码OFDM(TPC-OFDM)系统性能的新方法。通过对不同多径衰落信道中QPSK映射和16QAM映射的TPC-OFDM系统性能的数值仿真，结果表明在10^-5误比特率下，这种新方法比传统的迭代译码大约有6～10dB的改进，对严重多径环境下TPC-OFDM系统的错误平底也有明显的改进。     

A soft-input soft-output APP module for iterative decoding ofconcatenated codes

Concatenated coding schemes consist of the combination of two or more simple constituent encoders and interleavers. The parallel concatenation known as “turbo code” has been shown to yield remarkable coding gains close to theoretical limits, yet admitting a relatively simple iterative decoding technique. The recently proposed serial concatenation of interleaved codes may offer superior performance to that of turbo codes. In both coding schemes, the core of the iterative decoding structure is a soft-input soft-output (SISO) a posteriori probability (APP) module. In this letter, we describe the SISO APP module that updates the APP's corresponding to the input and the output bits, of a code, and show how to embed it into an iterative decoder for a new hybrid concatenation of three codes, to fully exploit the benefits of the proposed SISO APP module     

Double-Binary Circular Turbo Decoding Based on Border Metric Encoding

This brief presents an energy-efficient soft-input soft-output (SISO) decoder based on border metric encoding, which is especially suitable for nonbinary circular turbo codes. In the proposed method, the size of the branch memory is reduced to half and the dummy calculation is removed at the cost of a small-sized memory that holds encoded border metrics. Due to the infrequent accesses to the border memory and its small size, the energy consumed for SISO decoding is reduced by 26.2%. Based on the proposed SISO decoder and the dedicated hardware interleaver, a double-binary tail-biting turbo decoder is designed for the WiMAX standard using a 0.18-mum CMOS process, which can support 24.26 Mbps at 200 MHz.     

Bit-Level Extrinsic Information Exchange Method for Double-Binary Turbo Codes

Nonbinary turbo codes have many advantages over single-binary turbo codes, but their decoder implementations require much more memory, particularly for storing symbolic extrinsic information to be exchanged between two soft-input–soft-output (SISO) decoders. To reduce the memory size required for double-binary turbo decoding, this paper presents a new method to convert symbolic extrinsic information to bit-level information and vice versa. By exchanging bit-level extrinsic information, the number of extrinsic information values to be exchanged in double-binary turbo decoding is reduced to the same amount as that in single-binary turbo decoding. A double-binary turbo decoder is designed for the WiMAX standard to verify the proposed method, which reduces the total memory size by 20%.      

Refinements and asymptotic performance of bandwidth-efficient turbo product codes

In this letter, a turbo product code (TPC) is combined with multilevel modulations (8-phase-shift keying and 16-quadrature amplitude modulation). The component codes are Bose-Chaudhuri-Hocquengem (BCH) or extended BCH. We derive soft-input/soft-output modules based on the dual code, with exact Euclidean metrics, and we show that the iterative TPC decoder gains no advantage in performance from this. Next, we evaluate asymptotic approximations for maximum-likelihood (ML) decoding from a combinatorial approach that can be applied to any bit-interleaved multilevel modulated code, once the first term (or terms) of the Hamming weight spectrum are known. For the TPCs and modulations studied in this letter, random bit interleaving before modulation leads to improved ML asymptotes. Simulations confirm that this advantage is maintained also under iterative decoding.     

Iterative Source-Channel Decoding With Markov Random Field Source Models

We propose a joint source-channel decoding approach for multidimensional correlated source signals. A Markov random field (MRF) source model is used which exemplarily considers the residual spatial correlations in an image signal after source encoding. Furthermore, the MRF parameters are selected via an analysis based on extrinsic information transfer charts. Due to the link between MRFs and the Gibbs distribution, the resulting soft-input soft-output (SISO) source decoder can be implemented with very low complexity. We prove that the inclusion of a high-rate block code after the quantization stage allows the MRF-based decoder to yield the maximum average extrinsic information. When channel codes are used for additional error protection the MRF-based SISO source decoder can be used as the outer constituent decoder in an iterative source-channel decoding scheme. Considering an example of a simple image transmission system we show that iterative decoding can be successfully employed for recovering the image data, especially when the channel is heavily corrupted.     

Reduced-Complexity Turbo Equalization for Turbo Coded MIMO/OFDM Systems

1IntroductionTowards wireless systems Beyondthe3G(B3G),it isa great challenge for the physical layer to support high-speed transmissioninthe mobile environment to providecomfortable Internet access.Multiple Input MultipleOutput(MI MO)technique is effectiv…     

Iterative reduced-search decoding for coded partial-response channels

The full-complexity soft-input/soft-output (SISO) detector based on the BCJR algorithm for coded partial-response channels has a computational complexity growing exponentially with channel memory length. In this letter, we propose a low complexity soft-output channel detector based on the Chase decoding algorithm, which was previously applied to decode turbo product codes. At each iteration, the proposed detector forms a candidate list using all possible combinations of bit patterns in the weakest indices based on tentative hard estimates and a priori information fed back from the outer decoder. To demonstrate the performance/complexity tradeoff of the proposed detector, simulation results over rate-8/9 turbo-coded EPR4 and ME/sup 2/PR4 channels are presented, respectively. It is shown that the proposed detector can significantly reduce the computational complexity with only a small performance loss compared to the BCJR algorithm.     

New SISO decoding algorithms

A new maximum a posteriori (MAP)-equivalent soft-input soft-output (SISO) algorithm is derived together with its simplified versions. The proposed SISO algorithms provide a good compromise between complexity and performance. Our simplest SISO algorithm has lower complexity than the log-MAP, the max-log-MAP, and the soft-output Viterbi (1998) algorithm SISO algorithms, and it is an equivalent max-log-MAP algorithm. When this algorithm is used, turbo codes with block length as short as 150 bits will outperform convolutional codes when compared on the basis of equal decoder complexity.     

High-performance VLSI architectures for turbo decoders with QPP interleaver

This paper analyses different VLSI architectures for 3GPP LTE/LTE-advanced turbo decoders for trade-offs in terms of throughput and area requirement. Data flow graphs for standard SISO MAP (maximum a posteriori) turbo decoder, SW – SISO MAP turbo decoder, PW SISO MAP turbo decoder have been presented, thus analysing their performance. Two variants of quadratic permutation polynomial (QPP) interleaver have been proposed which tend to simplify the complexity of ‘mod’ operator implementation and provide best compromise between area, delay and power dissipation. Implementation of decoder using one variant of QPP interleaver has also been discussed. A novel approach for area optimisation has been proposed to reduce required number of interleavers for parallel window turbo decoder. Multi-port memory has also been used for parallel turbo decoder. To increase the throughput without any effective increase in area complexity, circuit-level pipelining and retiming have been used. Proposed architectures have been synthesised using Synopsys Design Compiler using 45-nm CMOS technology.     

Turbo乘积码在衰落信道中的应用

基于Turbo乘积码的编译码原理,利用Matlab仿真工具,对以(64,57,4)扩展汉明码为子码的Turbo乘积码进行迭代次数、量化比特数等不同参数的性能仿真,根据仿真结果选取最佳的设计参数,同时通过仿真给出了Turbo乘积码在衰落信道中的应用效果。结合Matlab仿真,在Quartus环境中完成编译码算法的硬件设计与调试,并将其应用到无线通信调制解调器中。测试结果表明,Turbo乘积码显著改善了调制解调器在衰落信道中的误码性能。     

Energy Efficient VLSI Architecture for Linear Turbo Equalizer

In this paper, energy efficient VLSI architectures for linear turbo equalization are studied. Linear turbo equalizers exhibit dramatic bit error rate (BER) improvement over conventional equalizers by enabling a form of joint equalization and decoding in which soft information is iteratively exchanged between the equalizer and decoder. However, turbo equalizers can be computationally complex and hence require significant power consumption. In this paper, we present an energy-efficient VLSI architecture for such linear turbo equalizers. Key architectural techniques include elimination of redundant operations and early termination. Early termination enables powering down parts of the soft-input soft-output (SISO) equalizer and decoder thereby saving power. Simulation results show that energy savings in the range 30–60% and 10–60% are achieved in equalization and decoding, respectively. Furthermore, we present finite precision requirements of the linear turbo equalizer and an efficient rescaling method to prevent overflow.     

Turbo multiuser detection for differentially modulated CDMA

In this letter, we study differentially modulated, iteratively decoded CDMA. The iterative multiuser receiver proposed consists of an additional soft-input soft-output (SISO) differential decoder, when compared to turbo multiuser detectors for absolutely modulated systems. Algorithms for iterative decoding with and without phase information at the receiver are developed. The resulting turbo receivers with differential modulation outperform coherent receivers with absolute modulation at moderate to high signal to noise ratios due to the interleaver gain associated with recursive inner encoders in serially concatenated encoding structures.     

Doubly Iterative Equalization of Continuous-Phase Modulation

In this paper, a doubly iterative receiver is proposed for joint turbo equalization, demodulation, and decoding of coded binary continuous-phase modulation (CPM) in multipath fading channels. The proposed receiver consists of three soft-input soft-output (SISO) blocks: a front-end soft-information-aided minimum mean square error (MMSE) equalizer followed by a CPM demodulator and a back-end channel decoder. The MMSE equalizer, combined with an a priori soft-interference canceler (SIC) and an a posteriori probability mapper, forms a SISO processor suitable for iterative processing that considers discrete-time CPM symbols which belong to a finite alphabet. The SISO CPM demodulator and the SISO channel decoder are both implemented by the a posteriori probability algorithm. The proposed doubly iterative receiver has a central demodulator coupled with both the front-end equalizer and the back-end channel decoder. A few back-end demodulation/decoding iterations are performed for each equalization iteration so as to improve the a priori information for the equalizer. As presented in the extrinsic information transfer (EXIT) chart analysis and simulation results for different multipath fading channels, this provides not only faster convergence to low bit error rates, but also lower computational complexity.     

Design and decoding of optimal high-rate convolutional codes

This correspondence deals with the design and decoding of high-rate convolutional codes. After proving that every (n,n-1) convolutional code can be reduced to a structure that concatenates a block encoder associated to the parallel edges with a convolutional encoder defining the trellis section, the results of an exhaustive search for the optimal (n,n-1) convolutional codes is presented through various tables of best high-rate codes. The search is also extended to find the "best" recursive systematic convolutional encoders to be used as component encoders of parallel concatenated "turbo" codes. A decoding algorithm working on the dual code is introduced (in both multiplicative and additive form), by showing that changing in a proper way the representation of the soft information passed between constituent decoders in the iterative decoding process, the soft-input soft-output (SISO) modules of the decoder based on the dual code become equal to those used for the original code. A new technique to terminate the code trellis that significantly reduces the rate loss induced by the addition of terminating bits is described. Finally, an inverse puncturing technique applied to the highest rate "mother" code to yield a sequence of almost optimal codes with decreasing rates is proposed. Simulation results applied to the case of parallel concatenated codes show the significant advantages of the newly found codes in terms of performance and decoding complexity.     

多维Turbo码研究

介绍了多维Turbo的编码原理,并提出了一种基于MAP算法的多维Turbo码译码器结构。研究了多维Turbo码的性能及优点,并通过仿真与二维的Turbo码进行了比较。分析表明,多维Turbo码可以获得更好的性能。     

Fast Chase algorithm with an application in turbo decoding

Turbo product codes (TPCs) provide an attractive alternative to recursive systematic convolutional (RSC)-based turbo systems. Rather than employ trellis-based decoders, an algebraic decoder may be repeatedly employed in a low-complexity, soft-input/soft-output errors-and-erasures decoder such as the Chase algorithm. Taking motivation from efficient forced erasure decoders, this implementation re-orders the Chase algorithm's repeated decodings such that the inherent computational redundancy is greatly reduced without degrading performance. The result is a highly efficient fast Chase implementation. The algorithm presented here is principally applicable to single error-correcting codes although consideration is also given to the more general case. The new decoder's value in practical turbo schemes is demonstrated via application to decoding of the (64,57,4) extended Hamming TPC