深亚微米p+栅pMOSFET中NBTI效应及氮在其中的作用

研究了p+栅pMOSFET中的NBTI效应.通过实验分析了NBTI应力后器件特性及典型参数的退化,研究了氮化栅氧中氮对NBTI效应的作用,并给出了栅氧中的氮对NBTI效应影响的可能机制,即栅氧中氮形成的Si-N键不易被分解,但栅氧中的氮提供了H+的陷阱中心,导致NBTI效应中氧化层正固定电荷的增加,其总体效果表现为氮对NBTI效应退化影响的增加.     

超深亚微米PMOSFET器件的NBTI效应

研究了超深亚微米PMOS器件中的NBTI(负偏置温度不稳定性)效应,通过实验得到了NBTI效应对PMOSFET器件阈值电压漂移的影响,并得到了在NBTI效应下求解器件阈值电压漂移的经验公式.分析了影响NBTI效应的主要因素:器件栅长、硼穿通效应和栅氧氮化以及其对器件寿命退化的作用.给出了如何从工艺上抑制NBTI效应的方法     

超深亚微米PMOSFET器件的NBTI效应

研究了超深亚微米PMOS器件中的NBTI(负偏置温度不稳定性)效应,通过实验得到了NBTI效应对PMOSFET器件阈值电压漂移的影响,并得到了在NBTI效应下求解器件阈值电压漂移的经验公式.分析了影响NBTI效应的主要因素:器件栅长、硼穿通效应和栅氧氮化以及其对器件寿命退化的作用.给出了如何从工艺上抑制NBTI效应的方法.     

NBTI效应的退化表征

对超深亚微米PMOSFET器件NBTI效应的失效机理和退化表征进行了讨论.反应-扩散模型是最为广泛接受的NBTI退化机理模型,它有效地解释了阈值电压漂移随时间逐渐饱和以及应力去除后NBTI效应部分恢复的退火现象.用阈值电压漂移量表征了NBTI效应的退化,深入讨论了影响NBTI效应的主要因素:应力作用时间、栅氧电场和温度应力,总结了阈值电压漂移与这些因素的关系,给出了一个经验-逻辑推理公式,对公式中的参数提取后可以得到NBTI寿命值,从而实现NBTI效应的可靠性评价.     

超深亚微米P^＋栅PMOSFET中NBTI效应及其机理研究

本文深入研究了P^ 栅PMOSFET中的NBTI效应，首先通过实验分析了NBTI应力后器件特性及典型参数的退化，基于这些实验结果提出了一种可能的NBTI效应发生机制：即由水分子参与的Si—SiO2界面处的电化学反应．最后从工艺的角度给出了减小和抑制NBTI效应的方法．     

影响PMOSFET中NBTI效应的相关因素研究

在PMOSFET上施加负栅压和高温应力后，出现的NBTI效应是超深亚微米MOS器件中重要的可靠性问题之一。研完了NBTI效应对PMOSFET器件参数的影响及其产生机理；基于NBTI效应的产生模型，分析了Si／SiO2界面处氢、氮和水等相关因素对NBTI效应的影响；介绍了减小NBTI效应的方法。     

28 nm PMOS器件中Ge注入对NBTI可靠性的影响

研究了28 nm 多晶硅栅工艺中Ge注入对PMOS器件的负偏压温度不稳定性(NBTI)的影响。在N阱中注入Ge,制作了具有SiGe沟道的PMOS量子阱器件。针对不同栅氧厚度和不同应力条件的器件,采用动态测量方法测量了NBTI的退化情况,采用电荷泵方法测量了界面态的变化情况。实验结果表明,由于Ge的注入,PMOS器件中饱和漏电流的退化量降低了43%,同时应力过程中产生的界面态得到减少,有效提高了PMOS器件的NBTI可靠性。     

pMOS器件NBTI效应随着器件参数变化规律的一种模型

器件的负偏压温度不稳定性(Negative bias temperature instability,NBTI)退化依赖于栅氧化层中电场的大小和强反型时沟道空穴浓度,沟道掺杂浓度的不同显然会引起栅氧化层电场的变化。栅氧化层的厚度不仅影响栅氧化层电场,而且会影响沟道空穴浓度,因而,改变沟道掺杂浓度和栅氧化层厚度会引起NBTI退化的不同。首先利用pMOSFETS器件的能带图和NBTI的退化模型,推导出了器件NBTI随器件参数变化的公式,并修订了NBTI的数值模拟方法,然后分别利用理论计算和数值模拟的方法对不同器件参数、相同阈值电压的器件进行定量地计算和仿真,继而总结出一种分析器件NBTI退化的应用模型,可对集成电路和器件的可靠性设计提供指导。     

超深亚微米P+栅PMOSFET中NBTI效应及其机理研究

本文深入研究了P⁺栅PMOSFET中的NBTI效应,首先通过实验分析了NBTI应力后器件特性及典型参数的退化,基于这些实验结果提出了一种可能的NBTI效应发生机制:即由水分子参与的Si-SiO₂界面处的电化学反应.最后从工艺的角度给出了减小和抑制NBTI效应的方法.     

pMOS器件NBTI界面电荷引起耦合的数值模拟分析

从二维模拟pMOS器件得到沟道空穴浓度和栅氧化层电场,用于计算负栅压偏置温度不稳定性NBTI(Negative bias temperature instability)效应的界面电荷的产生,是分析研究NBTI可靠性问题的一种有效方法。首先对器件栅氧化层/硅界面的耦合作用进行模拟,通过大量的计算和已有的实验比对分析得出:当NBTI效应界面电荷产生时,栅氧化层电场是增加了,但并没有使界面电荷继续增多,是沟道空穴浓度的降低决定了界面电荷有所减少(界面耦合作用);当界面电荷的产生超过1012/cm2时,界面的这种耦合作用非常明显,可以被实验测出;界面耦合作用使NBTI退化减小,是一种新的退化饱和机制,类似于"硬饱和",但是不会出现强烈的时间幂指数变化。     

PMOSFET的NBTI效应

随着工艺的发展,器件尺寸的不断缩小,PMOSFET受负温度不稳定性(NBTI)效应影响而失效的现象愈来愈严重,NBTI效应的影响成为器件可靠性的一个焦点问题.本文综述了NBTI效应的产生机理、影响因素、减缓方法及其相关的一些前沿问题.     

Effects of Measurement Temperature on NBTI

Negative bias temperature instability (NBTI) is a pressing reliability issue for the CMOS industry. NBTI has been measured at stress temperature in most of the recent works. For the first time, this letter will demonstrate that, for a given number of defects, the threshold-voltage shift measured at stress temperature can be less than half of its value at room temperature. As a result, the data obtained at different measurement temperatures should not be used for extracting the thermal enhancement of defect creation. In the future, this newly identified dependence on measurement temperature should be taken into account when estimating the NBTI limited lifetime of pMOSFETs     

An On-Chip Sensor to Monitor NBTI Effects in SRAMs

The increasing need to store more and more information has resulted in the fact that Static Random Access Memories (SRAMs) occupy the greatest part of Systems-on-Chip (SoCs). Therefore, SRAM’s robustness is considered crucial in order to guarantee the reliability of such SoCs over lifetime. In this context, one of the most important phenomena that degrades Nano-Scale SRAMs reliability is related to Negative-Bias Temperature Instability (NBTI), which causes the memory cells aging. The main goal of this paper is to present a hardware-based approach able to monitor SRAMs’ aging during the SoC’s lifetime based on the insertion of On-Chip Aging Sensors (OCASs). In more detail, the proposed strategy is based on the connection of one OCAS to every SRAM column, each periodically monitoring write operations on the SRAM cells. It is important to note that in order to prevent the OCAS from aging and to reduce leakage power dissipation, the OCAS circuitry is powered-off during its idle periods. The proposed hardware-based approach has been evaluated throughout SPICE simulations using 65 nm CMOS technology and the results demonstrate the sensor’s capacity to detect early aging states and therefore, guaranteeing high SRAM reliability. To conclude, a complete analysis of the sensor’s overheads is presented.     

Experimental Evaluation of Circuit-Based Modeling of the NBTI Effects in Double-Gate FinFETs

In this work, an example of practical implementation of the auxiliary sub-circuit (ASC) for modeling of the NBTI effects in DG FinFETs is described. A good agreement between the simulated and measured electrical characteristics of p-type DG FinFETs fabricated in SOI technology has been obtained using the industry-standard BSIM-CMG model with ASC. The oxide and interface trap densities are extracted in Spice simulations by tuning the ASC trapped charge parameters to fit the NBTI experimental data. The increase of oxide and interface trapped charge in p-type DG FinFET device is found to follow the logarithmic dependence with NBTI stress time.     

Ultrafast Measurement on NBTI

We combine customary pulsed $I$– $V$ setup with a simple linear drain–current correction method to provide a possible standard for NBTI characterization. The method is implemented using standard equipment and yet is able to achieve sub-100-ns delay, the shortest reported to date for a wafer-level setup. Unlike the ramped-voltage method for which synchronization of the gate and drain waveforms is critical, relative delay between the gate and drain signals is not a concern in our case since measurement is made during quasi-steady state. For the present setup, gate and drain signals are shown to “stabilize” after $sim!hbox{50}$ ns (upon switching) for a gate capacitive load of 1.5 pF (equivalent to $sim!hbox{80} $ devices used in this letter), rendering parallel testing possible using a single gate voltage source. Extension of the method for direct threshold voltage extraction by the constant subthreshold drain current approach is also discussed.      

深亚微米pMOS器件的HCI和NBTI耦合效应与物理机制

研究了深亚微米pMOS器件的热载流子注入(hot-carrier injection,HCI)和负偏压温度不稳定效应(negative bias temperature instability,NBTI)的耦合效应和物理机制. 器件在室温下的损伤特性由HCI效应来控制. 高温条件下，器件受到HCI和NBTI效应的共同作用，二者的混合效应表现为NBTI不断增强的HCI效应. 在HCI条件下器件的阈值电压漂移依赖沟道长度，而NBTI效应中器件的阈值电压漂移与沟道长度无关，给出了分解HCI和NBTI耦合效应的方法.