A 0.5 V 4.85 Mbps Dual-Mode Baseband Transceiver With Extended Frequency Calibration for Biotelemetry Applications

This work provides a dual-mode baseband transceiver chipset for wireless body area network (WBAN) system. The modulation schemes include multi-tone code division multiple access (MT-CDMA) and orthogonal frequency division multiplexing (OFDM) to meet multi-user coexistence (up to 8) and high data rate purposes. Based on the analysis of the WBAN operation behavior, several methods including higher data rate, optimal storage determination, and low power implementation techniques are proposed to reduce the transmission energy. To achieve tiny area integration, an embedded phase frequency tunable clock generator and frequency error pre-calibration scheme are provided to extend the frequency mismatch tolerance to 100 ppm (2.5x of state-of-the-art systems). This chipset is manufactured in 90 nm standard CMOS process. Working at supply voltage of 0.5 V, this chipset is able to provide maximum date rate of 4.85 Mbps with modulator power consumption of 5.52 $mu$W.      

An Ultra-Low-Power and Portable Digitally Controlled Oscillator for SoC Applications

In this paper, a novel ultra-low-power digitally controlled oscillator (DCO) with cell-based design for system-on-chip (SoC) applications is presented. Based on the proposed segmental delay line (SDL) and hysteresis delay cell (HDC), the power consumption can be saved by 70% and 86.2% in coarse-tuning and fine-tuning stages, respectively, as compared with conventional approaches. Besides, the proposed DCO employs a cascade-stage structure to achieve high resolution and wide range at the same time. Measurement results show that power consumption of the proposed DCO can be improved to 140 muW (@200 MHz) with 1.47-ps resolution. In addition, the proposed DCO can be implemented with standard cells, making it easily portable to different processes and very suitable for SoC applications.     

An LTCC-Based Wireless Transceiver for Radio-Over-Fiber Applications

This paper describes the realization of a low-temperature co-fired ceramic (LTCC)-based wireless transceiver with optical interface for radio-over-fiber applications involving several standards. The RF front-end including an antenna is fabricated in LTCC technology, while the optical transceiver with a single-mode optical interface is built on a silicon motherboard. The front-end operates in the 5-6-GHz band, while the modulated optical carrier is transmitted at 1.55-mum wavelength. The front-end module is an attractive solution for wireless local area network applications such as IEEE 802.11a or HIPERLAN2 requiring a direct link to an optical backbone     

无线收发数传MODEM模块PTR2030及其应用

本文介绍了PTR2030的主要特点、引脚功能、软件设计、硬件连接及具体的应用电路.PTR2030是超小型、超低功耗、高速率无线数传MODEM,它性能优异,是目前低功率无线数传的理想选择.     

A Transceiver Front-End for Ultra-Wide-Band Applications

An integrated pulse based ultra-wide-band (UWB) transceiver front-end is presented in this paper. The pulse generator produces Gaussian modulated pulses satisfying Federal Communication Commission spectral mask with possibility for binary-phase shift keying modulation. The generated pulses have a bandwidth of 2 GHz from 3.1 to 5.1 GHz. The receiver front-end consists of an UWB low-noise amplifier (LNA). The transmit and receive paths are chosen by a transmit/receive (T/R) switch. The pulse generator, T/R switch and the LNA are integrated on a single chip and fabricated using 0.25-mum SiGe:C BiCMOS technology. The integrated circuit components are designed fully differential. The off-chip antenna and bandpass filter are single ended and connected to the T/R switch through a hybrid coupler     

A 2.4GHz CMOS Monolithic Transceiver Front-End for IEEE 802.11b Wireless LAN Applications

A 2.4GHz CMOS monolithic transceiver front-end for IEEE 802.11b wireless LAN applications is presented.The receiver and transmitter are both of superheterodyne structure for good system performance.The front-end consists of five blocks:low noise amplifier,down-converter,up-converter, pre-amplifier,and LO buffer.Their input/output impedance are all on-chip matched to 50Ω except the down-converter which has open-drain outputs.The transceiver RF front-end has been implemented in a 0.18μm CMOS process.When the LNA and the down-converter are directly connected,the measured noise figure is 5.2dB,the measured available power gain 12.5dB,the input 1dB compression point -18dBm,and the third-order input intercept point -7dBm.The receiver front-end draws 13.6mA currents from the 1.8V power supply.When the up-converter and pre-amplifier are directly connected,the measured noise figure is 12.4dB,the power gain is 23.8dB,the output 1dB compression point is 15dBm,and the third-order output intercept point is 16dBm.The transmitter consumes 276mA current from the 1.8V power supply.     

CC1000 射频收发器在无线游戏控制器中的应用

无线游戏控制器正迅速被市场接受.射频(RF)技术对这一应用非常理想.     

Subthreshold Source-Coupled Logic Circuits for Ultra-Low-Power Applications

This paper presents a novel approach for implementing ultra-low-power digital components and systems using source-coupled logic (SCL) circuit topology, operating in weak inversion (subthreshold) regime. Minimum size pMOS transistors with shorted drain-substrate contacts are used as gate-controlled, very high resistivity load devices. Based on the proposed approach, the power consumption and the operation frequency of logic circuits can be scaled down linearly by changing the tail bias current of SCL gates over a very wide range spanning several orders of magnitude, which is not achievable in subthreshold CMOS circuits. Measurements in conventional 0.18 m CMOS technology show that the tail bias current of each gate can be set as low as 10 pA, with a supply voltage of 300 mV, resulting in a power-delay product of less than 1 fJ. Fundamental circuits such as ring oscillators and frequency dividers, as well as more complex digital blocks such as parallel multipliers designed by using the STSCL topology have been experimentally characterized.     

An Ultra-Low-Power Injection Locked Transmitter for Wireless Sensor Networks

This paper presents the principles for designing low-power transmitters for wireless sensor networks. Based on these principles, an injection-locked transmitter is implemented in a standard 0.13-$muhbox m$CMOS process and packaged using chip-on-board assembly. The transmitter utilizes a film bulk acoustic resonator (FBAR) to obtain a stable carrier at 1.9 GHz. At 0 dBm output power, the transmitter achieves an efficiency of 32% at 50 kb/s and 28% at 156 kb/s. With 50% on-off keying, the transmitter consumes 1.6 and 1.8 mW, respectively.     

零中频无线接收机:理想、现实与演化

本文通过与超外差式无线接收机的对比,介绍了零中频接收机的设计思想、工作原理以及所面临的技术困难,进一步讨论了近年来为解决这些困难而提出的一些新的电路技术与系统结构。     

A Subthreshold Low-Noise Amplifier Optimized for Ultra-Low-Power Applications in the ISM Band

The IEEE 802.15.4 standard relaxes the requirements on the receiver front-end making subthreshold operation a viable solution. The specification is discussed and guidelines are presented for a small area ultra-low-power design. A subthreshold biased low-noise amplifier (LNA) has been designed and fabricated for the 2.4-GHz IEEE 802.15.4 standard using a standard low-cost 0.18-mum RF CMOS process. The single-stage LNA saves on chip area by using only one inductor. The measured gain is more than 20 dB with an S₁₁ of -19 dB while using 630 muA of dc current. The measured noise figure is 5.2 dB.     

一种面向无线音频应用的片上系统平台

提出并实现了一种面向无线音频的高性能、低功耗Calliope SoC架构平台.该平台通过多媒体DSP指令扩展的CK510E处理器、前向纠错编解码ASIC IP和双协议(I2S和S/PDIF)数字音频接口IP,兼容多种音频编解码标准和数字音频传输标准,并可有效提高无线传输信道的容错性.基于Calliope SoC架构平台,给出了音频编解码算法的优化实现方法.实验证明:使用RS(32,24)的FEC使无线数字音频传输系统的丢包率在移动情况下由7.21%降到4.87%,有效提高了系统的准确稳定性.Calliope SoC平台可分别在40 MHz、80 MHz和70 MHz系统工作频率下实现SBC、MP2和FLAC三种不同音频实时编/解码运算.     

A Single-Chip CMOS Transceiver Front-End for DCS-1800 Wireless Communications

This work describes the design and realization of a low voltage single-chip wireless transceiver front-end in a standard 0.25 m CMOS technology. The presented prototype integrates the LNA, down-converters, VCO, quadrature generator, up-converter and pre-amplifier on a single die. A high level of integration is achieved by using a low-IF topology for reception, a direct quadrature up-conversion topology for transmission and an oscillator with on-chip integrated inductor. The final objective of this design is to develop a complete transceiver system for wireless communications at 1.8 GHz that can be built with a minimum of surrounding components: only an antenna, a duplexer, a power amplifier and a baseband signal processing chip. The presented circuit consumes 240 mW from a 2.5 V supply and occupies a die area of 8.6 mm².     

A CMOS IR-UWB Transceiver Design for Contact-Less Chip Testing Applications

This paper presents a novel CMOS impulse radio (IR) ultra-wide-band (UWB) transceiver system design for future contact-less chip testing applications using inductive magnetic coupling as wireless interconnect. The proposed architecture is composed of a simple and robust design of a Gaussian monocycle impulse generator at the transmitter, a wideband short-range on-chip transformer for data transmission, and a g_m-boosted common-gate low-noise amplifier in the UWB receiver path. SpectreRF post-layout simulation with a 90-nm CMOS technology shows that the transceiver operates up to a 5 Gb/s data rate, and consumes a total of 9 mW under a 1-V power supply.     

A 2 MHz Wireless CMOS Transceiver for Implantable Biosignal Sensing Systems

An implementation of an implantable sensing biosystem composes of a readout circuit, a power management block, an embedded microcontroller unit (MCU), an implantable drug delivery section and a wireless uplink transceiver system. This paper describes a bi-directional wireless transceiver system for implantable sensing systems. The transceiver system is composed of an external and implantable transceiver, communicating through an inductive link. Half duplex communication between transceivers at a 10 Kbps data rate was achieved at a maximum distance of 4 cm. Command and data will be supplied to the implantable module by radio frequency (RF) telemetry utilizing an amplitude shift keying (ASK) modulated 2 MHz carrier frequency. A capacitor-less amplitude demodulation receiver architecture was produced in the research with implantable receiver core area measuring at 113.2 μm by 171.8 μm with average power dissipation at 815.1 μW at a 3.3 V single rail power supply. An active uplink transceiver utilizing load shift keying (LSK) as backward data telemetry was designed. Implantable transmitter core area measures 251.7 μm by 139.3 μm, consuming 103.62 mW while driving an RF ferrite core antenna at maximum reading range. Integrating both circuits, implantable transceiver, measuring 355.3 μm by 171.8 μm, was designed and implemented using TSMC 0.35 μm mixed-signal 2P4M 3.3 V standard CMOS process. The integrated circuit solution addressed solutions for many of the problems associated with implanted devices and introduces circuits which improve in several ways over previously published designs, in functionality and integration level. In addition to being fully integrated in plain CMOS technology, not relying at least partly on available specialized elements and expensive technologies, these building blocks improve on previous designs in performance and/or power consumption. This work succeeded in implementing building blocks for an implantable transceiver, which depends only on the absolute minimum off-chip components. A complete implantable chip is presented, which highlight the design tradeoffs and optimizations applied to the design of CMOS implantable system chips.     

无线IC收发机体系结构(上)

在目前的小型化趋势中,降低通信芯片的成本迫在眉睫.这促使设计者要以更高的集成度来改进收发机.在天线和数据输出之间获得最大集成的目标不象用片上元件代替外部元件那样简单,它需要彻底改变前端设计.当前对功率、尺寸和成本的要求都很苛刻,传统的多元件无线设计已不能适应,因此,这就需要新的具有更少片外元件的无线体系结构.     

无线IC收发机体系结构(下)

亚-采样接收机　　随着高速CMOS工艺的出现,已有人开始探讨基于带通采样定理应用的亚采样系统.图9示出了中频的亚采样体系结构.采样电路代替了零-中频体系结构中的混频器.图10示出了频域中的下变频处理.射频信号以基带信号的奈奎斯特速率进行采样.下面的等式给出带通采样产生的频谱镜象:　　……     

应用于无线传感网络SoC的逐次逼近A/D转换器

设计了应用于无线传感网络SoC解决方案的10位150 kS/s 逐次逼近A/D转换器.通过失调消除技术、合理的时序控制和版图设计,实现了电路的高精度和低功耗.设计的A/D转换器积分非线性和微分非线性分别为0.54 LSB和0.8 LSB;在150 kS/s采样率、14.3 kHz输入信号频率时,信噪比为60.8 dB,无杂散动态范围83.1 dB.设计实现基于TSMC 0.18 μm混合信号CMOS工艺,IP核面积为0.083 mm2,1.8 V工作电压下功耗为0.56 mW.     

An Energy-Efficient OOK Transceiver for Wireless Sensor Networks

A 1-Mb/s 916.5-MHz on-off keying (OOK) transceiver for short-range wireless sensor networks has been designed in a 0.18-mum CMOS process. The receiver has an envelope detection based architecture with a highly scalable RF front-end. Untuned RF circuits are leveraged and optimized in the receiver to achieve superior energy efficiency compared to tuned RF circuits. The receiver power consumption scales from 0.5 mW to 2.6 mW, with an associated sensitivity of -37 dBm to -65 dBm at a BER of 10 ^-3. The transmitter consumes 3.8 mW to 9.1 mW with output power from -11.4 dBm to -2.2 dBm. The receiver achieves a startup time of 2.5 mus, allowing for efficient duty cycling     

基于nRF401的通用智能无线收发装置

介绍了一种通过单片机W77E58对无线收发芯片nRF401进行智能控制的通用无线收发装置的设计方法,包括硬件电路和软件部分的实现方法,并给出了主要的C51源代码。最后,进行了硬件电路的测试。开发的无线收发装置可以方便地嵌入各种带有串口的测量和控制系统中,实现无线数据的双向传输。