Removal of stacking faults in Ge grown on Si through nanoscale openings in chemical SiO2

Nucleation and eventual coalescence of Ge islands, grown out of 5 to 7 nm diameter openings in chemical SiO₂ template and epitaxially registered to the underlying Si substrate, have been shown to generate a low density of threading dislocations (?10⁶ cm^− 2). This result compares favorably to a threading dislocation density exceeding 10⁸ cm^− 2 in Ge films grown directly on Si. However, the coalesced Ge film contains a relatively high density of stacking faults (5 × 10⁷ cm^− 2), and subsequent growth of GaAs leads to an adverse root-mean-square roughness of 36 nm and a reduced photoluminescence intensity at 20% compared to GaAs grown on Ge or GaAs substrates. Herein, we find that annealing the Ge islands at 1073 K for 30 min before their coalescence into a contiguous film completely removes the stacking faults. However, the anneal step undesirably desorbs any SiO₂ not covered by existing Ge islands. Further Ge growth results in a threading dislocation density of 5 × 10⁷ cm^− 2, but without any stacking faults. Threading dislocations are believed to result from the later Ge growth on the newly exposed Si where the SiO₂ has desorbed from areas uncovered by Ge islands. The morphology and photoluminescence intensity of GaAs grown on the annealed Ge is comparable to films grown on GaAs or Ge substrates. Despite this improvement, the GaAs films grown on the annealed Ge/Si exhibit a threading dislocation density of 2 × 10⁷ cm^− 2 and a minority carrier lifetime of 67 ps compared to 4 to 5 ns for GaAs on Ge or GaAs substrates. A second oxidation step after the high temperature anneal of the Ge islands is proposed to reconstitute the SiO₂ template and subsequently improve the quality of Ge film.     

Epitaxial growth of relaxed germanium layers by reduced pressure chemical vapour deposition on (110) and (111) silicon substrates

The growth of Ge on (110) and (111) oriented Si substrates is of great interest to enhance the mobility of both holes and electrons in complementary metal oxide semiconductor transistors. However, the quality of thick, relaxed Ge layers grown epitaxially on these surfaces is usually much lower than similar layers grown on (100) Si, resulting in both higher defect densities (i.e. threading dislocations and stacking faults) and rougher surfaces. In this work we have investigated the growth of Ge layers on (110) and (111) Si substrates by reduced-pressure chemical vapour deposition using a two temperature process. We have found that the combination of suppressing the Ge seed layer roughness and high temperature post-growth annealing can reduce the rms surface roughness of (110) Ge layers to below 2 nm and the threading dislocation density to below 1 × 10⁷ cm^− 2. Thick (111) Ge layers were found to exhibit a very high density of stacking faults, that could not be reduced by post-growth annealing and a higher rms surface roughness of around 12 nm, which was limited by the Ge seed layer.     

Growth of 3C-SiC on Si(111) using the four-step non-cooling process

A modified four-step method was applied to grow a 3C-SiC thin film of high quality on the off-axis 1.5° Si(111) substrate in a mixed gas of C₃H₈, SiH₄ and H₂ using low pressure chemical vapor deposition. The modified four-step method adds a diffusion step after the carburization step and removes the cooling from the traditional three-step method (clean, carburization, and growth). The X-ray intensity of the 3C-SiC(111) peak is enhanced from 5 × 10⁴ counts/s (the modified three steps) to 1.1 × 10⁵ counts/s (the modified four steps). The better crystal quality of 3C-SiC is confirmed by the X-ray rocking curves of 3C-SiC(111). 3C-SiC is epitaxially grown on Si(111) supported by the selected area electron diffraction patterns taken at the 3C-SiC/Si(111) interface. Some {111} stacking faults and twins appear inside the 3C-SiC, which may result from the stress induced in the 3C-SiC thin film due to lattice mismatch. The diffusion step plays roles in enhancing the formation of Si-C bonds and in reducing the void density at the 3C-SiC/Si(111) interface.     

Epitaxy of In0.01Ga0.99As on Ge/offcut Si (001) virtual substrate

In_0.01Ga_0.99As thin films free of anti-phase domains were grown on 7° offcut Si (001) substrates using Ge as buffer layers. The Ge layers were grown by ultrahigh vacuum chemical vapor deposition using ‘low/high temperature’ two-step strategy, while the In_0.01Ga_0.99As layers were grown by metal-organic chemical vapor deposition. The etch-pit counting, cross-section and plane-view transmission electron microscopy, room temperature photoluminescence measurements are performed to study the dependence of In_0.01Ga_0.99As quality on the thickness of Ge buffer. The threading dislocation density of Ge layer was found to be inversely proportional to the square root of its thickness. The threading dislocation density of In_0.01Ga_0.99As on 300 nm thick Ge/offcut Si was about 4 × 10⁸ cm^− 2. Higher quality In_0.01Ga_0.99As can be obtained on thicker Ge/offcut Si virtual substrate. We found that the threading dislocations acted as non-radiative recombination centers and deteriorated the luminescence of In_0.01Ga_0.99As remarkably. Secondary ion mass spectrometry measurement indicated as low as 10¹⁶ cm^− 3 Ge unintended doping in In_0.01Ga_0.99As.     

Chemical bath deposition of PbS nanocrystals: Effect of substrate

Nanocrystalline PbS layers have been deposited chemically on Si, Ge and GaAs substrates from alkaline solutions containing 0.05 mol l^− 1 of Pb(NO₃)₂, 0.04 mol l^− 1 of thiourea, 0.05 mol l^− 1 of triethanolamine, and 0.15 mol l^− 1 of NaOH. Rutherford backscattering spectroscopy, transmission electron and atomic force microscopy reveal that the chemical nature of the substrate has a profound influence on the structure and thickness of the deposited layers. It is found that a large lattice mismatch between the substrate and PbS results in formation of coarse-grained layers with a small effective thickness (e.g. PbS on Si). On the other hand, close matching of lattice constants leads to deposition of thicker layers with smaller grain size (e.g. PbS on Ge, GaAs).     

Honeycomb voids due to ion implantation in germanium

For future semiconductor devices, germanium layers are very attractive due to their high carrier mobility with ion implantation remaining the dominant method for forming pn junctions. Yet, implantation of heavy ions above a critical dose causes inadmissible surface roughness and formation of voids. To understand the main factors of influence, a comprehensive study on void formation was performed with different ions (BF₂, P, Al, Ga, Ge, As, Sb) implanted at various doses, dose rates, and energies. It was found that the dose is the most important parameter for void formation. The critical dose was determined to be 2 · 10¹⁵ cm^− 2 for As, 2 · 10¹⁵ cm^− 2 for Ga, and 5 · 10¹⁴ cm^− 2 for Sb, respectively. For ions with lower mass (BF₂, P, Al), no or only negligible surface roughening was observed.     

A benchmarking of silane, disilane and dichlorosilane for the low temperature growth of group IV layers

In a 300 mm industrial Reduced Pressure-Chemical Vapour Deposition tool we have assessed the advantages and drawbacks of disilane for the low temperature growth of Si and SiGe. Four distinct regions can be noticed on the Arrhenius plot of the Si growth rate at 2660 Pa (i.e. 20 Torr) from Si₂H₆ as a function of the reverse growth temperature. For T > 850 °C, we are in the high temperature, Si precursor supply-limited regime (as with SiH₄). For T ≤ 850 °C, the situation is more complicated, with the presence of a growth rate “plateau” between 575 °C and 675 °C (not present for SiH₄ or SiH₂Cl₂), surrounded by domains where the Si growth rate increases with the temperature at different rates (E_a = 1.39 eV (T > 675 °C) ⇔ E_a = 2.30 eV (T < 575 °C)). This translates into Si growth rates which, for T < 575 °C, are approximately ten times higher with Si₂H₆ than with SiH₄, which are in turn roughly ten times higher than with SiH₂Cl₂. For given GeH₄ and Si precursor mass-flow ratios, lower Ge contents and much higher SiGe growth rates are obtained at 550 °C, 2660 Pa with Si₂H₆ than with SiH₄ and especially SiH₂Cl₂. SiGe and Si layers grown with disilane are generally of high crystalline quality, however moderate Si₂H₆ mass-flows should be used in the growth rate plateau, in order to avoid the formation of defective Si.     

Insights for void formation in ion-implanted Ge

The formation of voids in ion-implanted Ge was studied as a function of ion implantation energy and dose. (001) Ge substrates were self-implanted at energies of 20-300 keV to doses of 1.0 × 10¹³-1.0 × 10¹⁷ cm^− 2. Transmission electron microscopy revealed clusters of voids just below the surface for implant energies ≤ 120 keV at a dose of 2.0 × 10¹⁵ cm^− 2 and complete surface coverage for an implant energy of 130 keV and doses ≥ 1.0 × 10¹⁶ cm^− 2. Void clusters did not change in size or density after isothermal annealing at 330 °C for 176 min. The initial void formation is discussed in terms of the vacancy clustering and “microexplosion” theories with a damage map detailing the implant conditions necessary to produce voids.     

Silicon-rich oxynitride hosts for 1.5 μm Er emission fabricated by reactive and standard RF magnetron sputtering

This study compares the erbium emission from different Si-rich silicon oxynitrides matrices fabricated by magnetron sputtering. The Er-doped layers were grown by two different sputtering configurations: (i) standard co-sputtering of three confocal targets (Er₂O₃, Si₃N₄ and SiO₂) under Ar plasma, and (ii) reactive co-sputtering under Ar + N₂ plasma of either three (Er₂O₃, pure Si and SiO₂) or two targets (Er₂O₃ and pure Si). The last reactive configuration was found to offer the best Er³⁺ PL intensity at 1.5 μm. This highest PL intensity was found comparable to the corresponding emission from Er-doped silicon-rich silicon oxide.     

Temperature dependent biaxial texture evolution in Ge films under oblique angle vapor deposition

The morphology and texture of Ge films grown under oblique angle vapor deposition on native oxide covered Si(001) substrates at temperatures ranging from 230 °C to 400 °C were studied using scanning electron microscopy, X-ray diffraction and X-ray pole figure techniques. A transition from polycrystalline to {001}<110> biaxial texture was observed within this temperature range. The Ge films grown at substrate temperatures < 375 °C were polycrystalline. At substrate temperatures of 375 °C and 400 °C, a mixture of polycrystalline and biaxial texture was observed. The 230 °C sample consisted of isolated nanorods, while all other films were continuous. The observed biaxial texture is proposed to be a result of the loss of the interface oxide layer, resulting in epitaxial deposition of Ge on the Si and a texture following that of the Si(001) substrates used. The rate of oxide loss was found to increase under oblique angle vapor deposition.     

Sb-modified growth of stacked Ge/Si(100) quantum dots

We report on the Sb induced modifications of the morphology of self assembled Ge/Si(100) quantum dot stacks in a Si matrix grown by a molecular beam epitaxy. It is shown that the size of the quantum dots in the stack and the Si spacer layer uniformity inside the stack are regulated by the amount of deposited Sb. We consider the thin Sb layer at the Ge/Si growth interface as a factor limiting the surface migration of Si and Ge ad-atoms. The surface diffusion coefficients of Si ad-atom on uncovered pyramid shaped Ge island and on a Ge island covered by a single monolayer of Sb are estimated to be 2.4 μm²s⁻¹ and 2.3 × 10⁻⁴ μm²s⁻¹ at a temperature of 600 °C, correspondingly. Based on this remarkable reduction of surface diffusion the morphology of the surface can be preserved when the growth is continued after the single monolayer of Sb is at the surface.     

Structural properties of the formation of yttrium germanides thin films on the Si(111) surface

We have performed first principles total energy calculations to investigate the deposit of yttrium digermanide on the Si(111) surface. We have used the periodic density functional theory as implemented in the Quantum-ESPRESSO package. For the adsorption of a monolayer of yttrium digermanide on the Si(111)-(1 × 1) surface, we have found that the most stable geometry corresponds to a configuration with Y atoms occupying the T4 site above a second layer Si atom, and with a Ge bilayer on top of the structure. The atomic structure of the Ge bilayer is similar to that of Si (Ge) in the bulk but rotated 180° with respect to the crystal. For the three dimensional growth of a few layers of yttrium digermanide on Si(111) we have considered a hexagonal structure with (√3 × √3) periodicity, similar to the one found in the growth of few layers of YSi₂ on Si(111): graphite-like Ge planes (with vacancies) intercalated with yttrium planes. As in the case of a single layer of YGe₂, there is a formation of a Ge bilayer on top of the structure. In this case, the Ge_down atoms of the bilayer, which are on top the vacancies, move down towards the vacancy, while Ge atoms in the graphitic layer, which are below the Ge_up atoms of the bilayer, are displaced towards the vacancy.     

Effect of layer thickness on structural quality of Ge epilayers grown directly on Si(001)

A study of Ge epilayer growth directly on a Si(001) substrate is presented, following the two temperature Ge layer method. In an attempt to minimize the overall thickness while maintaining a good quality Ge epilayer, we have investigated the effect of varying the thickness of both the low and high temperature Ge layers, grown at 400 °C and 670 °C, respectively, by reduced pressure chemical vapor deposition. We find that the surface of the low temperature (LT) seed layer has a threading dislocation density (TDD) to the order of 10¹¹ cm^− 2. On increasing the LT layer thickness from 30 nm to 150 nm this TDD decreases by a factor of 2, while its roughness doubles and degree of relaxation increases from 82% to 96%. Growth of the high temperature (HT) layer reduces the TDD level to around 10⁸ cm^− 2, which is also shown to decrease with increasing layer thickness. Both the surface roughness and degree of relaxation reach stable values for which increasing the thickness beyond about 700 nm has no effect. Finally, annealing the HT layer is shown to reduce the TDD, without affecting the degree of relaxation. However, unless a thick structure is used the surface roughness increases significantly on annealing.     

Monolithic integration of III-V optical interconnects on Si using SiGe virtual substrates

Working optical links epitaxially grown by atmospheric MOCVD and fabricated on Si via SiGe virtual substrates are demonstrated for the first time. The SiGe virtual substrates are graded from Si substrates to 100% Ge. Because of the 0.07% lattice mismatch between GaAs and Ge, high-quality GaAs-based thin films with threading dislocation densities <3×10⁶ cm^–2 were realized. The optical link consists of a GaAs PIN-LED and a GaAs PIN detector diode. A vertical-coupling scheme was utilized to couple devices with a Al_0.15Ga_0.85As waveguide. Waveguides of varying length, Y-junctions, and bends were fabricated. The straight waveguides exhibited loss of approximately 144 dB cm^–1.An erratum to this article can be found at     

In-situ Ga doping of fully strained Ge1-xSnx heteroepitaxial layers grown on Ge(001) substrates

We have investigated the Ga and Sn content dependence of the crystallinity and electrical properties of Ga-doped Ge_1-xSn_x layers that are heteroepitaxially grown on Ge(001) substrates. The doping of Ga to levels as high as the solubility limit of Ga at the growth temperature leads to the introduction of dislocations, due to the increase in the strain of the Ge_1-xSn_x layers. We achieved the growth of a fully strained Ge_0.922Sn_0.078 layer on Ge with a Ga concentration of 5.5 × 10¹⁹ /cm³ without any dislocations and stacking faults. The resistivity of the Ga-doped Ge_1-xSn_x layer decreased as the Sn content was increased. This decrease was due to an increase in the carrier concentration, with an increase in the activation level of Ga atoms in the Ge_1-xSn_x epitaxial layers being induced by the introduction of Sn. As a result, we found that the resistivity for the Ge_0.950Sn_0.050 layer annealed at 600°C for 1 min is 3.6 times less than that of the Ga-doped Ge/Ge sample.     

Development of analytical model for strained silicon relaxation on (100) fully relaxed Si0.8Ge0.2 pseudo-substrates

Early stages of strained silicon (sSi) relaxation during the growth on (100) Si_0.8Ge_0.2 pseudo-substrates with low threading dislocation density (3 · 10^+ 4/cm²) have been studied. Threading dislocations are only observed in sSi layers at early stages of growth whereas Shockley partial dislocations appear at thicknesses of sSi above 18 nm. By analyzing the dislocation types in different sSi layers we observed three different regimes of relaxation:

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for sSi thickness below 15 nm, no dislocation generation is observed,

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for sSi thickness between 15 nm and 18 nm, threading dislocation density increases but no stacking faults are generated,

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for sSi thickness above 18 nm, threading dislocation density decreases as well as Shockley partial dislocation density increases due to the splitting of threading dislocations into partial dislocations. In this regime the stacking fault linear density has a logarithmic dependence with sSi thickness.

We developed an analytical model to describe stacking fault linear density evolution with sSi thickness and we showed that 18 nm threshold thickness for dislocation splitting corresponds to an intrinsic stacking fault energy of 90 mJ/m² in sSi.     

Radiation damage of Si1-xGex S/D p-type metal oxide semiconductor field effect transistor with different Ge concentrations

The 2-MeV electron radiation damage of Si_1-xGe_x source/drain (S/D) p-type metal oxide semiconductor field effect transistor (p-MOSFET) with different Ge concentrations is studied. After irradiation at fluences below 2 × 10¹⁷ e/cm², the drain current and the maximum hole mobility decrease with increasing electron fluence for all Ge concentrations. It suggests that lattice defects are introduced by electron irradiation. In the case of Si_1-xGe_x S/D p-MOSFET, there are two locations for lattice defects, namely, the Si channel and SiGe stressor regions (S/D). Below 2 × 10¹⁷ e/cm² irradiation, no clear correlation between the radiation degradation and Ge concentration has been observed. It suggests that this degradation is mainly due to lattice defects in the Si channel, and the effects of the compressive-strain induced by the SiGe stressors on the enhancement of the hole mobility still remains after irradiation at 2 × 10¹⁷ e/cm². In the case of 5 × 10¹⁷ e/cm² irradiation, the drain current drastically decreases after irradiation for all Ge concentrations. Moreover, after 5 × 10¹⁷ e/cm² irradiation, the maximum hole mobility of x = 0.2 is close to x = 0, and in the case of x = 0.3, the maximum hole mobility drastically decreases. This fact suggests the contributions of the lattice defects, which are in the SiGe stressors, are prominent after 5 × 10¹⁷ e/cm² irradiation and dependent on Ge concentration. In addition, it provides evidence that the compressive strain in the Si-channel is relaxed by high fluence electron irradiation.     

Metal-induced negative oxide charge detected by an alternating current surface photovoltage in thermally oxidized Fe-contaminated n-type Si (001) wafers

The atomic-bridging type negative oxide charge in SiO₂ is investigated using the Fe-contaminated (001) surface of n-type Si wafers. The investigation is done on the basis of a chemical analysis and a method in which the frequency-dependent alternating current (AC) surface photovoltage (SPV) is measured. At room temperature, an AC SPV appears and gradually increases, saturating after approximately one day (with an Fe concentration on the Si surface of 4.0 × 10¹³ atoms/cm²). The AC SPV eventually becomes inversely proportional to frequency except at very low frequencies (< 10 Hz) corresponding to weak or strong inversion, indicating that the negative Fe induced oxide charge appears in the form of a (FeOSi)⁻ network. Also, in Fe-contaminated n-type Si(001) surfaces thermally oxidized at between 550 and 650 °C for 60 min, strong inversion is unquestionably observed, proving that the (FeOSi)⁻ network survives and that most of the added Fe has segregated into the region closest to the surface of the thin SiO₂ film. At 850 °C and/or for long oxidation times, the AC SPV decreases and ultimately disappears, implying that the (FeOSi)⁻ network has collapsed and may have changed into Fe₂O₃. A model for the metal-induced negative oxide charge in the conventional oxide charge diagram is proposed.     

Manifestations of strain-relaxation in the structure of nano-sized Co-2 × 2 islands grown on Ag/Ge(111)-√3 × √3 surface

We have examined strain-relaxation of Co-2 × 2 islands grown on the Ag/Ge(111)-√3 × √3 surface by analyzing scanning tunneling microscopy images. We have found that the Co-2 × 2 islands commonly adopt a more compact arrangement as compared to that of the Ge(111) substrate, however they differ in a degree of an atomic compactness. We have not found a distinct relation between strain-relaxation and the island height. Three groups of islands have been identified upon analyzing a correspondence between strain-relaxation and the island size: (i) small islands (not bigger than 80 nm²) with a high atomic compactness, displaying fixed inter-row distances, (ii) small islands with unfixed distances between atomic rows, and (iii) big islands (bigger than 80 nm²) with fixed inter-row distances, but with a less compact atomic arrangement compared to that of the first two groups. We propose a model to account for the relation between the relaxation and the island size.     

The effects of low temperature buffer layer on the growth of pure Ge on Si(001)

We investigated the effects of low temperature (LT) Ge buffer layers on the two-step Ge growth by varying the thickness of buffer layers. Whereas the two-step Ge layers using thin (< 40 nm) Ge buffer layers were roughened due to the formation of SiGe alloy, pure and flat Ge layers were grown by using thick (> 50 nm) LT Ge buffer layers. The lowest threading dislocation density of 1.2 × 10⁶ cm⁻² was obtained when 80-nm-thick LT Ge buffer layer was used. We concluded that the minimum thickness of buffer layer was required to grow uniform two-step Ge layers on Si and its quality was subject to the thickness of buffer layer.