Thin film transistors by solution-based indium gallium zinc oxide/carbon nanotubes blend

Solution-based indium gallium zinc oxide (IGZO)/single-walled carbon nanotubes (SWNTs) blend have been used to fabricate the channel of thin film transistors (TFTs). The electrical characteristics of the fabricated devices were examined. We found a low leakage current and a higher on/off currents ratio for TFT with SWNTs compared to solution-based TFTs made without SWNTs. The saturation field effect mobility (μ_sat) of about 0.22 cm²/Vs, the current on/off ratio is ~ 10⁵, the subthreshod swing is ~ 2.58 V/decade and the threshold voltage (V_th) is less than − 2.3 V. We demonstrated that the solution-based blend active layer provides the possibility of producing higher performance TFTs for low-cost large area electronic and flexible devices.     

Improvement in the negative bias temperature stability of ZnO based thin film transistors by Hf and Sn doping

We assessed the performance of ZnO TFTs using Si₃N₄ gate dielectrics after various treatments. A remarkable improvement in the transfer characteristics was obtained for the O₂ plasma treated ZnO TFT and SiO₂ interlayer deposited ZnO TFT. Also, we developed amorphous hafnium-zinc-tin oxide (HZTO) thin film transistors (TFTs) and investigated the influence of hafnium (Hf) doping on the electrical characteristics of the hafnium-zinc oxide (HZO) thin film transistors. Doping with Hf can decrease the carrier concentration, which may result from a decrease of the field effect mobility, and reduce oxygen vacancy related defects in the interfacial layer. Adding tin (Sn) can suppress the growth of a crystalline phase in the HZTO films. The HZTO TFTs exhibited good electrical properties with a field effect mobility of 14.33 cm²/Vs, a subthreshold swing of 0.97 V/decade, and a high I_ON/OFF ratio of over 10⁹.     

Fabrication of n-type Schottky barrier thin-film transistor with channel length and width of 0.1 μm and erbium silicide source/drain

In this paper, a Schottky barrier polycrystalline silicon thin-film transistor (SB TFT) with erbium silicide source/drain is demonstrated using low temperature processes. A low temperature oxide is used for a gate dielectric and the transistor channel is crystallized by a metal-induced lateral crystallization process. An n-type SB TFT shows a normal electrical performance with subthreshold slope of 239 mV/dec, I_ON/I_OFF ratio of 5.8 × 10⁴ and I_ON of 2 μA/µm at V_G = 3 V, V_D = 2.5 V for 0.1 μm device. A process temperature is maintained at less than 600 °C throughout the whole processes. The SB TFT is expected to be a promising candidate for a next system-on-glass technology and an alternative 3D integration technology.     

Copper phthalocyanine thin-film field-effect transistor with SiO2/Ta2O5/SiO2 multilayer insulator

Top-contact Copper phthalocyanine (CuPc) thin-film field-effect transistor (TFT) with SiO₂/Ta₂O₅/SiO₂ (STS) multilayer as the dielectric was fabricated and investigated. With the multi-layer dielectric, drive voltage was remarkably reduced. A relatively large on-current of 1.1 × 10⁻⁷ A at a V_GS of −15 V was obtained due to the strong coupling capability provided by the STS multilayer gate insulator. The device shows a moderate performance: saturation mobility of μ_sat = 6.12 × 10⁻⁴ cm²/V s, on-current to off-current ratio of I_on/I_off = 1.1 × 10³, threshold voltage of V_TH = −3.2 V and sub-threshold swing SS = 1.6 V/dec. Atomic force microscope images show that the STS multilayer has a relative smooth surface. Experiment results indicate that STS multilayer is a promising insulator for the low drive voltage CuPc-based TFTs.     

Influence of process steps on the performance of microcrystalline silicon thin film transistors

Bottom gate microcrystalline silicon thin film transistors (μc-Si TFT) have been realized with two types of films: μc-Si(1) and μc-Si(2) with crystalline fraction of 80% and close to 100% respectively. On these TFTs we applied two types of passivation (SiN_x and resist). μc-Si TFTs with resist as a passivation layer present a low leakage current of about 2.10^− 12 A for V_G = − 10 and V_D = 0.1V an ON to OFF current ratio of 10⁶, a threshold voltage of 7 V, a linear mobility of 0.1 cm²/V s, and a sub-threshold voltage of 0.9 V/dec. Microcrystalline silicon TFTs with SiN_x as a passivation present a new phenomenon: a parasitic current for negative gate voltage (− 15 V) causes a bump and changes the shape of the sub-threshold region. This excess current can be explained by and oxygen contamination at the back interface.     

Analysis of carrier modulation in channel of ferroelectric-gate transistors having polar semiconductor

We have been fabricated and characterized a ferroelectric-gate thin-film transistors (TFTs) using ZnO as a channel polar semiconductor and YMnO₃ as a ferroelectric gate. A typical n-channel transistor property showing clear drain current saturation in I_D-V_D (drain current - drain voltage) characteristics was recognized. When the 3 V of the gate voltage is applied under the 4 V of drain voltage, the large drain current of about 1.1 mA is obtained. These controlled-polarization-type ferroelectric-gate TFTs using ZnO-channel TFTs operate in the accumulation-depletion mode and the ON/OFF state of the ferroelectric-gate TFTs strongly depends on the polarization switching of P_SFe. In this paper, therefore, the polarization switching of P_SFe in the TFT is carefully examined and the relationship between the polarization switching and the carrier accumulation (depletion) state is discussed using impedance spectroscopy and Capacitance-Voltage (C-V) measurements at applied the gate voltage.     

Threshold voltage shift by controlling Ga in solution processed Si-In-Zn-O thin film transistors

The threshold voltage change of solution processed gallium-silicon-indium-zinc oxide (GSIZO) thin film transistors (TFTs) annealed at 200 °C has been investigated depending on gallium ratio. GSIZO thin films were formed with various gallium ratios from 0.01 to 1 M ratio. The 30 nm-thick GSIZO film exhibited optimized electrical characteristics, such as field effect mobility (μ_FE) of 2.2 × 10^− 2 cm²/V·s, subthreshold swing (S.S) of 0.11 V/dec, and on/off current ratio (I_on/off) of above 10⁵. The variation of gallium metal cation has an effect on the threshold voltage (V_th) and the field effect mobility (μ_FE). The V_th was shifted toward positive direction from − 5.2 to − 0.4 V as increasing gallium ratio, and μ_FE was decreased from 2.2 × 10^− 2 to 5 × 10^− 3 cm²/V s. These results indicated that gallium was acted as carrier suppressor by degenerating oxygen vacancy. The electrical property of GSIZO TFTs has been analyzed as a function of the gallium ratio in SIZO system, and it clearly showed that variation of gallium contents could change on the performance of TFTs.     

Device characteristics improvement of a-In-Ga-Zn-O TFTs by low-temperature annealing

A low-temperature process to improve performances of a-In-Ga-Zn-O (a-IGZO) thin-film transistors (TFTs) fabricated at room temperature was examined. Two deposition methods, pulsed laser deposition (PLD) and RF magnetron sputtering were employed to deposit the a-IGZO channels. For the PLD case, the TFT characteristics were improved significantly by wet annealing at dew point (d.p.) of 50 °C at the annealing temperature of 200 °C. For the sputtered TFTs, a wider range of annealing temperature from 100 to 200 °C was examined. It was found that annealing at ≥ 150 °C improved the TFT characteristics when dry annealing was employed. On the other hand, wet annealing also improved μ_sat and S values, but very large negative threshold voltage (V_th) shift was observed. These results indicate that the annealing at 150 °C is enough to obtain mobility (μ_sat) as large as 8 cm² Vs^− 1, but annealing temperature as high as 200 °C provides larger μ_sat comparable to those obtained by 400 °C annealing. It is speculated that the large negative V_th shift originates from compensated donors in as-deposited sputtered films.     

The influence of fabrication process on top-gate thin-film transistors

Amorphous indium zinc oxide (a-IZO) thin-film transistors (TFTs) with bottom- and top-gate structures were fabricated at room temperature by direct current (DC) magnetron sputter in this research. High dielectric constant (κ) hafnium oxide (HfO₂) films and a-IZO were deposited for the gate insulator and the semiconducting channel under a mixture of ambient argon and oxygen gas, respectively. The bottom-gate TFTs showed good TFT characteristics, but the top-gate TFTs did not display the same characteristics as the bottom-gate TFTs despite undergoing the same process of sputtering with identical conditions. The electrical characteristics of the top-gate a-IZO TFTs exhibited strong relationships with sputtering power as gate dielectric layer deposition in this study. The ion bombardment and incorporation of sputtering ions damaged the interface between the active layer and the gate insulator in top-gate TFTs. Hence, the sputtering power was reduced to decrease damage while depositing HfO₂ films. When using 50 W DC magnetron sputtering, the top-gate a-IZO TFTs showed the following results: a saturation mobility of 5.62 cm²/V-s; an on/off current ratio of 1 × 10⁵; a sub-threshold swing (SS) of 0.64 V/decade; and a threshold voltage (V_th) of 2.86 V.     

Flexible organic thin-film transistors using single-walled carbon nanotubes as an activated channel

We report on the fabrication of organic thin-film transistors (OTFTs) with a spun cross linked poly-4-vinylphenol (PVP) dielectric on a polyethersulphone (PES) flexible substrate. To improve the electrical performance of OTFTs, we employed a random single-walled carbon nanotubes (SWNTs) network as a carrier transfer underlay without sacrificing the flexibility of the TFTs. The random SWNTs showed that they can act as a semiconducting channel and conduction path to shorten the channel length in our TFTs. The flexible thin-film transistors (TFTs) with a random SWNTs/pentacene bilayer as an active channel exhibited an improved saturation field effect mobility (µ_sat) of 2.6 × 10^− 1 cm²/Vs compared to that of TFTs without the SWNTs underlay, while creating only a minor reduction of the current on/off ratio.     

Resistive switching of HfO2-based Metal-Insulator-Metal diodes: Impact of the top electrode material

This paper deals with the impact of the top metal electrode on the resistive switching properties of HfO₂-based Metal-Insulator-Metal diodes. By screening five different metals as top electrode, Al-Cu-Hf-Pt-Ti, we have demonstrated the feasibility of the resistive switching effect on HfO₂. Metals with a low enthalpy of formation of oxides ΔH_f⁰ (Pt and Cu) lead to uni-polar switching whereas easily oxidizable metals with a higher ΔH_f⁰ (Al, Hf and Ti) lead to bipolar switching. Cu-, Hf- and Pt-based devices show a degradation of the top electrode after the forming step by the formation of bubbles whereas such phenomenon was not observed in Al- and Ti-based devices. 200 switching cycles were performed on each device in order to extract the main parameters of the resistive switching effect: I_ON and I_OFF currents in the mA range, R_OFF/R_ON resistance ratio up to 5, V_set and V_reset, voltage levels around 1 V, and powers dissipated during read and write operations in the μW and mW range, respectively. For all systems, the reset process dissipates higher power than the set process. From these results, the Ti top adlayer shows the best performance in terms of stability and resistive switching characteristics.     

Analysis of surface states and series resistance in Au/n-Si Schottky diodes with insulator layer using current-voltage and admittance-voltage characteristics

In order to good interpret the experimentally observed Au/n-Si (metal-semiconductor) Schottky diodes with thin insulator layer (18 Å) parameters such as the zero-bias barrier height (Φ_bo), ideality factor (n), series resistance (R_s) and surface states have been investigated using current-voltage (I-V), capacitance-frequency (C-f) and conductance-frequency (G-f) techniques. The forward and reverse bias I-V characteristics of Au/n-Si (MS) Schottky diode were measured at room temperature. In addition, C-f and G-f characteristics were measured in the frequency range of 1 kHz-1 MHz. The higher values of C and G at low frequencies were attributed to the insulator layer and surface states. Under intermediate forward bias, the semi-logarithmic Ln (I)-V plot shows a good linear region. From this region, the slope and the intercept of this plot on the current axis allow to determine the ideality factor (n), the zero-barrier height (Φ_bo) and the saturation current (I_S) evaluated to 2.878, 0.652 and 3.61 × 10⁻⁷ A, respectively. The diode shows non-ideal I-V behavior with ideality factor greater than unity. This behavior can be attributed to the interfacial insulator layer, the surface states, series resistance and the formation barrier inhomogeneity at metal-semiconductor interface. From the C-f and G-f characteristics, the energy distribution of surface states (N_ss) and their relaxation time (τ) have been determined in the energy range of (E_c − 0.493E_v)-(E_c − 0.610) eV taking into account the forward bias I-V data. The values of N_ss and τ change from 9.35 × 10¹³ eV⁻¹ cm⁻² to 2.73 × 10¹³ eV⁻¹ cm⁻² and 1.75 × 10⁻⁵ s to 4.50 × 10⁻⁴ s, respectively.     

The effect of metallization contact resistance on the measurement of the field effect mobility of long-channel unannealed amorphous In-Zn-O thin film transistors

The effect of contact resistance on the measurement of the field effect mobility of compositionally homogeneous channel indium zinc oxide (IZO)/IZO metallization thin film transistors (TFTs) is reported. The TFTs studied in this work operate in depletion mode as n-channel field effect devices with a field effect mobility calculated in the linear regime (μ_FE) of 20 ± 1.9 cm²/Vs and similar of 18 ± 1.3 cm²/Vs when calculated in the saturation regime (μ_FE^sat). These values, however, significantly underestimate the channel mobility since a large part of the applied drain voltage is dropped across the source/drain contact interface. The transmission line method was employed to characterize the contact resistance and it was found that the conducting-IZO/semiconducting-IZO channel contact is highly resistive (specific contact resistance, ρ_C > 100 Ωcm²) and, further, this contact resistance is modulated with applied gate voltage. Accounting for the contact resistance (which is large and modulated by gate voltage), the corrected μ_FE is shown to be 39 ± 2.6 cm²/Vs which is consistent with Hall mobility measurements of high carrier density IZO.     

Polymer binder effects on the electrical characteristics of 6, 13-bis(triisopropylsilylethynyl)-pentacene thin-film transistors in different solvents

This paper presents the effects of the polymer binder on the electrical properties of 6,13-bis(triisopropylsilylethynyl)-pentacene (TIPS-pentacene) organic thin-film transistors (OTFTs) which have been fabricated using a variety of 2 wt.% TIPS-pentacene solutions that have been prepared in different solutions, including anisole, toluene, and chlorobenzene. Poly(triarylamine) (PTAA) is added as a polymer binder to help the TIPS-pentacene form a stronger binding, thus improving device performances. By using these materials as the active channel, a molecular guest-host system is formed, with TIPS-pentacene as the host and the PTAA as the guest. Introducing the TIPS-pentacene solutions means that the polymer binder and the solvent dependent electrical characteristics can be investigated to determine if the device exhibits the best performance when the solution is prepared with anisole as the solvent and PTAA as the polymer binder. Consequently, a device made from anisole with PTAA exhibits superior electrical properties in comparison to the devices made with the other solutions including the saturation field-effect mobility (μ_sat) ?of 0.21 cm²/V?s, current on/off ratios of 5 × 10⁶, and a sub-threshold slope (SS) of 0.46 V/dec at a gate bias V_GS = -40 V.     

Effect of Ag doping on the performance of ZnO thin film transistor

Ag-doped zinc oxide (SZO) thin film transistors (TFTs) have been fabricated using a back-gate structure on thermally oxidized and heavily doped p-Si (100) substrate. The SZO thin films were deposited via pulsed laser deposition (PLD) from a 1, 3, and 5 wt.% Ag-doped ZnO (1SZO, 3SZO, and 5SZO, respectively) target using a KrF excimer laser (λ, 248 nm) at oxygen pressure of 350 mTorr. The deposition carried out at both room-temperature (RT) and 200 °C. The SZO thin films had polycrystalline phase with preferred growth direction of (002) as well as a wurtzite hexagonal structure. Compare with ZnO thin films, the SZO thin films were characterized by confirming the shift of (002) peak to investigate the substitution of Ag dopants for Zn sites. The as-grown SZO TFTs deposited at RT and 200 °C showed insulator characteristics. However the SZO TFTs annealed at 500 °C showed good n-type TFT performance because Ag was diffused from Zn lattice site and bound themselves at the high temperature, and it caused generation of electron carriers. The post-annealed 5SZO TFT deposited at 500 °C exhibited a threshold voltage (V_th) of 11.5 V, a subthreshold swing (SS) of 2.59 V/decade, an acceptable mobility (μ_SAT) of 0.874 cm²/V s, and on-to-off current ratios (I_on/off) of 1.44 × 10⁸.     

Ammonia-free chemically deposited CdS films as active layers in thin film transistors

In this work we have grown CdS thin films using an ammonia-free chemical bath deposition process for the active layer in thin film transistors. The CdS films were deposited substituting sodium citrate for ammonia as the complexing agent. The electrical characterization of the as-deposited CdS-based thin film transistors shows that the field effect mobility and threshold voltage were in the range of 0.12-0.16 cm²V⁻¹ s⁻¹ and 8.8-25 V, respectively, depending on the channel length. The device performance was improved considerably after thermal annealing in forming gas at 250 °C for 1 h. The mobility of the annealed devices increased to 4.8-8.8 cm²V⁻¹ s⁻¹ and the threshold voltage decreased to 8.4-12 V. I_on/I_off for the annealed devices was approximately 10⁵-10⁶.     

Amorphous In-Ga-Zn-O thin-film transistor with coplanar homojunction structure

Amorphous In-Ga-Zn-O (a-IGZO) thin-film transistors (TFTs) with a coplanar homojunction structure are demonstrated. The coplanar source and drain regions made of a-IGZO were formed by depositing a hydrogenated silicon nitride (SiN_X:H) layer onto the a-IGZO layer. The a-IGZO regions on which the SiN_X:H layer was directly deposited showed the low resistivity of 4.7 × 10⁻³  Ω cm and degenerated conduction. The fabricated TFT showed excellent transfer and output characteristics with a field-effect mobility of 11 cm² V^− 1 s^− 1, a subthreshold swing of 0.17 V decade^− 1, and an on-to-off current ratio larger than 1 × 10⁹. The width-normalized source-to-drain resistance (R_sdW) calculated using a channel resistance method was 51 Ω cm. This TFT also showed good stability over environment change and under electrical stress.     

Carrier transport mechanisms and photovoltaic characteristics of p-H2Pc/n-Si heterojunctions

Heterojunction cells of p-H₂Pc/n-Si were fabricated by vacuum deposition of p-H₂Pc thin films onto n-Si single crystals. Measurements of the current-voltage (I-V) and the capacitance—voltage (C-V) characteristics have been evaluated to identify the mechanisms of barrier formation and, consequently, current flow. The forward current involves tunneling and could be explained by a multi-step tunneling recombination model due to a high density of interface defects. The C-V characteristics indicate an abrupt heterojunction model. The devices exhibit strong photovoltaic characteristics with an open-circuit voltage of 0.34 V, a short-circuit current density of 17.5 mA/cm² and a power conversion efficiency of 1.5%. These parameters have been estimated at room temperature and under constant illumination of 150 mW/cm².     

Amorphous structure and electrical performance of low-temperature annealed amorphous indium zinc oxide transparent thin film transistors

The effect of low-temperature (200 °C) annealing on the threshold voltage, carrier density, and interface defect density of amorphous indium zinc oxide (a-IZO) thin film transistors (TFTs) is reported. Transmission electron microscopy and x-ray diffraction analysis show that the amorphous structure is retained after 1 h at 200 °C. The TFTs fabricated from as-deposited IZO operate in the depletion mode with on-off ratio of > 10⁶, sub-threshold slope (S) of ~ 1.5 V/decade, field effect mobility (μ_FE) of 18 ± 1.6 cm²/Vs, and threshold voltage (V_Th) of − 3 ± 0.7 V. Low-temperature annealing at 200 °C in air improves the on-current, decreases the sub-threshold slope (1.56 vs. 1.18 V/decade), and increases the field effect mobility (μ_FE) from 18.2 to 23.3 cm²/Vs but also results in a V_Th shift of − 15 ± 1.1 V. The carrier density in the channel of the as-deposited (4.3 × 10¹⁶ /cm³) and annealed at 200 °C (8.1 × 10¹⁷ /cm³) devices were estimated from test-TFT structures using the transmission line measurement methods to find channel resistivity at zero gate voltage and the TFT structures to estimate carrier mobility.     

Localization effect of a current-path in amorphous In-Ga-Zn-O thin film transistors with a highly doped buried-layer

The highly-doped buried layer (carrier concentration of ~ 10¹⁹ cm^− 3) in an amorphous indium-gallium-zinc oxide (a-IGZO) channel layer of thin film transistor (TFT) led to dramatic improvements in the performance and prolonged bias-stability without any high temperature treatment. These improvements are associated with the enhancement in density-of-states and carrier transport. The channel layer is composed of Ga-doped ZnO (GZO) and a-IGZO layers. Measurements performed on GZO-buried a-IGZO (GB-IGZO) TFTs indicate enhanced n-channel active layer characteristics, such as V_th, μ_FE, I_off, I_on/off ratio and S.S, which were enhanced to 1.2 V, 10.04 cm²/V·s, ~ 10⁻¹³A, ~ 10⁷ and 0.93 V/decade, respectively. From the result of simulation, a current path was well defined through the surface of oxide active layer especially in GB-IGZO TFT case because the highly-doped buried layer plays the critical role of supplying sufficient negative charge density to compensate the amount of positive charge induced by the increasing gate voltage. The mechanism underlying the high performance and good stability is found to be the localization effect of a current path due to a highly-doped buried layer, which also effectively screens the oxide bulk and/or back interface trap-induced bias temperature instability.