一种用于信息处理微系统DDR互连故障的自测试算法

为解决信息处理微系统中双倍速率同步动态随机存储器（Double Data Rate, DDR）复杂互连故障的检出效率和测试成本问题,通过分析DDR典型互连故障模式,将单个存储器件的自动测试设备（Auto Test Equipment,ATE）测试算法与板级系统的系统级测试（System Level Test, SLT）模式相结合,提出面向DDR类存储器的测试算法和实现技术途径。并基于现场可编程门阵列（Field Programmable Gate Array, FPGA）器件实现微系统内DDR互连故障的自测试,完成了典型算法的仿真模拟和实物测试验证。相较于使用ATE测试机台的存储器测试或通过用户层测试软件的测试方案,本文所采用的FPGA嵌入特定自测试算法方案可以实现典型DDR互连故障的高效覆盖,测试效率和测试成本均得到明显改善。     

一种高速增益单元存储器的内建自测试方案

介绍了一种用于测试高速增益单元嵌入式动态随机存储器的内建自测试方案。该方案包括了指令集设计和体系结构设计。四级指令流水线的引入使全速测试成为可能。该设计方案可以通过执行不同的测试指令,对待测存储器执行多种类型的测试,从而达到较高的故障覆盖率。该内建自测试模块被集成在了一个存储容量为8kb的增益单元嵌入式动态随机存储器芯片中,并在中芯国际0.13μm标准逻辑工艺下进行了流片验证。芯片测试结果表明,该内建自测试方案可以在多种测试模式下对待测存储器执行全速测试,提高了测试速度,降低了对自动测试设备的性能要求,提高了测试的效率。     

On-Chip SRAM内建自测试及其算法的研究

具体研究on-Chip SRAM的内建自测试及其算法.在引入嵌入式存储器内建自测试的基础上,详细分析on-Chip SRAM内建自测试的具体实现方法,反映出内建自测试对于简化测试程序和缩短测试时间,从而降低测试成本的重要性.详细描述在测试on-Chip SRAM时常用的算法,并具体分析非传统性测试算法——Hammer算法和Retention算法.     

一种有效的ADC内建自测试方案

内建自测试是降低ADC电路测试成本的有效方法。通过最小二乘法和斜坡柱状图。我们得出了测试ADC电路的增益误差、失调误差、微分非线性和积分非线性的算法。根据这些测试算法。介绍了一种易于片上集成的内建自测试结构。实验结果表明，该内建自测试方案具有较高的测试精度。     

嵌入式存储器内建自测试时间的优化

存储器测试是集成电路测试的重要部分。随着集成电路存储器件向着高集成度发展,存储器测试成本在集成电路总测试成本中所占比例急剧增高。通过减少存储器测试时间来减小存储器测试成本,是一种高效的降低芯片测试成本的方法。本文以一款单周期同步存储器为例,选取读写时序为对象,详细分析了存储器内建自测试方法,给出了一种通过优化存储器内建自测试逻辑时序来减小存储器测试时间的设计实现方法。     

低功耗测试矢量生成技术的研究

在集成电路内建自测试的过程中,电路的测试功耗通常显著高于正常模式产生的功耗,因此低功耗内建自测试技术已成为当前的一个研究热点。为了减少被测电路内部节点的开关翻转活动率,研究了一种随机单输入跳变（Random Single Input Change,RSIC）测试向量生成器的设计方案,利用VHDL语言描述了内建自测试结构中的测试向量生成模块,进行了计算机模拟仿真并用FPGA（EP1C6Q240C8）加以硬件实现。实验结果证实了这种内建自测试原理电路的正确性和有效性。     

V4系列FPGA全局时钟缓冲器的内建自测试研究

提出一种新的基于V4系列FPGA全局时钟缓冲器的内建自测试方法。目前关键时钟缓冲器内建自测试正面临巨大的挑战,时序问题是目前发现的时钟缓冲器内建自测试的主要问题。由于时钟缓冲器输入端的同步开关会产生不同的相移,使得正常的器件内建自测试中产生故障指示。此外,目前时钟缓冲器内建自测试使用的是普通的布线资源连接时钟信号,而不是使用专用的时钟布线资源,这种方法会加剧时序问题。提出一种改良的方法去解决内建自测试的时序问题,并讨论这种方法对于可测试的最大时钟频率和总测试时间的影响。所有测试环节均在V4系列FPGA上实现。     

基于BIST的编译码器IP核测试

介绍了用于IP核测试的内建自测试方法（BIST）和面向测试的IP核设计方法,指出基于IP核的系统芯片（SOC）的测试、验证以及相关性测试具有较大难度,传统的测试和验证方法均难以满足。以编译码器IP核为例,说明了基于BIST的编译码器IP核测试的基本实现原理和具体实现过程,通过加入测试外壳实现了对IP核的访问、隔离和控制,提高了IP核的可测性。     

SOC的可测试性设计策略

介绍了几种主要的VLSI可测性设计技术,如内部扫描法、内建自测试法和边界扫描法等,论述如何综合利用这些方法解决SOC内数字逻辑模块、微处理器、存储器、模拟模块、第三方IP核等的测试问题,并对SOC的可测性设计策略进行了探讨.     

数字VLSI电路测试技术-BIST方案

分析了数字VLSI电路的传统测试手段及其存在问题,通过对比的方法,讨论了内建自测试(BIST)技术及其优点,简介了多芯片组件(MCM)内建自测试的目标、设计和测试方案。     

Fully Programmable Memory BIST for Commodity DRAMs

To accomplish a high‐speed test on low‐speed automatic test equipment (ATE), a new instruction‐based fully programmable memory built‐in self‐test (BIST) is proposed. The proposed memory BIST generates a high‐speed internal clock signal by multiplying an external low‐speed clock signal from an ATE by a clock multiplier embedded in a DRAM. For maximum programmability and small area overhead, the proposed memory BIST stores the unique sets of instructions and corresponding test sequences that are implicit within the test algorithms that it receives from an external ATE. The proposed memory BIST is managed by an external ATE on‐the‐fly to perform complicated and hard‐to‐implement functions, such as loop operations and refresh‐interrupts. Therefore, the proposed memory BIST has a simple hardware structure compared to conventional memory BIST schemes. The proposed memory BIST is a practical test solution for reducing the overall test cost for the mass production of commodity DDRx SDRAMs.     

Scalable Delay Fault BIST for Use with Low-Cost ATE

We present a BIST architecture based on a Multi-Input Signature Register (MISR) expanding single input vectors into sequences, which are used for testing of delay faults. Input vectors can be stored on-chip or in the ATE; in the latter case, a low speed tester can be employed though the sequences are applied at-speed to the block-under-test. The number of input vectors (and thus the area demand on-chip or ATE memory requirements) can be traded for the test application time.We propose several methods for generating input vectors, which differ in test application time, area requirements and algorithm run-time. As all of them require only a two-pattern test as input, IP cores can be handled by these methods.The block-under-test can be switched off for some amount of time between application of consecutive input vectors. We provide arguments why this approach may be the only way to meet thermal and power constraints. Furthermore, we demonstrate how the BIST scheme can use these cool-down breaks for re-configuration.     

基于SMIC40LL工艺的DDR物理层IP设计

随着高性能消费电子如智能手机,平板电脑的迅速普及,对高性能低功耗的DDR接口电路的需求随之迅速增加。本文论述了在SMIC40LL工艺上实现了高性能、低功耗、小面积的DDR物理层IP技术,包括DDR物理层架构、DLL设计、10设计和物理实现。该物理层IP可以在ss条件下达到1333Mbps的速率并在核心电压稍稍过压下达到1600Mbps的速率。     

BIST-Based Delay-Fault Testing in FPGAs

We present the first delay-fault testing approach for Field Programmable Gate Arrays (FPGAs), applicable for on-line testing as well as for off-line manufacturing and system-level testing. Our approach is based on Built-In Self-Test (BIST), it is comprehensive, and does not require expensive external test equipment (ATE). We have successfully implemented this BIST approach for delay-fault testing on the Lattice ORCA 2C and Xilinx Spartan FPGAs.     

改进的IP可重用性评估程序

随着IP在设计中重用的次数和比例不断增加,工业界需要有一种客观、有效的可重用性评估方法.一方面,IP用户可以利用它从第三方供应商提供的众多同类型IP中选择合适、高可重用性的产品,从而最大程度的降低设计成本和风险;另一方面,开发者也必须对IP做出评估,并通过不断改进设计方法学达到提高产品质量的目的.本文在对国际通用的IP可重用性评估程序OpenMORE和QIP分析的基础上,针对其中存在较大的"主观误差"问题提出了改进的方法,改进后的方法较之现有方法在评分和权值设定等方面有了较大的改善.     

Hardware Generation of Random Single Input Change Test Sequences

The combination of higher quality requirements and sensitivity of high performance circuits to delay defects has led to an increasing emphasis on delay testing of VLSI circuits. As delay testing using external testers requires expensive ATE, built-in self test (BIST) is an alternative technique that can significantly reduce the test cost.It has been proven that Single Input Change (SIC) test sequences are more effective than classical Multiple Input Change (MIC) test sequences when a high robust delay fault coverage is targeted. It has also been shown that random SIC (RSIC) test sequences achieve a higher fault coverage than random MIC (RMIC) test sequences when both robust and non robust tests are under consideration; the experimental results were based on a software generation of RSIC sequences that are easily generated.Obviously, a hardware RSIC generation providing similar results can be obtained. However, this hardware generator must be carefully designed. In this paper, it is explained what are the criteria which must be satisfied for this purpose. A solution is proposed and illustrated with an example. Then, it is shown that a bad result may be obtained if one of these criteria is not satisfied.     

基于DDR SDRAM的CTM算法与实现

高分辨率SAR实时成像的大数据量使得矩阵转置运算量激增,成为算法研究中的重要问题。本文结合DDR SDRAM的内部运行机制和读写时序,提出面向DDR SDRAM的最快列读取CTM(corner turning memory,矩阵转置)和读写均衡CTM算法,在无冗余存储器DDR SDRAM体系中获得满意的效果。     

Testing analogue and mixed-signal integrated circuits by weighted sum of selected node voltages

System-on-chip (SOC) design based on intellectual property (IP) cores has become a growing trend in integrated circuit (IC) design. Testing of such cores is a challenging problem, especially when these cores are deeply embedded in the system chip. The wrapper of the P1500 standard can facilitate the testing of such cores; however, a full-size wrapper is expensive because the hardware overhead is large. If the requirement for testing I/O pins of IP cores is considered and reduced to a minimum during the core design, SOC designers will need to put much less effort into testing the cores. In this paper, a built-in self-test (BIST) technique, which is applicable to both analogue and mixed-signal integrated circuits and is based on the weighted sum of selected node voltages, is proposed. Besides high fault coverage, the proposed BIST technique needs only one extra testing output pin, and only a single dc stimulus is needed to feed at the primary input of the circuit under test (CUT). Hence, the proposed BIST technique is especially suitable for testing IP cores.