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逐次逼近A/D变换器和D/A变换器洪志良(复旦大学电子工程系,上海,200433)l引言逐次逼近A/D变换器是最早采用的A/D变换技术,由于它对工艺技术的要求不苛刻,使用硬件少,早期就被用于较高精度A/D变换器的集成中。逐次近似A/D变换不用额外的工... 相似文献
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一比特过取样A/D,D/A变换系统和多比特A/D,D/A变换系统相比较而言,有着独特的优越性。本文分析了仍存在的问题,并在原有的研究基础上继续分析了各种结构的一比特过取样A/D,D/A变换系统的输出波形和频谱。 相似文献
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过取样AD/DA变换(oversampledAD/DAConverter)作为一种电路设计技术,已经迎来了一个新的发展时期,该技术使用了△调制和△∑调制这些过去大家都很熟悉的优选电路,本文将说明这一新变换技术的原理,传统的AD/DA变换的极限范围,及它对大规模LSI设计的影响。过取样方式增加了数字处理的比重,减轻了模拟电路的负担,适应了VLSI发展的要求。 相似文献
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真RMS—DC变换器AD736/AD737 总被引:4,自引:0,他引:4
AD736/AD737是AD公司推出的真有效值直流变换器。和以往的有效值测量技术不同,真有效值直流变换可以直接测得各种波形的真实有效值,它不是采用整流加平均的测量技术,而是采用信号平方后积分的平均技术。采用AD736/AD737可以简化仪器的设计,增加信号测量品种,并且灵敏度、精确度也大大改善。本文讨论了真RMS测量技术的工作原理,并给出了AD736/AD737的典型应用电路。 相似文献
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过取样AD/DA变换作为一种电路设计技术,已经迎来了一个新的发展时期,该技术使用了△调制和△∑调制这些过去大家都很熟悉的优选电路,本文将说明这一新变换技术的原理,传统的AD/DA变的极限范围,及它对大规模LSI设计的影响。过取样方式增加了数字处理的比重,减轻了模拟电路的负担,适应了VLSI发展的要求 相似文献
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本文阐述了军用高速低功耗A/D变速器的设计与研制。B-MSZD A/D变换器具有集成度高、体积小、重量轻、功耗低、功能齐全等特性。 相似文献
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CCD(电荷耦合器件)信号处理器VSD2100是一款完整的数字相机IC,它为CCD阵列输出提供信号调理和10位A/D变换。它所提供的CCD信号处理包括:从像素获取视频信息的相关双取样(CDS);与供变化的照明度条件用的数字控制相当的0dB到+34dB增益;为得到精确黑色基准的黑色电平箝位。该信号处理器的特性包括53dBSNR。其10位A/D变换的变换率达27MHz,而且没有漏代码。低电压(2.7V到3.6V),低功率(2.7V为160mW,3.0V为190mW)便携工作。它的应用包括:视频相机,… 相似文献
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过采样∑-△A/D调制器洪志良(复旦大学电子工程系,上海,200433)1引言过采样∑-△A/D变换器通过过采样以时间来交换精度,从而避免实现高精度A/D变换器所需要的复杂性。∑-△调制器结构是迄今为止在数字VLSI技术中执行高精度A/D变换最吸引人... 相似文献
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A new pipeline D/A convertor configuration is presented. This structure can be used as a module in a pipeline A/D convertor. The advantage of this D/A structure is that the accuracy is not influenced by any stray capacitor such as bottom plates or drain/source junction capacitors. As a result video frequency operation can be obtained with this structure 相似文献
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一种基于流水逐次逼近比较方式的模/数转换器 总被引:1,自引:0,他引:1
提出了一种新型模数转换方法——流水逐次逼近比较式模数转换法,并给出了相应的实验结果。在达到逐次逼近比较A/D转换器的相同转换时间tc的前提下,流水逐次逼近比较式A/D转换器的m和n函数关系等同于逐次逼近比较A/D转换器,而其tc和n的函数关系优于逐次逼近比较A/D转换器,并且比较流水式A/D转换器易于实现。 相似文献
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A new method for the realisation of analogue multiplier/divider circuits is presented. The method uses a modified cyclic data convertor that operates sequentially as an A/D convertor and as a D/A multiplying convertor in such a way that it performs the analogue operation v/sub 0/=v/sub x/v/sub y//v/sub z/.<> 相似文献
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《Solid-State Circuits, IEEE Journal of》1976,11(6):795-800
A novel way to obtain a very high accuracy in the bit weighting required for bipolar monolithic digital-to-analog (D/A) converters is described. The new method combines passive division using matched elements with a time division concept, needs no trimming, and is insensitive to element aging. A 12-bit monolithic D/A network with internal reference sources, built as a test circuit, demonstrates the versatility of this new technique. 相似文献
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基于AD650的VFC型A/D转换器 总被引:1,自引:0,他引:1
针对实际工程的技术要求,设计了一种新型高精度模数转换电路——VFC型A/D转换器。该电路作为计算机控制系统与受控设备之间的接口电路,在计算机控制下,所有的逻辑判断和校正网络均由计算机软件实现,此转换电路不仅调试方便、简单,而且增加了系统的可靠性。实践表明,设计的VFC型A/D转换电路完全满足系统设计要求。本文详细叙述了VFC型A/D转换电路的工作原理、设计思想和实现方法。 相似文献
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This proposal of a new interpolation technique is presented for application in a double folding A/D converter with interpolation. This interpolation technique is applied in the master latches of the A/D converter without consumption increase. Compared to resistive interpolation, this new interpolation technique has the advantage of avoiding the resistive interpolation ladder adding only three transistors in some master latches and the current is the same as in the simple master latch. A 6-bit A/D converter was designed and implemented in a 1.2 μm BiCMOS process, an FT of 8 GHz, to explain the implementation of interpolation circuitry and evaluate the experimental results. 相似文献
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《Solid-State Circuits, IEEE Journal of》1979,14(6):912-920
A new multiple-differential-voltage input, MOS, sampled-data, `charge-balance' comparator which can `weight' or scale each of many input voltage pairs has been developed. This comparator easily allows a differential analog input voltage capability on a monolithic A/D converter and greatly reduces the required number of resistors and decoding switches of a potentiometric successive approximation register (SAR) A/D design. An 8 bit converter has been built which uses 20 Rs and 32 switches as compared to the 256 Rs and 512 switches of a standard 2/SUP N/R ladder design. Measurements made on the 8 bit A/D converter are reported and indicate that at least 12 bit converters are possible with this technique. Therefore, a 13 bit converter has been designed which exhibits even greater component reductions-33 Rs and 64 switches instead of 8192 Rs and 16384 switches. A simple interface to microprocessors is provided for both converters which makes use of the standard logic signals of the control bus where the A/D is designed to appear as memory or an I/O port to the microprocessor. A new flexible reference voltage circuit is presented which, in combination with the analog differential input voltage feature, can accommodate arbitrary analog input voltage spans with any desired zero scale offset. 相似文献
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Time-interleaved oversampling convertors 总被引:2,自引:0,他引:2
A new architecture is proposed which exploits the time-interleaving concept to increase the oversampling ratio in delta-sigma modulators. It is shown that the effective oversampling ratio is increased by a factor M through the use of M interconnected modulators. Although a high speed sample-and-hold circuit is still required for an analogue-to-digital convertor, speed constraints are significantly reduced for the majority of analogue parts such as loop filters, A/D and D/A blocks.<> 相似文献
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新型自控原理实验装置的研制 总被引:1,自引:1,他引:0
本文介绍了一种基于计算机并口A/D、D/A转换实现的新型自控原理实验装置。该装置由计算机、A/D及D/A接口板、模拟实验箱等组成,软件在Windows环境下用VB编制,实现了对实验数据的采集、存储和计算处理,使实验结果更准确直观,显著提高了实验效果。 相似文献