Non-destructive on-chip imaging flow cell-sorting system for on-chip cellomics

We have developed a non-destructive imaging flow cell-sorting system using an ultra-high-speed camera (shutter speed of 1/10,000 s) with a real-time image analysis unit and a poly(methyl methacrylate) (PMMA)-based disposable microfluidic chip for single-cell-based on-chip cellomics. It has a 3-D micropipetting device that supports fully automated sorting and collection of samples. The entire fluidic system is implemented in a disposable plastic chip, enabling biological samples to be lined up in a laminar flow using hydrodynamic focusing. Its optical system enables direct observation-based cell identification using specific image indexes and phase-contrast/fluorescence microscopy, real-time image processing. It has a non-destructive, wider dynamic range, sorting procedure using mild electrostatic force in a laminar flow; agarose gel electrodes are used to prevent electrode loss and electrolysis bubble formation. The microreservoir used for recultivating collected target cells is contamination-free. An integrated ultra-high-speed droplet polymerase chain reaction measurement module is used for DNA/mRNA analysis of the collected target cells. This system was used to separate cardiomyocyte cells from a mixture of various cells. All the operations were automated using the 3-D micropipetting device. The results demonstrate that this imaging flow cell-sorting system is practically applicable for biological research and clinical diagnosis.     

An energy-efficient design of microkernel-based on-chip OS for NOC-based manycore system

The chip multiprocessor is the most prolific processor design because its many cores enhance system performance. Network on chip (NOC) has been proposed as a promising model to solve the connection problem of the cores. However, a new challenge consists of fully benefiting from the on-chip network and the cores. In this paper, we propose a novel energy-efficient design of a microkernel-based on-chip operating system for an NOC-based manycore system. The operating system (OS) is partitioned into the microkernel and the other OS modules. They are distributed on the network to provide services to the user programs. Our experimental results show that our design can improve system performance with reduced power consumption.     

An on-chip self-repair calculation and fusing methodology

Laser fusing is a standard technique for improving yield with memory reconfiguration and repair, but implementing fusing in production can be challenging and costly. This article introduces an electrically programmable polysilicon fuse and shows how it can reduce fuse area and programming complexity.     

基于片上系统的EFI安全机制研究

实现了基本的Winnow算法、Balanced Winnow算法和带反馈学习功能的Winnow算法,并将其成功地应用于大规模垃圾邮件过滤,分别在SEWM2007和SEWM2008数据集上对上述三个算法进行了对比实验.实验结果表明,Winnow算法及其变体在分类效果和效率上都优于Logiisfic算法.     

Microfluidic network-based combinatorial dilution device for high throughput screening and optimization

We present a combinatorial dilution device using a three-layer microfluidic network that can produce systematic variations of buffer and additive solutions in a combinatorial fashion for high throughput screening and optimization. A proof-of-concept device providing seven combinations (ABC/D, AB/D, BC/D, AC/D, A/D, B/D, and C/D) of three additive samples (A, B, and C) into a buffer solution (D) has been demonstrated. Such combinations are often used in simplex-centroid mixture DOE (design of experiments), useful techniques to minimize the experimental efforts at maximal information output with systematic variations of large-scale components. Based on mathematical and electrical modeling and computational fluid dynamic simulation, the device has been designed, fabricated, and characterized.     

An optimised 3D topology for on-chip communications

Increasing system complexity, energy and device reliability, requirement of modular approach, structured layout, effective spatial reuse of resources, scalability and re-programmability have made network-on-chip (NoC) an obvious interconnection design alternative to the ubiquitous bus based on chip communication architecture in system-on-chip. Designing of a topology and its routing scheme plays a vital role in determining performance of any NoC architecture. In recent years, 3D stacked NoC architecture attracts added interest in NoC design as it offers improved performance and shorter global interconnect. In this paper, we have developed a partially, vertically interconnected 3D topology, namely 3D Recursive Network Topology (3D RNT) and prove that the topology has a Hamiltonian connectedness. We have developed deadlock-free routing algorithm for the 3D RNT topology. Also, we compare the performance of the 3D RNT with partially and fully connected 3D mesh topologies (3D PMT and 3D FMT) by conducting suitable experiments. The experiment results show that there is not much deviation in respect of the performance of the 3D RNT on comparing with 3D PMT and 3D FMT even though a number of vertical links are trimmed down to 75%, which is an encouraging outcome as far as design space is concerned.     

An optimal multiprocessor combinatorial auction solver

A combinatorial auction (CA) is an auction that permits bidders to bid on bundles of goods rather than just a single item. Unfortunately, winner determination for CAs is known to be NP-hard. In this paper, we propose a distributed algorithm to compute optimal solutions to this problem. The algorithm uses nagging, a technique for parallelizing search in heterogeneous distributed computing environments. Here, we show how nagging can be used to parallelize a branch-and-bound algorithm for this problem, and provide empirical results supporting both the performance advantage of nagging over more traditional partitioning methods as well as the superior scalability of nagging to larger numbers of processors.     

Applications of random sampling to virtual screening of combinatorial libraries

We describe statistical techniques for effective evaluation of large virtual combinatorial libraries (> 10(10) potential compounds). The methods described are used for computationally evaluating templates (prioritization of candidate libraries for synthesis and screening) and for the design of individual combinatorial libraries (e.g., for a given diversity site, reagents can be selected based on the estimated frequency with which they appear in products that pass a computational filter). These statistical methods are powerful because they provide a simple way to estimate the properties of the overall library without explicitly enumerating all of the possible products. In addition, they are fast and simple, and the amount of sampling required to achieve a desired precision is calculable. In this article, we discuss the computational methods that allow random product selection from a combinatorial library and the statistics involved in estimating errors from quantities obtained from such samples. We then describe three examples: (1) an estimate of average molecular weight for the several billion possible products in a four-component Ugi reaction, a quantity that can be calculated exactly for comparison; (2) the prioritization of four templates for combinatorial synthesis using a computational filter based on four-point pharmacophores; and (3) selection of reagents for the four-component Ugi reaction based on their frequency of occurrence in products that pass a pharmacophore filter.     

用于细胞培养的便携式电刺激器设计与实现

设计了一种以STC89C51单片机为核心的数字化多功能电刺激器,可根据用户需要产生直流、方波、正弦波、三角波和锯齿波共5种类型的电刺激信号,同时可实现各个波形的幅值和频率可调,其幅值输出范围为0～5V,频率范围为0～10 kHz,实现相同温度、湿度及培养基环境条件下,细胞培养过程中的电信号刺激以及高通量筛选.     

An on-chip signal suppression countermeasure to power analysis attacks

There are several attacks that exploit the presence of side channels in hardware implementations of cryptographic algorithms to extract secret data. Differential power analysis (DPA) and simple power analysis (SPA) attacks sense the power consumption of the hardware to extract the secret cryptographic key. These attacks either directly examine the power traces or carry out statistical operations on the power traces obtained from the hardware while executing the cryptographic algorithm. This paper presents a circuit that can be added to crypto-hardware to suppress information leakage through the power supply pin side channel. We discuss the design, simulation results and the limitations of the suppression circuit. We show that this countermeasure significantly increases the number of power trace samples required to undertake a DPA attack. The countermeasure does not require any assumptions about the design of the hardware under protection.     

虚拟组合衍生程序系统的研制

AVAL是一个自行设计、实现的虚拟组合衍生程序系统。该系统的基础是分子拓扑结构处理模块AVALsdk,经封装、集成为组合衍生程序AVALapp;再以C/S方式开发了CGI网站,并增加守护程序AVALd以适应AVALapp多任务、长时间运行的要求。该系统配合有机合成数据库,能查询分子骨架合成通式,还自动提供约100种取代基。除分子骨架,用户也可以提交自己的有机合成反应和取代基。对每个分子骨架,根据其R基团数目和每个R基团取代基数目的变化,AVAL可以生成不同数量级的衍生结构。     

启发式教学法在计算机专业学生系统能力培养的运用

计算机专业的学生需要更多地关心计算系统的整体特性.计算机科学与技术专业教学指导分委员会系统研究组对课程在系统能力培养方面的作用进行了层次划分,操作系统属于重组内容的核心课程.为探讨操作系统课程对学生系统能力培养的作用,以在Windows平台开展“生产者-消费者”实验为例,探讨了在操作系统实验课中运用“启发式”教学法.     

An architecture for high-performance scalable shared-memory multiprocessors exploiting on-chip integration

Recent technology improvements allow multiprocessor designers to put some key components inside the processor chip, such as the memory controller, the coherence hardware, and the network interface/router. In this paper, we exploit such integration scale, presenting a novel node architecture aimed at reducing the long L2 miss latencies and the memory overhead of using directories that characterize cc-NUMA machines and limit their scalability. Our proposal replaces the traditional directory with a novel three-level directory architecture, as well as it adds a small shared data cache to each of the nodes of a multiprocessor system. Due to their small size, the first-level directory and the shared data cache are integrated into the processor chip in every node, which enhances performance by saving accesses to the slower main memory. Scalability is guaranteed by having the second and third-level directories out of the processor chip and using compressed data structures. A taxonomy of the L2 misses, according to the actions performed by the directory to satisfy them, is also presented. Using execution-driven simulations, we show that significant latency reductions can be obtained by using the proposed node architecture, which translates into reductions of more than 30 percent in several cases in the application execution time.     

An on-chip cache compression technique to reduce decompression overhead and design complexity

This research explores a compressed memory hierarchy model which can increase both the effective memory space and bandwidth of each level of memory hierarchy. It is well known that decompression time causes a critical effect to the memory access time and variable-sized compressed blocks tend to increase the design complexity of the compressed memory systems. This paper proposes a selective compressed memory system (SCMS) incorporating the compressed cache architecture and its management method. To reduce or hide decompression overhead, this SCMS employs several effective techniques, including selective compression, parallel decompression and the use of a decompression buffer. In addition, fixed memory space allocation method is used to achieve efficient management of the compressed blocks. Trace-driven simulation shows that the SCMS approach can not only reduce the on-chip cache miss ratio and data traffic by about 35% and 53%, respectively, but also achieve a 20% reduction in average memory access time (AMAT) over conventional memory systems (CMS). Moreover, this approach can provide both lower memory traffic at a lower cost than CMS with some architectural enhancement. Most importantly, the SCMS is a more attractive approach for future computer systems because it offers high performance in cases of long DRAM latency and limited bus bandwidth.     

基于筛选进化模型的指标体系建立方法

针对评估指标的优选和权重分配问题,借鉴生物进化思想,构建筛选进化模型SEM,在筛选中计算基于欧氏距离的数据可信度和基于评价信息熵的指标适应度,根据指标适应度选择优势指标进入指标初始集,对劣势指标执行交叉和变异操作形成新的备选指标集。经过多轮筛选后建立指标初始集,并依据指标适应度进行权重分配。实例分析表明了该方法的可行性和有效性。     

Toward on-chip datacenters: a perspective on general trends and on-chip particulars

Due to economical reasons, the traditional philosophy in data centers was to scale out, rather than scaling up. However, the advances in CMP technology enabled chip multiprocessors to become more prevalent and they are expected to become more affordable and power-efficient in the coming years. Current trend towards more densely packaged systems and increasing demand for higher performance push the market towards placing datacenters on highly powerful chips that have many cores on a single platform. However, increasing the number of cores on a single chip brings along very important problems to be addressed at the chip level regarding the use of shared resources and QoS satisfaction. After briefly exploring current datacenter perspective, this paper captures the current state of the art in the field of chip multiprocessors through a detailed discussion of different studies that pave the way to the datacenters on-chip. Finally, a number of open research issues are highlighted with the intention of inspiring new contributions and developments in the field of datacenters on-chip.     

An immune memory clonal algorithm for numerical and combinatorial optimization

Inspired by the clonal selection theory together with the immune network model, we present a new artificial immune algorithm named the immune memory clonal algorithm (IMCA). The clonal operator, inspired by the immune system, is discussed first. The IMCA includes two versions based on different immune memory mechanisms; they are the adaptive immune memory clonal algorithm (AIMCA) and the immune memory clonal strategy (IMCS). In the AIMCA, the mutation rate and memory unit size of each antibody is adjusted dynamically. The IMCS realizes the evolution of both the antibody population and the memory unit at the same time. By using the clonal selection operator, global searching is effectively combined with local searching. According to the antibody-antibody (Ab-Ab) affinity and the antibody-antigen (Ab-Ag) affinity, The IMCA can adaptively allocate the scale of the memory units and the antibody population. In the experiments, 18 multimodal functions ranging in dimensionality from two, to one thousand and combinatorial optimization problems such as the traveling salesman and knapsack problems (KPs) are used to validate the performance of the IMCA. The computational cost per iteration is presented. Experimental results show that the IMCA has a high convergence speed and a strong ability in enhancing the diversity of the population and avoiding premature convergence to some degree. Theoretical roof is provided that the IMCA is convergent with probability 1.     

基于Fution模数混合FPGA芯片的心电仪片上系统开发

利用Actel公司的基于Flash构架的模数混合型Fusion系列FPGA芯片,设计了一款低功耗片上的心电监护仪采集显示系统.结合Fusion系列的FPGA芯片的各种资源,实现了心电采集预处理模块、数据的处理和显示模块的系统集成,完整地形成了片上系统.