A 5-GHz 20-dBm Power Amplifier With Digitally Assisted AM-PM Correction in a 90-nm CMOS Process

This paper presents an integrated CMOS power amplifier and a technique for correcting AM-PM distortion in power amplifiers. The linearization technique uses a varactor as part of a tuned circuit to introduce a phase shift that counteracts the AM-PM distortion of the power amplifier. The varactor is controlled by the amplitude of the IQ baseband data in a feedforward fashion. The technique has been demonstrated in a 5-GHz class-AB CMOS power amplifier designed for WLAN applications and implemented in a 90-nm CMOS process. The power amplifier delivers 16 dBm of average power while transmitting at 54 Mb/s (64 QAM). The proposed linearization technique is shown to improve the efficiency of the power amplifier by a factor of 2.8.     

An 800-MHz–6-GHz Software-Defined Wireless Receiver in 90-nm CMOS

A software-defined radio receiver is designed from a low-power ADC perspective, exploiting programmability of windowed integration sampler and clock-programmable discrete-time analog filters. To cover the major frequency bands in use today, a wideband RF front-end, including the low-noise amplifier (LNA) and a wide tuning-range synthesizer, spanning over 800 MHz to 6 GHz is designed. The wideband LNA provides 18-20 dB of maximum gain and 3-3.5 dB of noise figure over 800 MHz to 6 GHz. A low 1/f noise and high-linearity mixer is designed which utilizes the passive mixer core properties and provides around +70 dBm IIP2 over the bandwidth of operation. The entire receiver circuits are implemented in 90-nm CMOS technology. Programmability of the receiver is tested for GSM and 802.11g standards     

A 23-dBm 60-GHz Distributed Active Transformer in a Silicon Process Technology

In this paper, a distributed active transformer for the operation in the millimeter-wave frequency range is presented. The transformer utilizes stacked coupled wires as opposed to slab inductors to achieve a high coupling factor of k_f=0.8 at 60 GHz. Scalable and compact equivalent-circuit models are used for the transformer design without the need for full-wave electromagnetic simulations. To demonstrate the feasibility of the millimeter-wave transformer, a 200-mW (23 dBm) 60-GHz power amplifier has been implemented in a standard 130-nm SiGe process technology, which, to date, is the highest reported output power in an SiGe process technology at millimeter-wave frequencies. The size of the output transformer is only 160times160 mum² and demonstrates the feasibility of efficient power combining and impedance transformation at millimeter-wave frequencies. The two-stage amplifier has 13 dB of compressed gain and achieves a power-added efficiency of 6.4% while combining the power of eight cascode amplifiers into a differential 100-Omega load. The amplifier supply voltage is 4 V with a quiescent current consumption of 300 mA     

A 1.8-GHz CMOS Power Amplifier Using a Dual-Primary Transformer With Improved Efficiency in the Low Power Region

A 1.8-GHz CMOS power amplifier for a polar transmitter is implemented with a 0.18- RF CMOS process. The matching components, including the input and output transformers, were integrated. A dual-primary transformer is proposed in order to increase the efficiency in the low power region of the amplifier. The loss induced by the matching network for the low-output power region is minimized using the dual-primary transformer. The amplifier achieved a power-added efficiency of 40.7% at a maximum output power of 31.6 dBm. The dynamic range was 34 dB for a supply voltage that ranged from 0.5 to 3.3 V. The low power efficiency was 32% at the output power of 16 dBm.     

A 9–31-GHz Subharmonic Passive Mixer in 90-nm CMOS Technology

A subharmonic down-conversion passive mixer is designed and fabricated in a 90-nm CMOS technology. It utilizes a single active device and operates in the LO source-pumped mode, i.e., the LO signal is applied to the source and the RF signal to the gate. When driven by an LO signal whose frequency is only half of the fundamental mixer, the mixer exhibits a conversion loss as low as 8–11 dB over a wide RF frequency range of 9–31GHz. This performance is superior to the mixer operating in the gate-pumped mode where the mixer shows a conversion loss of 12–15dB over an RF frequency range of 6.5–20 GHz. Moreover, this mixer can also operate with an LO signal whose frequency is only 1/3 of the fundamental one, and achieves a conversion loss of 12–15dB within an RF frequency range of 12–33 GHz. The IF signal is always extracted from the drain via a low-pass filter which supports an IF frequency range from DC to 2 GHz. These results, for the first time, demonstrate the feasibility of implementation of high-frequency wideband subharmonic passive mixers in a low-cost CMOS technology.     

A Fully Integrated 3.3–3.8-GHz Power Amplifier With Autotransformer Balun

This paper demonstrates the usage of a differential autotransformer as an output balun for an integrated power amplifier (PA) operating at low-gigahertz frequencies. In comparison with a conventional transformer balun, an autotransformer balun offers lower power losses, thereby increasing the saturated output power and reducing the gain compression at the edge of target power range. A theoretical analysis of an integrated autotransformer is given, comparison with a magnetic transformer is performed. The concept was experimentally verified in a fully integrated PA for a 3.3-3.8-GHz WiMAX band fabricated in SiGe : C bipolar technology. The active part of the amplifier implements the derivative superposition method aimed at linearizing the power transfer characteristic. Measured PA delivers saturated output power above 29 dBm. The maximum achieved power-added efficiency exceeds 40% at 3.4 GHz. At 3.5 GHz, 1-dB gain compression occurs for P _out = 24.6 dBm.     

A 1.5-V 2–9.6-GHz Inductorless Low-Noise Amplifier in 0.13-μm CMOS

This paper presents an inductorless low-noise amplifier (LNA) design for an ultra-wideband (UWB) receiver front-end. A current-reuse gain-enhanced noise canceling architecture is proposed, and the properties and limitations of the gain-enhancement stage are discussed. Capacitive peaking is employed to improve the gain flatness and -3-dB bandwidth, at the cost of absolute gain value. The LNA circuit is fabricated in a 0.13-mum triple-well CMOS technology. Measurement result shows that a small-signal gain of 11 dB and a -3-dB bandwidth of 2-9.6 GHz are obtained. Over the -3-dB bandwidth, the input return loss is less than -8.3 dB, and the noise figure is 3.6-4.8 dB. The LNA consumes 19 mW from a low supply voltage of 1.5 V. It is shown that the LNA designed without on-chip inductors achieves comparable performances with inductor-based designs. The silicon area is reduced significantly in the inductorless design, the LNA core occupies only 0.05 mm², which is among the smallest reported designs.     

A 71–80 GHz Amplifier Using 0.13- μm CMOS Technology

A 71-80 GHz amplifier using 0.13-mum standard mixed signal/radio frequency complementary metal-oxide-semiconductor (CMOS) technology is presented in this letter. This four-stage cascade thin-film microstrip amplifier achieves the peak gain of 7.0 dB at 75 GHz. The 3-dB frequency bandwidth range is from 71 to 80 GHz. The amplifier demonstrates the highest amplification frequency and smallest chip size among previous published millimeter-wave (MMW) 0.13-mum CMOS amplifiers.     

Analysis and Design of Reduced-Size Marchand Rat-Race Hybrid for Millimeter-Wave Compact Balanced Mixers in 130-nm CMOS Process

The analysis and design flow for reduced-size Marchand rat-race hybrids are presented in this paper. A simplified single-to-differential mode is used to analyze the Marchand balun, and the methodology to reduce the size of Marchand balun is developed. The 60-GHz CMOS singly balanced gate mixer and diode mixer using the reduced-size Marchand rat-race hybrid are implemented to verify the design methodology. The monolithic microwave integrated circuit mixers achieve comparable performance with a compact chip size among the reported 60-GHz CMOS mixers.      

A 56–65 GHz Injection-Locked Frequency Tripler With Quadrature Outputs in 90-nm CMOS

A sub-harmonic injection-locked tripler multiplies a 20-GHz differential input to 60-GHz quadrature (I/Q) output signals. The tripler consists of a two-stage ring oscillator driven by a single-stage polyphase input filter and 50-$Omega$ I and Q-signal output buffers. Each gain stage incorporates a hard limiter to triple the input frequency for injection locking and a negative resistance cell with two positive feedback loops to increase gain. Regenerative peaking is also used to optimize the gain/bandwidth performance of the 50-$Omega$ output buffers. Fabricated in 90-nm CMOS, the tripler has a free-running frequency of 60.6 GHz. From a 0-dBm RF source, the measured output lock range is 56.5–64.5 GHz, and the measured phase noise penalty is 9.2 $ pm 1~$dB with respect to a 20.2-GHz input. The $0.3times 0.3~ hbox{mm}^{2}$ tripler (including passives) consumes 9.6 mW, while the output buffers consume 14.2 mW, all from a 1-V supply.      

An RF Power Amplifier in a Digital CMOS Process

A two stage class B power amplifier for 1.9 GHz is presented. The amplifier is fabricated in a standard digital EPI-CMOS process with low resistivity substrate. The measured output power is 29 dBm in a 50 load. A design method to find the large signal parameters of the output transistor is presented. It separates the determination of the optimal load resistance and the determination of the large signal drain-source capacitance. Based on this method, proper values for on-chip interstage matching and off-chip output matching can be derived. A envelope linearisation circuit for the PA is proposed. Simulations and measurements of a fabricated linearisation circuit are presented and used to calculate the achievable linearity in terms of the spectral leakage and the error vector magnitude of a EDGE (3/8-8PSK) modulated signal.     

CMOS伪差分E类射频功率放大器设计

分析了E类功放的非理想因素,其中着重分析寄生电感对系统性能的影响,采用伪差分E类功放结构有效地抑制寄生电感的影响。最后基于理想的设计方程和Load Pull技术,采用 0.18 μm CMOS工艺,设计出高效率的差分E类功率放大器。在电源电压1.8 V,温度25 ℃,输入信号0 dBm条件下,具有最大输出功率26.1 dBm,PAE为60.2%。     

UHF宽带线性功率放大器设计

针对电磁环境模拟器应用设计了一个全固态UHF波段多级宽带线性高功率放大器。驱动放大器工作在A类，末级放大器以三个AB类功放模块频域分段覆盖工作频段，通过控制PIN开关切换。末级输出接低通滤波器改善谐波。实测从400MHz～1250MHz，功放的1dB压缩点功率为25W（44dBm），二次谐波低于-40dBc，输出功率在38dBm时双音测试三阶交调（IM3）优于-44dBc。     

一种Ka波段宽带功率合成放大器的设计

随着电子对抗等宽带微波系统的日益发展,毫米波宽带功率放大器需求也越加强烈。近年来随着空间功率合成技术研究的深入开展,基于波导内的空间合成技术在合成效率、相对带宽和实用化方面均展现了良好的特性,受到了广泛的关注。介绍了一种新颖的小型化空间功率合成器,基于波导内空间合成技术,采用非均匀对极鳍线的等分过渡方式,对BJ320波导进行分层结构设计并实现了一种Ka全频段功率放大器,在32 mm×30 mm×24 mm总体积内实现了4路合成,显示出了良好的工作性能。     

2-GHz CMOS射频低噪声放大器的设计与测试

本文采用CMOS工艺,针对无线通信系统前端(Front-end)的低噪声放大器进行了分析、设计、仿真和测试.测试结果表明,该放大器工作在2.04-GHz的中心频率上,3dB带宽约为110MHz,功率增益为22dB,NF小于3.3dB.测试结果与仿真结果能够很好地吻合.     

A 5.8 GHz 1 V Linear Power Amplifier Using a Novel On-Chip Transformer Power Combiner in Standard 90 nm CMOS

A fully integrated 5.8 GHz Class AB linear power amplifier (PA) in a standard 90 nm CMOS process using thin oxide transistors utilizes a novel on-chip transformer power combining network. The transformer combines the power of four push-pull stages with low insertion loss over the bandwidth of interest and is compatible with standard CMOS process without any additional analog or RF enhancements. With a 1 V power supply, the PA achieves 24.3 dBm maximum output power at a peak drain efficiency of 27% and 20.5 dBm output power at the 1 dB compression point.     

35–65-GHz CMOS Broadband Modulator and Demodulator With Sub-Harmonic Pumping for MMW Wireless Gigabit Applications

Sub-harmonic modulator and demodulator are presented in this paper using 0.13-mum standard CMOS technology for millimeter-wave (MMW) wireless gigabit direct-conversion systems. To overcome the main problem of local oscillator (LO) leakage in direct-conversion systems, the sub-harmonically pumped scheme is selected in this mixer design. An embedded four-way quadrature divider is utilized in the sub-harmonic Gilbert-cell design to generate quadrature-phases LO signals at MMW frequency. For broadband applications, a broadband matching design formula is provided in this paper to extend the operational frequency range from 35 to 65 GHz. To improve the flatness of conversion loss at high frequency, high-impedance compensation lines are incorporated between the transconductance stage and LO switching quad of the Gilbert-cell mixer to compensate the parasitic capacitance. The sub-harmonic modulator and demodulator exhibit 6 plusmn1.5 dB and 7.5 plusmn1.5 dB measured conversion loss, respectively, from 35 to 65 GHz. For MMW wireless gigabit applications, the gigabit modulation signal test is successfully performed through the direct-conversion system in this paper. To our knowledge, this is the first demonstration of the MMW CMOS sub-harmonic modulator and demodulator that feature broadband and gigabit applications.     

一种非均匀结构的分布式功率放大器的设计

宽带功率放大器的应用对于提升脉冲多普勒雷达等军用和民用系统的性能具有重要的意义。采用0.18 μm CMOS工艺,设计了一种非均匀结构的宽带分布式功率放大器。采用峰化电感以提高放大器的增益,在漏极人工传输线的输出端增加L型匹配网络,改善了放大器的阻抗匹配特性。仿真结果表明,该放大器在1.5～15 GHz频率范围内的增益为10.7 dB,带内增益平坦度为±1 dB;1 dB压缩点处的输出功率为6.3~9.8 dBm,PAE为6.8%~15%;饱和输出功率为9.4~12.3 dBm,对应的PAE达到14%~26.7%,表现出良好的综合性能。     

基于40 nm CMOS工艺的高效率功率放大器设计

针对硅基毫米波功率放大器存在的饱和输出功率较低、增益不足和效率不高的问题,基于TSMC 40nm CMOS工艺,设计了一款工作在28GHz的高效率和高增益连续F类功率放大器。提出的功率放大器由驱动级和功率级组成。针对功率级设计了一款基于变压器的谐波控制网络来实现功率合成和谐波控制,有效地提高了功率放大器的饱和输出功率和功率附加效率。采用PMOS管电容抵消功率级的栅源电容,进一步提高线性度和增益。电路后仿真结果表明,设计的功率放大器在饱和输出功率为20.5dBm处的峰值功率附加效率54%,1dB压缩点为19dBm,功率增益为27dB,在24GHz~32GHz频率处的功率附加效率大于40%。     

Design of a 1.7-GHz low-power delay-fault-testable 32-b ALU in 180-nm CMOS technology

In this paper, we present the design of a 32-b arithmetic and log unit (ALU) that allows low-power operation while supporting a design-for-test (DFT) scheme for delay-fault testability. The low-power techniques allow for 18% reduction in ALU total energy for 180-nm bulk CMOS technology with minimal performance degradation. In addition, there is a 22% reduction in standby mode leakage power and 23% lower peak current demand. In the test mode, we employ a built-in DFT scheme that can detect delay faults while reducing the test-mode automatic test equipment clock frequency.