Fast base extension and precise scaling in RNS for look-up tableimplementations

Both base extension and scaling are fundamental operations in residue computing and several techniques have been proposed previously for their efficient implementation. Using look-up tables, the best result (log₂ n table took-up cycles, where n is the number of residue moduli in the system) has been obtained by using the Chinese remainder theorem (CRT) at the expenses of a redundant representation of the numbers and of an approximated scaling. The CRT approach is reconsidered and it is shown that the same average time performances (log₂ n lookup cycles) can be achieved without any redundancy and with a precise result for scaling     

SOC集成电路设计的新纪元

介绍了ＳＯＣ集成电路设计的方法,过程。     

Design and Implementation of High-Performance RNS Wavelet Processors Using Custom IC Technologies

The design of high performance, high precision, real-time digital signal processing (DSP) systems, such as those associated with wavelet signal processing, is a challenging problem. This paper reports on the innovative use of the residue number system (RNS) for implementing high-end wavelet filter banks. The disclosed system uses an enhanced index-transformation defined over Galois fields to efficiently support different wavelet filter instantiations without adding any extra cost or additional look-up tables (LUT). A selection of a small wordwidth modulus set are the keys for attaining low-complexity and high-throughput. An exhaustive comparison against existing two's complement (2C) designs for different custom IC technologies was carried out. Results reveal a performance improvement of up to 100% for high-precision RNS-based systems. These structures demonstrated to be well suited for field programmable logic (FPL) assimilation as well as for CBIC (cell-based integrated circuit) technologies.     

New integer programming scheme for nonrecursive digital filter design

A new mixed-integer linear programming objective function for optimising an f.i.r. linear-phase digital filter is presented. In comparison with the conventional objective function, the new one has the advantages of reducing the number of delays and/or the coefficient wordlength.     

MOSFET modeling for RF IC design

High-frequency (HF) modeling of MOSFETs for radio-frequency (RF) integrated circuit (IC) design is discussed. Modeling of the intrinsic device and the extrinsic components is discussed by accounting for important physical effects at both dc and HF. The concepts of equivalent circuits representing both intrinsic and extrinsic components in a MOSFET are analyzed to obtain a physics-based RF model. The procedures of the HF model parameter extraction are also developed. A subcircuit RF model based on the discussed approaches can be developed with good model accuracy. Further, noise modeling is discussed by analyzing the theoretical and experimental results in HF noise modeling. Analytical calculation of the noise sources has been discussed to understand the noise characteristics, including induced gate noise. The distortion behavior of MOSFET and modeling are also discussed. The fact that a MOSFET has much higher "low-frequency limit" is useful for designers and modelers to validate the distortion of a MOSFET model for RF application. An RF model could well predict the distortion behavior of MOSFETs if it can accurately describe both dc and ac small-signal characteristics with proper parameter extraction.     

Constraint transformation for IC physical design

In a top-down design methodology, design tasks are divided into simpler subtasks across levels of a hierarchy as an effective divide-and-conquer technique. For every task, tolerances are defined on all performance characteristics to take into account parasitics, mismatches, and other nondeterministic process parameter variations. Constraint transformation is a process used to translate performance specifications into subtask requirements. This paper introduces the problem of constraint transformation and describes some formal solutions for analog circuit applications. Examples illustrate the methodology and show the suitability of this approach in industrial-strength applications     

Monolithic transformers for silicon RF IC design

A comprehensive review of the electrical performance of passive transformers fabricated in silicon IC technology is presented. Two types of transformer construction are considered in detail, and the characteristics of two-port (1:1 and 1:n turns ratio) and multiport transformers (i.e., baluns) are presented from both computer simulation and experimental measurements. The effects of parasitics and imperfect coupling between transformer windings are outlined from the circuit point of view. Resonant tuning is shown to reduce the losses between input and output at the expense of operating bandwidth. A procedure for estimating the size of a monolithic transformer to meet a given specification is outlined, and circuit examples are used to illustrate the applications of the monolithic transformer in RF ICs     

MOS transistor modeling for RF IC design

This paper presents the basis of the modeling of the MOS transistor for circuit simulation at RF. A physical equivalent circuit that can easily be implemented as a Spice subcircuit is first derived. The subcircuit includes a substrate network that accounts for the signal coupling occurring at HF from the drain to the source and the bulk. It is shown that the latter mainly affects the output admittance Y22. The bias and geometry dependence of the subcircuit components, leading to a scalable model, are then discussed with emphasis on the substrate resistances. Analytical expressions of the Y parameters are established and compared to measurements made on a 0.25-μm CMOS process. The Y parameters and transit frequency simulated with this scalable model versus frequency, geometry, and bias are in good agreement with measured data. The nonquasi-static effects and their practical implementation in the Spice subcircuit are then briefly discussed. Finally, a new thermal noise model is introduced. The parameters used to characterize the noise at HF are then presented and the scalable model is favorably compared to measurements made on the same devices used for the S-parameter measurement     

Design on ESD protection scheme for IC with power-down-mode operation

This paper presents a new electrostatic discharge (ESD) protection scheme for IC with power-down-mode operation. Adding a VDD ESD bus line and diodes into the proposed ESD protection scheme can block the leakage current from I/O pin to VDD power line and avoid malfunction during power-down operation. The whole-chip ESD protection design can be achieved by insertion of ESD clamp circuits between VSS power line and both the VDD power line and VDD ESD bus line. Experiment results show that the human-body model (HBM) ESD level of this new scheme can be greater than 7.5 kV in a 0.35-/spl mu/m silicided CMOS process.     

中国IC设计企业的发展思路

IC产业已经开始向中国转移,汽车产业的发展、"中国制造2025"的提出、国内的集成电路已具备一定基础,基于这些优势,中国的IC产业将会面临弯道超车的新机遇.     

集成电路设计中的IP设计与集成方法

在集成电路芯片设计中采用IP核(Intellectual Property Core)是IC设计进入SoC时代的必然选择,它可以达到提高设计效率、节省人力、满足及时上市的要求.重点阐述了IP的定义、分类、特征,国内外IP产业的发展状况以及IP的设计、验证、集成过程中的技术.     

几种新型集成电路器件的封装技术

介绍了目前集成电路器件封装的发展情况,重点是目前受到市场普遍关注的ＢＧＡ（球栅阵列）、ＱＦＰ（矩型扁平封装）和ＣＳＰ（芯片尺寸封装）器件的封装的技术。     

Power and area-optimised Carry-Select Adder architecture for standard cell-based design

A Carry-Select Adder (CSA) is one of the most suitable adders for high-speed applications, but the power and area penalties are greater, because it requires a double Ripple-Carry Adder (RCA) structure corresponding to carry inputs 0 and 1. Current low-power and low-area techniques are not suitable for a standard cell-based design which is one of the widely adopted design methodologies. Our work proposes two simple optimised architectures suitable for standard cell-based designs. A simple decision logic that replaces the RCA for Carry input 1 in a conventional CSA is proposed. One of the proposed architectures reduces power and area significantly with a small delay penalty compared to the existing techniques. Another proposed architecture improves the speed of operation and reduces the power and area considerably. The first one is more suitable for high-speed arithmetic in battery-operated applications where there is a trade-off between speed and power, while the other one is suitable for high-performance applications which also require area and power optimisation. The proposed architectures were implemented in TSMC 0.18um CMOS technology, and compared with conventional Square Root Carry-Select Adders and an existing standard cell-based design.     

Opportunistic multichannel driving scheme for low power mobile TFT-LCD driver IC

A novel source driving scheme called opportunistic multichannel driving (OMCD) is proposed for use in mobile TFT-LCD driver ICs (T-LDIs). In the OMCD scheme, the operation of the source drivers of a T-LDI is controlled by the equivalence of RGB colour data for adjacent pixels. That is, one source driver drives the neighbouring source lines as well as the corresponding one when the colour data of adjacent pixcels are identical to each other. With this scheme, all the source drivers associated with the neighbouring source lines can be completely turned off, allowing the reduction of static and dynamic current of these drivers. A test chip was fabricated in a 5 V/0.8 /spl mu/m 2.5 V/0.25 /spl mu/m triple-metal CMOS process, and the experimental result shows that the power reduction of 12-21% was obtained with die size overhead less than 0.5%.     

Cross-layer design scheme for multihop communications

A cross-layer design scheme for wireless communications is proposed and the performance evaluated. The scheme combines a truncated automatic repeat request (ARQ) protocol at the data link layer and multihop transmission at the physical layer. Closed-form solutions are derived for the average throughput and the average number of transmissions required to send a packet when the channel surfers from Nakagami-m fading. Finally, the improvement, when the cross-layer design is implemented is shown.     

基于IP核开发模式的高校集成电路设计发展策略研究

针对当前集成电路领域企业缺少原始技术积累、高校成果转化困难的问题,提出一种以IP核合作方式促进高校集成电路设计加快发展、实现高校企业双赢的创新机制。高校作为我国IC产业链中不可缺少的一部分,以西安交通大学SoC设计中心近十年来的发展历程为案例进行分析,提出基于IP核开发的高校集成电路设计发展的具体策略。     

An RNS Architecture for Quasi-Chaotic Oscillators

Wideband chaotic carrier is a promising solution for wideband communication, since it overcomes the disadvantages of both narrowband and spread-spectrum communication. It is particularly suited to realize information encryption for secure communication. Chaotic signals can be generated by using discrete-time non-linear dynamical circuits, since they can exhibit a quasi-chaotic (QC) behavior. A particular implementation of QC digital filters can be based on finite precision arithmetic and, in particular, on residue number system (RNS) circuits, which possess very attractive features with regard to their VLSI implementation. In the present paper, we propose an RNS architecture that can be used in connection with secure communication. Each RNS channel consists of a QC oscillator, having its coefficients belonging to a Galois field defined by a prime modulus. In particular, the QC behavior is ensured by well-known properties of primitive polynomials in this field, which generate the characteristic feedback of the oscillator. We demonstrate in the paper that the proposed RNS architecture yields a cost-effective VLSI implementation, which favorably compares with respect to other secure communication approaches proposed in the technical literature. We obtain encouraging results both in terms of confidentiality of the encrypted information and of throughput rate for real-time applications. Moreover, we propose an extended architecture suited to the protection of the secure communication system against transmission errors, by using the self-correcting ability of Redundant RNS (RRNS).     

A Generalization of a Fast RNS Conversion for a New 4-Modulus Base

A generalization of a new generic 4-modulus base for residue number systems (RNS) is presented in this paper. An efficient RNS to binary conversion algorithm and a hierarchical architecture for these bases are also described. The key features of our conversion architecture compared to previous published architectures of the same output range are a larger moduli set selection and savings on the critical delay, area and power. The FPGA implementation and the detailed proof supporting it are also discussed.      

Embeded EEPROM Memory Achieving Lower Power - New design of EEPROM memory for RFID tag IC

A 2-kb embedded EEPROM memory, operating over a wide voltage range (typically 2.5 V-5 V), was designed and fabricated using the SMIC 0.35-mum 2P3M CMOS embedded EEPROM process. The chip size is about 0.6 mm². The method of adding control transistors improved the static power dissipation. The transient power consumption of the charge pump circuit was greatly reduced by using a slowly varying clock. The proposed SA using a voltage sensing method also significantly improved the read power dissipation. By employing these techniques, a low-power embedded EEPROM memory with 40 muA read current and 250 muA page write current was developed, that achieved much lower power than EEPROM memory designs reported in scientific journals or conferences. This EEPROM memory was used in the ISO/IEC 15693-compatible RFID tag IC project