氢化非晶硅的红外光谱及氢释放的研究

用等离子体增强化学气相淀积（ Ｐ Ｅ Ｃ Ｖ Ｄ）制备了氢化非晶硅薄膜（ａ Ｓｉ∶ Ｈ）并进行了退火实验, 利用红外吸收光谱（ Ｉ Ｒ）和金相显微镜研究薄膜中的氢含量及退火前后的脱氢现象, 得出材料组成及热稳定性对衬底温度 Ｔｓ 和射频功率 Ｐｒｆ 的依赖关系。     

利用电子束掺杂技术制备微米,亚微米P—MOSFET器件

本文对辉光放电电子束在ＭＯＳＦＥＴ中的应用进行研究。结果表明，利用辉光放电电子束掺杂方法成功地实现了微米、亚微米Ｐ－ＭＯＳＦＥＴ。器件的漏流小，Ｉ－Ｖ特性好，源漏结浅、均匀和横向掺杂效应小。此方法与常规ＭＯＳ工艺兼容，所需的设备结构简单、操作方便，价格低廉，易于推广到ＶＬＳＩ中去。     

利用电子束掺杂技术制备微米、亚微米P－MOSFET器件

本文对辉光放电电子束在ＭＯＳＦＥＴ中的应用进行研究．结果表明，利用辉光放电电子束掺杂方法成功地实现了微米、亚微米Ｐ－ＭＯＳＰＥＴ．器件的漏流小，Ｉ－Ｖ特性好，源漏结浅、均匀和横向掺杂效应小．此方法与常规ＭＯＳ工艺兼容，所需的设备结构简单、操作方便，价格低廉，易于推广到ＶＬＳＩ中去．     

氢化非晶碳膜与硅的界面特性

利用直流辉光放电分解碳氢气体来淀积ａ－Ｃ：Ｈ膜，通过测量Ａｌ／ａ－Ｃ：Ｈ／ＳｉＭＩＳ结构的高频Ｃ－Ｖ曲线讨论了ａ－Ｃ：Ｈ／Ｓｉ界面的电子特性，结果表明ａ－Ｃ：Ｈ／Ｓｉ膜有可能用作半导体器件的表面钝化膜。     

利用氟化气体和氧气的混和物进行SiC薄膜的反应离子刻蚀

本文研究了在ＳＦ６，ＣＢｒＦ３和ＣＨＦ３与氧相混合的几种氟化气体等离子体中，ＳｉＣ薄膜反应离子刻蚀（ＲＩＥ）的深度。通过监测射频等离子体的光发射谱及产生等离子体的直流偏压来研究刻蚀机理，为了更精确地定量分析刻蚀工艺，使用氩光能测定技术使等离子发射强度转换为相应的等离子物质浓度。为获得选择性的ＳｉＣ－Ｓｉ刻蚀及ＳｉＣ薄膜的各向异性图形，对等离子体条件，如气体混合物的构成，压力和功率进行了研究。首次采     

非晶硅太阳电池效率研究

介绍了近年来用辉光放电法制备的ａ－Ｓｉ：Ｈ太阳电池的效率问题，文中讨论了有效光电能量转换的条件；ａ－Ｓｉ：Ｈ电池的结构，新型的高效率非晶硅太阳电池的改进；非晶硅ａ－Ｓｉ：Ｈ太阳电池的展望等。     

铝硅合金激光熔凝处理后的电化学腐蚀现象

利用２ｋＷＣＯ２激光器对不同合Ｓｉ量的ＡＩ－Ｓｉ合金进行了搭接扫描熔凝处理，通过ＳＥＭ和ＴＥＭ对激光熔凝处理后Ａｌ－Ｓｉ合金的组织结构进行了观察，通过测定在不同介质条件下的阳极极化曲线，讨论了激光熔凝处理对ＡＩ－ｓｉ合金耐蚀性的影响。结果表明，激光处理可改善Ａｌ－Ｓｉ合金在１０％Ｈ２ＳＯ４和１０％ＨＮＯ３溶液中的耐蚀性，而对Ａｌ－Ｓｉ合金在１０％ＨＣｌ和５％ＮａＣｌ溶液中的耐蚀性没有明显的促进作用。     

与等离子体相关的真空沉积技术及其应用

介绍了产生等离子几种放电方式（如直流二极放电，射频放电，真空辉光放电，真空弧光放电等）与等离子体相关的溅射沉积，离子镀沉积等常用的真空沉积技术及其在薄膜 备中的应用。     

纳米硅／非晶硅多层膜室温可见光致发光研究

本文报道了在用等离子体增强化学汽相淀积法制备的氢化纳米硅（ｎｃ－Ｓｉ：Ｈ）／氢化非晶硅（ａ－Ｓｉ：Ｈ）多层膜中，未经任何后处理工艺，观察到室温可见光致发光（ＰＬ）．当ｎｃ－Ｓｉ：Ｈ层厚度由４．０ｎｍ下降至２．１ｎｍ时，ＰＬ峰波长由７５０ｎｍ兰移至７０８ｎｍ．本文将这种对量大于Ｓｉ单晶能隙的光发射归因于多层膜中ｎｃ－Ｓｉ：Ｈ子层的量子尺寸效应．     

钯／超薄氧化层／硅隧道二极管氢敏器件的研制

本文采用Ｐｄ／ＵＴＳｉＯ２／ｎ－Ｓｉ隧道二极管结构，研制出在室温下空气中，对１５０ｐｐｍ氢气反向电流改变１０倍以上的氢敏器件。     

To suppress photoexcited current of hydrogenated polysilicon TFTswith low temperature oxidation of polychannel

In this letter, a short time low temperature oxidation of poly-Si channel has been studied to suppress the photoexcited current of the hydrogenated poly-Si TFTs. The effect of the treatment, which contains different-time oxidation and different-time post-hydrogenation, on the dark-current and photocurrent of poly-Si TFTs under off state were investigated in detail. An optimal combination of both technologies has been proposed according to the investigation. The poly-Si TFTs treated with the optimal process can be operated well under a high illumination environment     

Fabrication of high-mobility p-channel poly-Si thin filmtransistors by self-aligned metal-induced lateral crystallization

High-mobility p-channel poly-Si TFTs were fabricated using a new low-temperature process (⩽500°C): self-aligned metal-induced lateral crystallization (MILC). With a one-step annealing at 500°C, activation of dopants in source/drain/gate a-Si films as well as the crystallization of channel a-Si films was achieved. The TFTs showed a threshold voltage of -1.7 V, and an on/off current ratio of ~10⁷ without post-hydrogenation. The mobility was measured to be as high as 90 cm²/V·s, which is two to three times higher than that of the poly-Si TFTs fabricated by conventional solid-phase crystallization at around 600°C     

镍硅化物诱导横向晶化制备高性能多晶硅薄膜晶体管

提出一种新的采用镍硅化物作为种子诱导横向晶化制备低温多晶硅薄膜晶体管的方法。分别采用微区Raman、原子力显微镜和俄歇电子能谱对制备的多晶硅薄膜进行结构和性能表征,并以此多晶硅薄膜为有源层制备了薄膜晶体管,测试其I-V转移特性。测试结果显示,制备的多晶硅薄膜具有较低的金属污染和较大的晶粒尺寸,且制备的多晶硅薄膜晶体管具有良好的电学特性,可以有效地减小漏电流,同时可提高场效应载流子迁移率。这主要是由于多晶硅沟道区中镍含量的有效降低使得俘获态密度减少。     

TiSi_2/N~+-poly Si/SiO_2/Si MOS结构的电学特性

<正> 一、 引言 随着半导体器件向微小型化发展,电路的速度与栅极和互连材料密切相关。目前应用较广的多晶硅栅技术具有自对准形成源漏区、低阈值电压、高温热稳定性好等优点。但多晶硅的电阻率较高,严重影响了电路速度的提高。在多晶硅上生长一层具有高电导率的TiSi_2薄膜取代多晶硅作为栅电极,可以有效地克服多晶硅电阻率高的缺点,提高电路速度。 本实验采用NH_3等离子体增强热退火,使Ti/poly Si固相反应形成TiSi_2,同时表面形成一层很薄的TiN。TiN被证明是一层良好的扩散阻挡层。通过对TiN/TiSi_2复合薄膜的薄层电阻测试和MOS高频C—V测试,证明这种方法是可行的。     

多晶硅薄膜晶体管的表面氮钝化技术

采用N2O和NH3等离子钝化技术对多晶硅薄膜表面和栅氧表面进行了钝化处理。实验结果表明,该技术能有效降低多晶硅薄膜的界面态密度,提高多晶硅薄膜晶体管性能,二次离子质谱分析表明在p-Si/SiO界面有氮原子富积,说明生成了强的Si-N键。     

Fabrication of Poly—Si TFT by Al—induced Lateral Crystallization at Low Temperature

Using a new low-temperature process (<600 ℃), the poly-Si TFT was fabricated by metal-induced lateral crystallization (MILC). An ultrathin aluminum layer was deposited on a-Si film and selectively formed by photolithography. The films were then annealed at 560 ℃ to obtain laterally crystallized poly-Si film, which is used as the channel area of a TFT. The poly-Si TFT showed an on/off current ratio of higher than 1×10 6 at a drain voltage of 5 V. The electrical properties are much better than TFT fabricated by conventional crystallization at 600 ℃.     

Thin-film transistors fabricated with poly-Si films crystallized atlow temperature by microwave annealing

Solid phase crystallization of amorphous silicon films for poly-Si thin film transistors (TFTs) has advantages of low cost and excellent uniformity, but the crystallization temperature is too high. Using a microwave annealing method, we lowered the crystallization temperature and shortened the crystallization time. The complete crystallization time at 550°C was within 2 h. The device parameters of TFTs with the poly-Si films crystallized by microwave annealing were similar to those of TFTs with the poly-Si films crystallized by conventional furnace annealing. The new crystallization method seems attractive because of low crystallization temperature, short crystallization time, and comparable film properties     

掺砷多晶硅特性研究

用ＬＰＣＶＤ方法生长了掺Ａｓ多晶Ｓｉ薄膜，通过能谱分析，扩展电阻测量，扫描电子显微镜观测，发现用ＬＰＣＶＤ方法生长的掺Ａｓ多晶Ｓｉ可获得极高的掺Ａｓ浓度，Ａｓ对衬底材料（ＳｉＯ２或多晶Ｓｉ）具有超常的低温快扩散特性，掺Ａｓ多晶Ｓｉ经高温退火，晶粒大小有反常的变化。利用这些特性可成功地解决ＬＰＣＶＤ法生长掺Ａｓ多晶Ｓｉ所遇到的生长速度愈来愈慢，Ａｓ浓度愈来愈高，难以生长较厚掺Ａｓ多晶Ｓｉ等问题。     

Improvement of electron emission efficiency and stability bysurface application of molybdenum silicide onto gated poly-Si fieldemitters

As an approach to improve electron field emission and its stability, molybdenum (Mo) silicide formation on n⁺ polycrystalline silicon (poly-Si) emitters has been investigated. Mo silicide was produced by direct metallurgical reaction, namely, deposition of Mo and subsequent rapid thermal annealing. The surface morphologies and emission properties of Mo-silicided poly-Si (Mo-polycide) emitters have been examined and compared with those of poly-Si emitters. While anode current of 0.1 μA per tip could be obtained at the gate voltage of 82 V from poly-Si emitters, the same current level was measured at 72 V from Mo-polycide emitters. In addition, the application of Mo silicide onto poly-Si emitters reduced the emission current fluctuation considerably. These results show that the polycide emitters can have potential applications in vacuum microelectronics to obtain superior electron emission efficiency and stability     

Reduction of Threshold Voltage by Diffusion Control Technique in p-MISFETs Using Poly-Si/TiN/HfSiON Gate Stacks

The effects of the diffusion control technique by inserting physical vapor deposition (PVD)-TiN film between poly-Si and CVD-TiN films on the properties of p-MISFETs using poly-Si/TiN/HfSiON gate stacks have been studied. This insertion was effective in suppressing the diffusion of Si from poly-Si to HfSiON and was able to reduce the V_th value by 0.12 V while keeping the equivalent oxide thickness and S value constant, when the thicknesses of the PVD and CVD-TiN films were 10 and 5 nm, respectively. Although too much ion implantation of fluorine into the substrate deteriorates S value and I_ON, it was verified that this diffusion control technique, in conjunction with a moderate substrate fluorine implantation, provided a reduction of V_th in pMIS without a deterioration of I_ON.