Recursive Receiver Down-Converters With Multiband Feedback and Gain-Reuse

Receiver down-converter topologies are presented that provide simultaneous frequency conversion and baseband amplification within a mixer, in order to reduce power dissipation for a given dynamic range. The down-converted IF output of a mixer is reapplied to its input stage in a recursive manner, which significantly enhances the conversion gain, with current requirement determined primarily by the input transconductor of the mixer. Two down-converter topologies based on this technique are presented. One topology utilizes common-source NMOS devices as the RF input stage of the mixer, and reuses their transconductance for providing baseband gain. The second topology utilizes differential pairs as the RF input stage, and employs the transconductance of the tail current-source devices for baseband gain. The designs are implemented in a 0.13 mum CMOS technology and achieve peak conversion gains of 50 dB and 56 dB, with single side-band noise figures of 12.7 dB and 9.4 dB, and OIP3 values of 8 and 11 , respectively. They operate at a nominal supply of 1.2 V with bias current of 2.9 mA and 2.1 mA, respectively. The active die area is less than 0.1 mm for each design. Noise and linearity performance of the down-converters is analyzed, and the potential for enhancement of IIP3 through cancellation of nonlinear products is discussed.     

一种基于动态阈值NMOS的1.2 V CMOS模拟乘法器

分析了以动态阈值NMOS晶体管作为输入信号的输入晶体管,利用4个动态阈值NMOS和2个有源电阻设计和实现的一种1.2 V低功耗CMOS模拟乘法器电路。该电路具有节省输入晶体管数目、偏置晶体管和偏置电路,以及性能指标优良的特点。其主要参数指标达到:一、三次谐波差值40 dB,输出信号频带宽度375 MHz,平均电源电流约30 μA,动态功耗约36 μW。可直接应用于低功耗通信集成电路设计。     

A low voltage CMOS RF front-end for IEEE 802.11b WLAN transceiver

A low voltage CMOS RF front-end for IEEE 802.11b WLAN transceiver is presented. The problems to implement the low voltage design and the on-chip input/output impedance matching are considered, and some improved circuits are presented to overcome the problems. Especially, a single-end input, differential output double balanced mixer with an on-chip bias loop is analyzed in detail to show its advantages over other mixers. The transceiver RF front-end has been implemented in 0.18 um CMOS process, the measured results show that the Rx front-end achieves 5.23 dB noise figure, 12.7 dB power gain (50 ohm load), −18 dBm input 1 dB compression point (ICP) and −7 dBm IIP3, and the Tx front-end could output +2.1 dBm power into 50 ohm load with 23.8 dB power gain. The transceiver RF front-end draws 13.6 mA current from a supply voltage of 1.8 V in receive mode and 27.6 mA current in transmit mode. The transceiver RF front-end could satisfy the performance requirements of IEEE802.11b WLAN standard. Supported by the National Natural Science Foundation of China, No. 90407006 and No. 60475018.     

Indium gallium arsenide microwave power transistors

Depletion-mode InGaAs microwave power MISFETs with 1-μm gate lengths and up to 1-mm gate widths have been fabricated using an ion-implanted process. The devices employed a plasma-deposited silicon/silicon dioxide gate insulator. The DC current-voltage (I -V) characteristics and RF power performance at 9.7 GHz are presented. The output power, power-added efficiency, and power gain as a function of input power are reported. An output power of 1.07 W at 9.7 GHz with a corresponding power gain and power-added efficiency of 4.3 dB and 38%, respectively, was obtained. The large-gate-width devices provided over twice the previously reported output power for InGaAs MISFETs at X-band. In addition, the first report of RF output stability of InGaAs MISFETs over 24 h period is also presented. An output power stability within 1.2% over 24 h of continuous operation was achieved. In addition, a drain current drift of 4% over 10⁴ s was obtained     

A Wideband CMOS Low Noise Amplifier Employing Noise and IM2 Distortion Cancellation for a Digital TV Tuner

A wideband CMOS low noise amplifier (LNA) with single-ended input and output employing noise and IM2 distortion cancellation for a digital terrestrial and cable TV tuner is presented. By adopting a noise canceling structure combining a common source amplifier and a common gate amplifier by current amplification, the LNA obtains a low noise figure and high IIP3. IIP2 as well as IIP3 of the LNA is important in broadband systems, especially digital terrestrial and cable TV applications. Accordingly, in order to overcome the poor IIP2 performance of conventional LNAs with single-ended input and output and avoid the use of external and bulky passive transformers along with high sensitivity, an IM2 distortion cancellation technique exploiting the complementary RF performance of NMOS and PMOS while retaining thermal noise canceling is adopted in the LNA. The proposed LNA is implemented in a 0.18 $muhbox{m}$ CMOS process and achieves a power gain of 14 dB, an average noise figure of 3 dB, an IIP3 of 3 dBm, an IIP2 of 44 dBm at maximum gain, and S11 of under ${- 9}~{rm dB}$ in a frequency range from 50 MHz to 880 MHz. The power consumption is 34.8 mW at 2.2 V and the chip area is 0.16 ${rm mm}^{2}$.      

A low-voltage ultra-wideband down-conversion mixer with improved power conversion gain

This article presents a wideband mixer using a TSMC 0.18?µm complementary metal-oxide semiconductor technology process for ultra-wideband (UWB) system applications. The measured 3-dB radio frequency (RF) bandwidth is from 3 to 8.4?GHz with an intermediate frequency of 10?MHz. The measurement results of the proposed mixer achieve 8.1?dB average power conversion gain ?5?dBm input third-order intercept point (IIP3) at 7.4?GHz and 12.4–13.3?dB double side band noise figure. The total dc power consumption of this mixer including output buffers is 3.18?mW from a 1?V supply voltage. The output current buffer consumption is about 2.26?mW with an excellent local oscillator-RF isolation of up to 40?dB at 5?GHz. The article presents a mixer topology that is greatly suitable for low-power operation in UWB system applications.     

一种16位1 GS/s电流舵型DAC的设计

设计了一种基于UMC 0.18μm CMOS工艺的16位1GS/s的电流舵型D/A转换器。该DAC采用7+4+5分段结构,1.8V/3V双电源供电,满摆幅输出电流为20mA。采用四开关结构、限幅开关驱动电路、两个cascode管的单位电流源以及两层结构的逻辑译码器,实现了优异的性能。在1GHz采样率、101.07MHz输入信号下,无杂散动态范围(SFDR)达到78.06dB。     

应用于无线传感器网络的功率放大器的设计

给出一种基于TSMC 0.18 μm RF CMOS工艺,应用于无线传感器网络的2.4 GHz 功率放大器的设计.该功率放大 器工作频率范围为2.4 GHz～2.4835 GHz,采用全差分AB类共源共栅电路结构,使用功率控制技术以节省功耗,当输入信号 功率-12.5 dBm时,输出功率在-10.4 dBm至5.69 ...     

一种PWM/PFM的同步整流升压转换器设计

文章介绍了一种工作在PWM/PFM双模式下的同步整流升压转换器设计,剖析电路的工作原理,采用0.35μmn阱CMOS工艺流片。通过SPECTRE仿真器模拟,结果显示该电路在输出负载电流是1mA时,输入电源电压0.9V启动,在关机模式下静态电流小于1μA,输出电压调节范围2.5V～5V,输入电压1V～5V,固定频率1.4MHz,允许采用外形扁平而小巧的电感器和陶瓷电容器,从而极大地节省了PCB板的面积,效率高达92%,可以从单节AA电池产生3.3V/260mA的输出或从双节AA电池产生3.3V/600mA的输出。该器件包括驱动管NMOS和同步整流管PMOS,具有斜率补偿的电流模式PWM设计,减少了外部元件的数量。抗振铃电路通过在不连续工作模式下对电感器进行阻尼来抑制EMI。在轻负载情况下工作在PFM模式,重负载情况下工作在PWM模式。     

一种用于GPS接收机的低噪声放大器

针对GPS接收机低功耗、低噪声、高增益的要求,采用功率限制下噪声匹配技术、阻抗匹配技术和电源复用技术,设计了一款可应用于GPS接收机的单端输入差分输出低噪声放大器,减少了巴伦损耗。采用SMIC 0.13 SymbolmAm CMOS RF工艺和全定制集成电路设计方法,工作频率为1575 GHz,对电路进行版图后仿真。仿真结果表明,该低噪声放大器在1.2 V电源电压下,功耗为4.8 mW,增益为22.65 dB,噪声系数为1.388 dB。     

An enhanced slew rate source follower

A unity-gain buffer capable of high slew rates in both the positive and negative directions is presented. By sensing the drain current of the common-drain device in an NMOS source follower, the extent of slewing is detected, and the tail current of the source follower is dynamically adjusted. A buffer incorporating this strategy was implemented in a 2 μm p-well process. This buffer has over 4 times the negative-going slew rate and twice the bandwidth of a source follower, while requiring only 13% more static power. Moreover, the output voltage swing range is as large as that of a source follower. With a 20 pF output load, the measured 3-dB bandwidth was 9 MHz. The signal-to-total-harmonic-distortion ratio with 2 V_p-p sinewave input at a frequency of 2 MHz was better than 50 dB     

A 90–96 GHz CMOS down-conversion mixer with high conversion gain and excellent LO–RF isolation

A 90–96 GHz down-conversion mixer for 94 GHz image radar sensors using standard 90 nm CMOS technology is reported. RF negative resistance compensation technique, i.e. NMOS LC-oscillator-based RF transconductance (GM) stage load, is used to increase the output impedance and suppress the feedback capacitance C_gd of RF GM stage. Hence, conversion gain (CG), noise figure (NF) and LO–RF isolation of the mixer can be enhanced. The mixer consumes 15 mW and achieves excellent RF-port input reflection coefficient of ?10 to ?36.4 dB for frequencies of 85–105 GHz. The corresponding -10 dB input matching bandwidth is 20 GHz. In addition, for frequencies of 90–96 GHz, the mixer achieves CG of 6.3–9 dB (the corresponding 3-dB CG bandwidth is greater than 6 GHz) and LO–RF isolation of 40–45.1 dB, one of the best CG and LO–RF isolation results ever reported for a down-conversion mixer with operation frequency around 94 GHz. Furthermore, the mixer achieves an excellent input third-order intercept point of 1 dBm at 94 GHz. These results demonstrate the proposed down-conversion mixer architecture is very promising for 94 GHz image radar sensors.     

基于中和电容的60 GHz CMOS功率放大器设计

功率放大器（Power Amplifier, PA）是射频前端重要的模块,本文基于SMIC 55 nm RF CMOS 工艺,设计了一款60 GHz 两级差分功率放大器。针对毫米波频段下,硅基CMOS晶体管栅漏电容（Cgd）严重影响放大器的增益和稳定性的问题,采用交叉耦合电容中和技术抵消Cgd影响。通过优化级间匹配网络和有源器件参数,提高了功率放大器的输出功率,增益和效率。后仿结果显示,在1.2V的供电电压下,工作在60 GHz的功率放大器饱和输出功率为11.3 dBm,功率增益为16.2 dB,功率附加效率为17.0%,功耗为62 mW。芯片面积380×570 um2 。     

Combined Linear and $Delta$-Modulated Switch-Mode PA Supply Modulator for Polar Transmitters

A combined linear and delta-modulated (DeltaM) switch-mode PA supply modulator for polar transmitters in wireless handsets is designed in a 0.25 mum CMOS process. The modulator employs a DeltaM switch-mode DC-DC buck converter to enhance the efficiency of a linear regulator at backed-off supply voltages and powers. The delta-modulator's noise-shaping characteristic, linear regulator's power supply rejection, digital pre-emphasis of the input envelope, and a closed-loop amplitude path from the PA output are simultaneously used to achieve state-of-the-art modulator performance. The presented supply modulator follows the input signal's envelope with 20 dB output dynamic range, maximum efficiency of 75.5% at an output power of 30.8 dBm, and 75 dB SFDR for envelope signals up to 4 MHz occupied RF bandwidth. For a 1625 kb/s 8 PSK RF input signal at 900 MHz, polar modulation of a commercial low-power GSM-900 PA provides 10 dB ACPR improvement.     

A single-input dual-output 13.56 MHz CMOS AC–DC converter with comparator-driven rectifiers for implantable devices

A highly efficient single-input, dual-output AC–DC converter for wireless power transfer in implantable devices is implemented using the 0.18-µm CMOS process. The proposed AC–DC converter, consisting of three rectifiers with cross-coupled NMOS transistors and comparator-driven PMOS transistors, achieves up to 79.5% power conversion efficiency at 13.56 MHz operation frequency in order to provide dual outputs of 1.2 V and 2.2 V DC voltages along with 6.2 mA and 22.6 mA of current, respectively, to the implant device from a single RF input. The designed IC consumes a core die area of 0.18 mm².     

用于射频SOC芯片的低噪声高电源抑制比LDO

设计了一种能够为射频芯片提供低噪声、高PSRR、全集成LDO.采用SMIC 0.18μmRF工艺实现,芯片有效面积0.11 mm2.测试结果表明:当输出电流从0跳变为20 mA时,最大Ripple 为100 mV,稳定时间2μs;当输出电流为20mA,频率到1 MHz的情况下,PSRR＜-30 dB;从1～100 kH...     

下一代移动通信LTE中功率放大器芯片设计

基于0.18μm SiGe BiCMOS工艺,设计了一种应用于下一代移动通信3GPP LTE TDD2.6 GHz频段(Band38)的射频功率放大器(PA)芯片。射频功率放大器采用共发射极3级级联的全差分结构,提高了输出电压摆幅,减小了功率晶体管的集电极电流,且降低了寄生的键合线电感。在预放大级和中间放大级、功率级中分别设计了电阻偏置和有源偏置两种偏置电路以提高线性度性能,并通过MOS开关管实现功率控制功能。测试结果表明:在2.57～2.62 GHz工作频段内,正向增益S21大于30.5 dB,输入回波损耗S11和输出回波损耗S22分别均小于-13 dB,功率增益大于31 dB,输出1 dB压缩点功率达28.6 dBm,功率附加效率为18%。     

应用于IEEE 802.11b无线局域网系统的2.4GHzCMOS单片收发机射频前端

实现了一个应用于IEEE 802.11b无线局域网系统的2.4GHz CMOS单片收发机射频前端,它的接收机和发射机都采用了性能优良的超外差结构.该射频前端由五个模块组成:低噪声放大器、下变频器、上变频器、末前级和LO缓冲器.除了下变频器的输出采用了开漏级输出外,各模块的输入、输出端都在片匹配到50Ω.该射频前端已经采用0.18μm CMOS工艺实现.当低噪声放大器和下变频器直接级联时,测量到的噪声系数约为5.2dB,功率增益为12.5dB,输入1dB压缩点约为-18dBm,输入三阶交调点约为-7dBm.当上变频器和末前级直接级联时,测量到的噪声系数约为12.4dB,功率增益约为23.8dB,输出1dB压缩点约为1.5dBm,输出三阶交调点约为16dBm.接收机射频前端和发射机射频前端都采用1.8V电源,消耗的电流分别为13.6和27.6mA.     

A Common Source Input Cross Coupled Quad CMOS Mixer*

A CMOS doubly balanced mixer circuit is implemented with a source follower input and a cross coupled mixing quad. The circuit employs an all N-channel configuration and is suitable for high frequency applications. As a down-converter with an RF input of 2.0 GHz and an IF output of 200 MHz, the mixer demonstrates 9 dB of conversion loss with a corresponding input referred third order intercept of 0 dBm. As an up-converter with an IF input frequency of 400 MHz and an RF output of 2.4 GHz, the mixer demonstrates 14 dB of conversion loss.     

2～12 GHz CMOS超宽带低噪声放大器设计

提出了一种基于双反馈电流复用结构的新型CMOS超宽带(UWB)低噪声放大器(LNA),放大器工作在2～12 GHz的超宽带频段,详细分析了输入输出匹配、增益和噪声系数的性能。设计采用TSMC 0.18μm RF CMOS工艺,在1.4 V工作电压下,放大器的直流功耗约为13mW(包括缓冲级)。仿真结果表明,在2～12 GHz频带范围内,功率增益为15.6±1.4 dB,输入、输出回波损耗分别低于-10.4和-11.5 dB,噪声系数(NF)低于3 dB(最小值为1.96 dB),三阶交调点IIP3为-12 dBm,芯片版图面积约为712μm×614μm。