Threshold voltage instability characteristics of HfO2 dielectrics n-MOSFETs

In this paper, the threshold voltage instability characteristics of HfO₂ high-k dielectric are discussed. The results from various stress bias conditions including DC and AC with variations of frequency, duty cycle, and polarity provide additional insights into the intrinsic behavior and the trapping dynamics of high-k materials. A reduced threshold voltage shift was observed at higher frequency and lower duty cycle under AC positive unipolar stress compared to DC stress. Similarly, the degradation of maximum transconductance was also reduced with AC stress. However, subthreshold swing changes were found to be negligible and fairly independent of stress frequencies and duty cycles under AC positive unipolar stress.When different polarity of stress, such as positive, negative, and bipolar stress was applied, it was observed that frequency and duty cycle dependencies were still valid in all three conditions. In contrast to positive stress, negative stress showed a decrease in the threshold voltage shift. Bipolar stress resulted in the highest threshold voltage instability, but the degradation in transconductance and subthreshold swing was actually smaller than those in negative unipolar stress. The bulk trap of HfO₂ dielectric, which is proportional to its physical thickness, is believed to be the primary factor for threshold voltage shift. AC unipolar operation would allow a higher 10-year lifetime operating voltage than the DC condition. In addition to experimental results, a plausible mechanism has been proposed.     

Comparison of La-based high-k dielectrics: HfLaSiON and HfLaON

For the first time, we present a comparative study on HfLaSiON and HfLaON gate dielectric with an equivalent oxide thickness (EOT) of 0.8 nm (T_inv = 1.2 nm). A detailed DC analysis of I_on vs. I_off shows HfLaON performs somewhat better than HfLaSiON. However, positive bias temperature instability (PBTI) lifetime of HfLaSiON is higher than HfLaON by about 2 orders of magnitude. On the other hand, hot carrier stress lifetime for HfLaSiON was similar to that of HfLaON. From the activation energy and U-trap, we found that the cause of different threshold voltage (V_T) shifts under PBT stress and detrapping was originated from stable electron traps induced by different charge trapping rates.     

Low-temperature degradation studies of AlGaAs/GaAs modulation-doped field effect transistors

The degradation of AlGaAs/GaAs modulation-doped field effect transistors (MODFETs) was studied at the low temperature of 77 K. The MODFETs were stress tested at 77 K under both short- and long-term bias stress conditions. The measured MODFET parameters include threshold voltage V_t, transconductance g_m and the gate voltage V_u at which g_m shows a maximum. Shifts of V_t, g_m and V_u were studied as a function of stress voltage and stress time. The measured shifts are found to depend on (V_g − V_d) which indicates the influence of hot electrons coming from the high mobility channel. The MODFETs were also tested for temperature cycling between 300 and 77 K up to 20 cycles. Some changes of device properties at 77 K were observed.     

The influence of visible light on the gate bias instability of In-Ga-Zn-O thin film transistors

We investigated the effect of photon irradiation with various energies on the gate bias instability of indium-gallium-zinc oxide transistors. The illumination of red and green light on the transistor caused positive threshold voltage (V_th) shifts of 0.23 V and 0.18 V, respectively, while it did not affect the V_th value in blue light after a positive bias stress. However, the stability of transistors was deteriorated with increasing photon energy after a negative bias stress: negative V_th shifts for red (−0.23 V) and blue light (−3.7 V). This difference can be explained by the compensation effect of the electron carrier trapping and the creation of meta-stable donors via photon excitation.     

Effect of plasma process-induced damage on bias temperature instability of MOSFETs

For a surface-channel n-MOSFET and a buried-channel p-MOSFET, the effect of plasma process-induced damage on bias temperature instability (BTI) was investigated. The gate oxide thickness, t_ox, of the test MOSFETs was 2.0, 3.0, or 4.5 nm. The shifts of threshold voltage V_th and of linear drain current I_dlin were measured after applying a BTI stress at a temperature of 125 °C. The measured shifts of V_th and I_dlin indicate that BTI on ultra-thin gate CMOS devices appears only in the form of SiO₂/Si interface degradation, and that the positive BTI for the n-MOSFET as well as the negative BTI for the p-MOSFET is important for the reliability evaluation of CMOS devices. Because of positive plasma charging to the gate, a protection diode was very efficient at reducing BTI for the p-MOSFET, but it was much less effective for the n-MOSFET.     

Temperature and bias investigation of self heating effect and threshold voltage shift in pHEMT's

In the present work we analyze the performance of power pseudomorphic HEMT's having scaled gate widths (300, 600, 900 μm) under a wide range of bias and temperature conditions to investigate the onset of an hot electron regime. These devices exhibit a negative slope of I_D with respect to V_DS and a subsequent negative differential resistance under high power dissipation conditions. This reduction in the drain current can be explained by a degradation of the carrier velocity in the two dimensional electron gas due to the self-heating effect.The output I−V characteristics of our devices are also affected by the threshold voltage shift. It results that the threshold voltage increases linearly by decreasing the temperature. This threshold voltage shift causes a decrease of the transconductance when the devices is biased closer to the pinch-off. Consequently, the forward transmission parameter S₂₁ at microwaves shows a degradation at lower temperatures despite the fact that the transport properties improve upon cooling.     

Threshold voltage instability at low temperatures in partiallydepleted thin-film SOI MOSFETs

A threshold voltage instability phenomenon at low temperatures in partially depleted thin-film silicon-on-insulator (SOI) SIMOX (separation by implantation of oxygen) MOSFETs is reported. This phenomenon was investigated under normal MOSFET operating conditions for temperatures ranging from 300 K down to 10 K, with both the magnitude and duration of the instability observed to be strongly dependent on temperature. Threshold voltage shifts as small as 0 V at room temperature and as large as 0.29 V at 10 K are reported. The duration of the instability ranged in the tens of minutes and was observed to increase as the temperature was decreased     

A CMOS threshold voltage reference source for very-low-voltage applications

This paper describes a CMOS voltage reference that makes use of weak inversion CMOS transistors and linear resistors, without the need for bipolar transistors. Its operation is analogous to the bandgap reference voltage, but the reference voltage is based on the threshold voltage of an nMOS transistor. The circuit implemented using 0.35 μm n-well CMOS TSMC process generates a reference of 741 mV under just 390 nW for a power supply of only 950 mV. The circuit presented a variation of 39 ppm/°C (after individual resistor trimming) for the −20 to +80 °C temperature range, and produced a line regulation of 25 mV/V for a power supply of up to 3 V.     

Damages of Ge devices by 2-MeV electrons and their recovery

The degradation and recovery behavior of the device performance of Ge diodes and p-Ge MOSFETs irradiated by 2-MeV electrons are studied. For diodes, it is noted that both the reverse and forward current increase after irradiation. However, an interesting observation is that the forward current decreases after irradiation for a forward voltage larger than ∼0.7 V. This reduction can be explained by an increased resistivity of the n-well in the germanium substrate. For the transistors, after irradiation, a slight negative shift of the threshold voltage and a decrease of the drain current input and output characteristics have been observed together with a decrease of the hole mobility. This is mainly due to the increase of the absolute value of the threshold voltage induced by positive charges in the gate oxide. The degradation recovers by thermal annealing after irradiation. For 1 × 10¹⁷ e/cm², the diode performance almost completely recovers to the initial condition after a 250 °C annealing and the anneal process is characterized by an activation energy of 0.59 eV. For transistor irradiated to 5 × 10¹⁷ e/cm², the device performance also recovers but with an activation energy of 0.33 eV.     

脉冲应力增强的NMOSFET's热载流子效应研究

 本文研究了交流应力下的热载流子效应,主要讨论了脉冲应力条件下的热空穴热电子交替注入对NMOSFET's的退化产生的影响.在脉冲应力下,阈值电压和跨导的退化增强.NMOSFET's在热空穴注入后,热电子随后注入时,会有大的退化量,这可以用中性电子陷阱模型和脉冲应力条件下热载流子注入引起的栅氧化层退化来解释.本文还定量分析研究了NMOSFET's退化与脉冲延迟时间和脉冲频率的关系,并且给出了详细的解释.在脉冲应力条件下,器件的热载流子退化是由低栅压下注入的热空穴和高栅压下热电子共同作用的结果.     

A mechanism of threshold voltage changes for WNx gate GaAs MESFETs in high temperature storage life tests

Reliability of 0.8 μm WN_x gate GaAs MESFETs with a self-aligned lightly doped drain structure has been investigated by means of high temperature storage life tests at 250, 275 and 300 °C. The observed reduction in threshold voltage followed by drain current increase was just reverse in contrast to those for ‘gate sinking’ effect reported on several Au-based gates. The correlation of the threshold voltage reduction with Shottky barrier height and other MESFET parameter changes during the tests suggested a model related to the short channel effect for the threshold voltage reduction, which was proved true by submitting samples of gate lengths 0.7, 1.0 and 1.5 μm to high temperature storage life tests. The dependence of threshold voltage changes on gate orientation relative to the crystal axis was also evaluated with 1.0 μm gate MESFETs to investigate the model in more detail. MESFETs parallel to [001] axis showed minimum absolute threshold voltage changes, while those parallel to piezoelectrically active [011] and [0 1] axes showed decreasing and increasing threshold voltage changes, respectively. From these results, the threshold voltage changes were tentatively ascribed to the relief of the stress caused by poly-imide die bonding process for packaging MESFET chips. In other words, WN_x gate GaAs MESFET chips themselves were concluded to show no appreciable degradation up to 1000 hr storage life tests at 250 and 275 °C, except for ohmic contact degradation at 300 °C.     

Functional Pixel Circuits for Elastic AMOLED Displays

While fabrication of active matrix organic LED (AMOLED) displays on plastic substrates continues to face technological challenges, stable electrical operation of thin-film transistor (TFT) pixel circuits under mechanical stress induced by substrate bending remains a critical issue. This paper investigates strain-induced shifts in hydrogenated amorphous silicon TFT characteristics and the compound impact on TFT circuit behavior. Measurements show that the magnitude of the shifts is determined by the direction of current flow in the TFT with respect to the bending stress orientation as well as bias conditions. Physically based compact models are developed that relate device characteristics to material behavior for design and optimization of AMOLED pixel circuits that can maintain immunity to bending stress. In particular, current mirror-based pixel circuits are presented that compensate for the long term threshold voltage shift and instantaneous strain-induced shifts in device characteristics.     

Reliability analysis of MOS varactor in CMOS LC VCO

The paper investigates the reliability of MOS varactor tuned voltage-controlled oscillators (VCO). Due to the stress induced threshold voltage shift of the MOS varactor, the resonant tank degrades and the center frequency and phase noise of VCO deviate. The behavior is modeled and an adaptive body biasing scheme is proposed to make VCO resilient to reliability. In the mean time it does not degrade the VCO performance. An LC VCO at 24 GHz carrier frequency with adaptive body biasing is compared with VCO without such biasing design in PTM 65 nm technology. The ADS simulation results show that the biasing design helps improve the robustness of the VCO in resonant frequency. The design reduces the frequency sensitivity of VCO by 20% when subjected to threshold voltage degradation.     

Extensive investigations of temperature influence on barrier integrity during reliability testing

Investigation of stress migration phenomena is one of the key aspects to characterize metallization reliability. Typical test methodologies are investigations of resistance shifts at wafer-level or package-level temperature storage tests under a temperature range between 150 °C and 275 °C. During these tests a very limited resistance increase dependent on the test structure is allowed. Most recently we encounter unusual resistance shift at the highest stress temperature which did not yield classical stress voiding detectable by failure analysis. We found changes in barrier integrity explaining the resistance shift by barrier oxidization. This has been verified by specially prepared material as well as extensive failure analysis investigation.     

AlGaN/GaN High Electron Mobility Transistor degradation under on- and off-state stress

AlGaN/GaN High Electron Mobility Transistors (HEMTs) with various gate lengths have been step-stressed under both on- and off-state conditions. On-state, high power stress tests were performed on 0.17 μm gate length HEMTs and a single 5 μm spaced TLM pattern. Significant degradation of the submicron HEMTs as compared to the excellent stability of the TLM patterns under the same stress conditions reveal that the Schottky contact is the source of degradation. Off-state stress showed a linear relationship between the critical degradation voltage and gate length, though two dimensional ATLAS/Blaze simulations show that the maximum electric field is similar for all gate lengths. Additionally, as the drain bias was increased, the critical voltage decreased. However, the cumulative bias between the gate and drain remained constant, further indicating that the electric field is the main mechanism for degradation.     

Comparison of radio frequency physical vapor deposition target material used for LaOx cap layer deposition in 32 nm NMOSFETs

The MOSFET gate length reduction down to 32 nm requires the introduction of a metal gate and a high-K dielectric as gate stack, both stable at high temperature. Here we use a nanometric layer of Lanthanum to shift the device threshold voltage from 500 mV. Because this layer plays a key role in the device performance and strongly depends on its deposition process, we have compared two LaO_x deposition methods in terms of physical properties and influence on electrical NMOS device parameters. Chemical characterizations have shown a different oxidization state according to Lanthanum thickness deposited. It has been related to threshold voltage shift and gate leakage current variations on NMOS transistors. Furthermore mobility extractions have shown that Lanthanum is a cause of mobility degradation.     

Low voltage CCD image sensor with optimized reset operation

A charge coupled device (CCD) image sensor operating with 3.0 V-reset has been developed using a charge injection to the gate dielectrics of a MOS structure. A DC bias generating circuit was added to the reset structure, which sets reference voltage and holds the signal charge to be detected. The generated Dc bias is added to the reset pulse to give an optimized voltage margin to the reset operation, and is controlled by adjustment of the threshold voltage of a MOS transistor in the circuit. By the pulse-type stress voltage applied to the gate, the electrons and holes were injected to the gate dielectrics, and the threshold voltage could be adjusted ranging from 0.2 to 5.5 V, which is suitable for controlling the incomplete reset operation due to the process variation. The charges trapped in the silicon nitride lead to the positive and negative shift of the threshold voltage, and this phenomenon is explained by Poole-Frenkel conduction and Fowler-Nordheim conduction. A CCD image sensor with 492(H)×510(V) pixels adopting this structure showed complete reset operation with the driving voltage of 3.0 V. The image taken with the image sensor utilizing this structure was not saturated to the illumination of 30 lux, that is, showed no image distortion.     

An ultra-low-power CMOS voltage reference generator based on body bias technique

A CMOS voltage reference, based on body bias technique, has been proposed and simulated using SMIC 0.18 μm CMOS technology in this paper. The proposed circuit can achieve a temperature coefficient of 19.4 ppm/°C in a temperature range from −20 °C to 80 °C, and a line sensitivity of 0.024 mV/V in a supply voltage range from 0.85 V to 2.5 V, without the use of resistors and any other special devices such as thick gate oxides MOSFETs with higher threshold voltage. The supply current at the maximum supply voltage and at 27 °C is 214 nA. The power supply rejection ratio without any filtering capacitor at 10 Hz and 10 kHz are −88.2 dB and −36 dB, respectively.     

AC/DC characterization of NMOS and PMOS hot-carrier-induceddegradation under AC/DC stress

The AC/DC measurements of NMOS and PMOS I_dsat shifts are compared following DC stress. The results of the I _dsat shifts are found to be the same. The AC I_dsat measurements were performed under a variety of different conditions (varying frequency, amplitude, and base level) and showed that hot-carrier-induced interfaced states are shallow and fast (<20 ns). AC versus DC stressing was also examined. In PMOS devices, pulsed drain stress was found to be generally quasi-static, while pulsed gate stress produced enhanced device degradation under certain bias conditions. In NMOS transistors AC drain stress was found to be quasi-static in strong device saturation, while AC gate stress resulted in significantly enhanced degradation. In weak device saturation, both gate and drain pulsing resulted in early catastrophic device failure     

Stability of polysilicon thin film transistors under switch operating

Ageing of low temperature polysilicon Thin Film Transistors (TFTs) under AC gate bias stress is reported in this study. The active layer of these high performances transistors is amorphous deposited using Low Pressure Chemical Vapor Deposition (LPCVD) technique. The drain and source regions are in-situ doped during the LPCVD deposition by using phosphine to fabricate n-type transistors. The active layer and the drain arid source regions are Solid Phase Crystallized. The field effect mobility is higher than 100 cm²/V.s, the subthreshold slope around 0.6 V/dec, the threshold voltage around 0.2V and the switching time around 370 nsec.As these TFTs are commonly used as switching devices in the most of applications in large area electronics field, the study of their stability under AC electrical stress is important. The present work shows that the effect of the positive or negative DC stress is higher than that of the AC stress and then the degradation of polysilicon TFTs is over-estimated when it is checked from the effects of DC gate bias stress.Degradation under bias stress is shown to originate from the creation of gap states at the channel-interface oxide and in the channel material. The lower influence of the AC stress is explained from an annealing effect of the created states by the application of an opposite sign bias stress.