VMOS—A new MOS integrated circuit technology

A new V-groove MOS integrated circuit technology (VMOS) is described. It makes use of preferential etching of silicon to define the channels of the MOS transistors. The fabrication involves either a three or four mask process and is capable of producing either silicon gate or standard metal gate transistors. The technology results in very short channel length devices using non-critical alignment tolerances. Despite the short channel length, the VMOS transistor exhibits lower output conductance and higher breakdown voltage than a standard MOS transistor.A first order theory is presented for the VMOS transistor along with measurements made on test devices of various channel lengths. Some integrated circuit applications of the technology are also presented, including an R-S fiip-flop and a 27-stage bucket brigade shift register. The advantages of the VMOS technology in such applications are discussed.     

Protective device for MOS integrated circuits

Two protective devices for MOS integrated circuits have been extensively tested and proved feasible. They also perform more reliably than conventional Zener diodes. One of them has been used in the fabrication of a dual 25-bit MOS and MNOS integrated shift register and performed reliably.     

4-µm LSI on SOS using coplanar-II process

SOS Si-gate 4-µm NMOS devices using a coplanar process (Coplanar-II process) have been investigated for the purpose of improving thé power-delay product and SOS LSI reliability. The gate breakdown field is improved by more than a factor of two (8.7 MV/cm) over that of transistors fabricated by a conventional SOS process. Two types of anomalous drain leakage currents which flow along the edge of the silicon island formed by using the conventional SOS process are suppressed. A typical drain leakage current is7 times 10^{-11}A/8 µm. The typical values of speed and power-delay product are 0.70 ns and 0.21 pJ for 4-µm channel length devices and 0.57 ns and 0.17 pJ for 3-µm devices. These values are 1.6 times faster than that of MOS/bulk due to a lack of stray capacitance in MOS/SOS. The temperature dependence of the delay time in NMOS/SOS E/D devices can be minimized by choosing the load transistor threshold voltage (VTD) to be -2.1 V. This is attributed to the higher temperature dependence of VTDthan that of MOS/bulk. The Coplanar-II process with Si-gate 4-µm NMOS/SOS is successfully applied to the fabrication of a 1300-gate LSI, RF0 (Register File 0). The circuitry has a unique register port which can be addressed from two independent ports simultaneously. In order to obtain higher speed and lower power, four kinds of threshold voltages are used. The circuits give rise to stable operation without any timing pulse such as a precharge and a higher internal access time of 25 ns in RF0, which consists of 256-bit memory and peripheral control circuit.     

A high speed bulk CMOS C/SUP 2/L microprocessor

The CDP 1802, single-chip, 8-bit microprocessor is fabricated in C/SUP 2/L, or closed COS/MOS logic, a new structural approach to high-speed bulk silicon COS/MOS logic. In this self-aligned silicon-gate CMOS technology, the gate completely surrounds the drain providing transistor aspect ratios which maximize the transconductance to capacitance ratio and thus allow high on-chip speed. Generally, standard 6-/spl mu/m channel length C/SUP 2/L devices show an improvement in packing density by a factor of 3 over standard CMOS and operate at frequencies approximately four times faster than standard CMOS. High density 5-/spl mu/m channel length devices further improve area and speed by factors up to 1.5. The fabrication sequence for C/SUP 2/L devices requires six photomasks (one less than standard CMOS).     

The bipolar transistor bucket-brigade shift register

An analysis of the bipolar transistor bucket-brigade shift-register operation is presented for comparison to other charge-transfer shift-register schemes. It is shown that incomplete charge transfer, the most important performance limiting effect for the charge-coupled device and the IGFET bucket brigade, is very small under most practical operating conditions for the bipolar transistor bucket brigade. In addition to charge loss due to finite transistor current gain h/SUB fe/ the next most important performance limitation comes from collector-emitter capacitance. It is shown that this collector-emitter capacitance leads to reduced analog time delay on transfer through the register and to signal attenuation effects similar to those resulting from incomplete charge transfer. Using the results of the analysis, experimental data reported by Sangster are discussed and a comparison of the advantages and disadvantages of the bipolar bucket-brigade register with the MOS charge-transfer registers is made.     

Shielded silicon gate complementary MOS integrated circuit

An electrostatic shield for complementary MOS integrated circuits was developed to minimize the adverse effects of stray electric fields created by the potentials in the metal interconnections. The process is compatible with silicon gate technology. n-doped polycrystalline silicon was used for all the gates and the shield. The effectiveness of the shield was demonstrated by constructing a special field plate over certain transistors. The threshold voltages obtained on a oriented silicon substrate ranged from 1.5 to 3 V for either channel. Integrated inverters performed satisfactorily from 3 to 15 V, limited at the low end by the threshold voltages and at the high end by the drain breakdown voltage of the n-channel transistors. The stability of the new structure with an n-doped silicon gate as measured by the shift inC-Vcurve under 200°C ± 20 V temperature-bias conditions was better than conventional aluminum gate or p-doped silicon gate devices, presumably due to the doping of gate oxide with phosphorous. The advantages of the new structure are: avoidance of field inversion, elimination of guard rings, and thinner and more stable oxides.     

Characterization of parasitic transistors to evaluate CMOS processuniformity

The design and fabrication of several families of parasitic transistors available in a standard CMOS process are discussed and their application to process control examined. These transistors are characterized and their extracted parameters correlated with those obtained from CMOS devices. From these correlations it is concluded that parasitic transistors are very sensitive to changes in the process that influence the performance of MOS transistors. As a result parasitic transistors can be used in conjunction with standard MOS devices and test structures to provide a more complete picture of CMOS process variation     

A CPD image sensor with an SOI structure

A CPD image sensor with an SOI (silicon-on-insulator) structure has been developed. The sensor is composed of read-out transistors fabricated on laser-recrystallized silicon, photodiodes on the seeding region, an MOS shift register, and a CCD shift register. A reproduced image with a 50 (H)×60 (V) pixel image sensor showed reduction of smear noise to a value 1/8000 times that in the bulk transistor as a result of complete isolation of the drains of the read-out transistors by oxide layers     

Direct capacitance measurements of small geometry MOS transistors

Methods for measuring the intrinsic capacitances of small geometry MOS transistors are described. The influence of short- and narrow-channel effects on the capacitance characteristics of MOS transistors is evaluated. The results are compared with long-channel devices. It is shown that the presented capacitance methods can be used to study the physics of short-channel transistors.     

A single chip radix-2 FFT butterfly architecture using parallel data distributed arithmetic

It is shown how distributed arithmetic techniques can be applied in parallel-data arithmetic computations to achieve highly regular and efficient VLSI structures on silicon. Two individual arithmetic processor chips are described as examples of the technique. The chips described, which are intended primarily for computation of the FFT butterfly, each contain the functional equivalence of two parallel pipelined multipliers. The first chip is an 8-bit prototype device which has been designed and fabricated on a standard 5-/spl mu/m silicon-gate n-channel MOS process. The second chip is a 16-bit CMOS-SOS design which uses a modified architecture to achieve higher clocking rates and improved versatility in systems use.     

Top down fabrication of long silicon nanowire devices by means of lateral oxidation

The process for the fabrication of devices based on a single silicon nanowire with a triangular section is presented and discussed. The top down fabrication process exploits the properties of silicon anisotropic etching for the realization of very regular trapezoidal structures, that can be uniformly reduced in controlled way by means of lateral oxidation. This allows the reproducible realization of nanowires smaller than 20 nm, and with a length of several micrometers, starting from relatively big structures that, even if electron beam lithography has been used in the present work, could be realized also by other (as optical) lithographic techniques. Nanowires are already placed between silicon contacts for electrical transport characterization. The process, compatible with the actual MOS technology, is suitable for a massive, large-scale production of silicon nanowire based devices and it allows a flexible platform for multigate and more complex structures and devices. The nanowire triangular section is a step toward the integration of three-dimensional devices. Electrical characteristics of silicon nanowire FETs, both p- and n-doped, will be reported and discussed.     

A 10 K-gate 950 MHz CML demonstrator circuit made with a 1-μmtrench-isolated bipolar silicon technology

A quad 512-b static shift register consuming 1.8 mW/stage designed to demonstrate the capabilities of an advanced bipolar silicon technology is discussed. The process uses 1-μm lithography, trench isolation, polyemitter transistors, polysilicon resistors, and polycide layer for local interconnections. This VLSI circuit (over 35 K transistors, 86-mm² chip) has been implemented on a sea-of-cells structure. An appropriate scheme has been used for the clock distribution. The experimental results show operation at a clock frequency up to 950 MHz     

Charge-coupled structures with self-aligned submicron gaps

A technique for fabricating charge-coupled devices with submicron gaps is described. The method relies on a "shadowing" effect produced by oblique deposition of the metal in an otherwise standard vacuum evaporation process. The biggest advantage of the technique is its extreme simplicity, particularly for one-dimensional CCD structures. The feasibility of the technique has been demonstrated for two-and three-phase devices; the two-phase structure was a 32-bit shift register which has been operated at up to 10 MHz. With some additional processing, the technique can be used to make bidirectional CCD arrays as required in area imagers and serpentine shift registers.     

Fundamental limitations in microelectronics—I. MOS technology

The physical phenomena which will ultimately limit MOS circuit miniaturization are considered. It is found that the minimum MOS transistor size is determined by gate oxide breakdown and drain-source punch-through. Other factors which limit device size are drain-substrate breakdown, drain ‘corner’ breakdown and substrate doping fluctuations. However these limitations are less severe than the oxide breakdown limitation mentioned above. Power dissipation and metal migration limit the frequency and/or packing density of fully dynamic and of complementary MOS circuits. In static non-complementary circuits, power dissipation is the principal limitation of the number of circuit functions per chip. The channel length of a minimum size MOS transistor is a factor of 10 smaller than that of the smallest present day devices. The tolerances required to manufacture such a transistor are compatible with electron beam masking techniques. It is thus possible to envision fully dynamic silicon chips with up to 10⁷–10⁸ MOS transistors per cm².     

MOS device fabrication using sputter-deposited gate oxide and polycrystalline silicon layers

For applications in the MOS device fabrication the interface properties of sputtered SiO₂ and SiO₂-polycrystalline silicon layers on silicon substrates were investigated and improved to a quality which is equivalent to those of thermally grown SiO₂ with pyrolytical polycrystalline silicon (polySi). For testing these layers as gate oxide and Si electrodes of MOS transistors the well known Si gate process was varied to include sputter deposition and the optimal deposition, annealing and diffusion parameters were integrated.MOS transistors with sputtered SiO₂ and Si gate material layers and for comparison Al gate devices with sputtered SiO₂ have been fabricated and their threshold voltage behavior was tested.     

A new technique to quantify deuterium passivation of interfacetraps in MOS devices

The ubiquitous presence of hydrogen in the fabrication of complementary metal oxide semiconductor (CMOS) devices results in the passivation of most interface traps by hydrogen. In this letter, we show that this hydrogen cannot be completely replaced by deuterium through a one-step deuterium anneal process. Improved device reliability attributed to deuterium incorporation at the oxide/silicon interface is thus limited by the remnant hydrogen. To determine the deuterium passivation fraction, we propose a new technique that is based solely on electrical testing. Compared to other techniques such as secondary ion mass spectrum (SIMS), the new technique can be used to measure the deuterium passivation fraction in deep submicron MOS devices with very small testing areas     

A digital readout technique for capacitive sensor applications

The difference between two capacitors is measured digitally using a charge redistribution technique incorporating a comparator, MOS switches, a successive approximation register, and a digital-to-analog converter. The technique is insensitive to comparator offset and parasitic capacitance, and the effect of MOS switch charge injection is measured and canceled. Extensive measurements have been made from test chips fabricated in 3-μm CMOS technology. Detection of percent differences of <0.5% on 20-100-fF capacitors has been successfully demonstrated     

C/SUP 2/L: A new high-speed high-density bulk CMOS technology

C/SUP 2/L, or closed COS/MOS logic, is a new structural approach to high-speed bulk-silicon COS/MOS logic. C/SUP 2/L is a self-aligned silicon-gate CMOS technology where the gate completely surrounds the drain. The use of such geometry maximises the transconductance to capacitance ratio for devices and thus allows high on-chip speed. The CDP 1802 single-chip 8-bit microprocessor, as well as several memory and I/O circuits announced recently by the RCA Solid State Division, are fabricated in this new technology. Generally, C/SUP 2/L devices show an improvement in packing density by a factor of 3 over standard CMOS and operate at frequencies approximately 4 times faster than standard CMOS. The fabrication sequence for C/SUP 2/L devices requires 6 photomasks (one less than standard CMOS).     

Impact of surrounding gate transistor (SGT) for ultra-high-densityLSI's

A transistor with compact structures for future MOS devices is discussed. This transistor, whose gate electrode surrounds the pillar silicon island, reduces the occupied area for all kinds of circuits. By using this transistor, the occupied area of the CMOS inverter can be shrunk to 50% of that using planar transistors. Other advantages, such as steep cutoff characteristics, very small substrate bias effects, and high reliability, are discussed. Its structure, which allows for the enlargement of gate-controllability to the channel and electric field relaxation at the drain edge, is described. The advantages of this SGT for large-scale integration (LSI) devices is discussed     

The CMOS carry-forward adders

The ripple-carry adder (RCA) has the simplest circuit structure but the longest delay among all adders. Thus, it is often realized with the dynamic circuits when speed is the major concern. In this paper, we propose circuit-level and architecture-level innovations over the dynamic RCA (DRCA) that lead to high operation speed and low hardware overhead. Circuit-wise, we propose a cost-effective way to eliminate the race problem of DRCA. Architecture-wise, we propose a new carry-forwarding scheme that combines a diagonal forwarding with the multilevel folding for dramatic speed improvement of the DRCA. Finally, a new multilevel carry-forwarding scheme is proposed to reduce the circuit complexity while keeping the speed. Based on all the proposed techniques, a 32-bit dynamic carry-forward adder (CFA32) with two-level carry forwarding is designed and fabricated with the 0.25-/spl mu/m CMOS technology. The CFA32 consists of 1202 MOS transistors, and occupies only 0.017-mm/sup 2/ silicon area after layout. The measurement result, which agrees with the simulation result, shows that the adder needs only 640 ps to perform an add operation under room temperature. Using the same techniques, a 64-bit carry-forward adder (CFA64) with two-level forwarding technique is also designed and simulated. The CFA64 consists of only 2502 MOS transistors, and the simulation result shows the evaluation time is only 780 ps.