Finite-difference time-domain analysis of integrated ceramic ball grid array package antenna for highly integrated wireless transceivers

This paper presents a study of the integration of an antenna in a ceramic ball grid array package for highly integrated wireless transceivers. The study has been carried out on an 11/spl times/11.66 mm/sup 2/ small microstrip antenna in a thin 48-ball ceramic ball grid array package with the finite-difference time-domain (FDTD) method in C band. The impedance and radiation characteristics of the antenna are examined. More importantly, the loading effects of the complementary metal-oxide-semiconductor (CMOS) chip and bond wires on the performance of the antenna are investigated. It is found that the loading generally increases the impedance bandwidth but decreases the radiation efficiency of the antenna. To minimize detrimental loading, the shield of the antenna from the CMOS chip is considered. A new design has been realized. The new antenna achieves impedance bandwidth of 4.65%, radiation efficiency of 63%, and gain of 5.6 dBi at 5.52 GHz.     

A Methodology for Drop Performance Modeling and Application for Design Optimization of Chip-Scale Packages

As handheld electronic products are more prone to being dropped during useful life, package-to-board interconnect reliability has become a major concern for these products. This has prompted the industry to evaluate the drop performance of chip-scale packages (CSPs) while mounted on printed wiring boards using board-level drop testing. Although a new board-level test method has been standardized through JEDEC (JESD22-B111), characterization tests take quite a long time to complete, extending the design cycle. This paper proposes a method to compare and evaluate the drop performance through simulations at the design stage. A global-local approach is used to first determine the dynamic response of the board during drop and then to translate it into stresses and strain energy density in solder joints and intermetallic layers. The dynamic response of the board is validated by using data from actual board level testing as per JEDEC standard. The solder joint and intermetallic stresses are then related to drop to failure test data to derive a relative prediction model. The method is then applied to quantify the effect of package design parameters on the drop performance. Factors considered include moldcap thickness, ball pad opening, and land grid array (LGA) versus ball grid array (BGA). The same factors were tested in board level drop to further validate the prediction model. The results indicate that the drop performance can be increased by a factor of 2 or more by changing package design variables     

多层封装基板中同步开关噪声研究

文章以栅格阵列封装(land grid array,LGA)模型为研究对象,分析了多层封装基板中的同步开关噪声(simultaneous switching noise,SSN)问题。首先利用频域仿真工具PowerSI得到了键合线和信号布线的S参数模型。然后通过在电路仿真工具HSPICE中加载封装结构的S参数模型和驱动器模型来仿真同步开关噪声。最后在设计中选取在多层基板上添加去耦电容的方式来减小同步开关噪声。仿真结果表明,通过在本LGA多层基板设计中添加110pF容值的去耦电容,可以较好地减少同步开关噪声,满足设计要求。     

一种毫米波封装的设计与优化方法

随着5G时代的到来,毫米波封装市场正在持续增长,毫米波模块的工作频率越来越高,封装也面临着越来越严格的要求。性能良好的毫米波封装应该在广阔的频段上都要有良好的射频性能。而现有封装设计中的策略是基于已有的设计经验和2D/2.5D建模的工具,其精确度已经没法适应毫米波频段的要求。在毫米波产品的研发中,需要在设计阶段就对已有设计在3D建模软件HFSS中进行仿真验证和精密优化,实现仿真与设计的并行。描述了一种FC-LGA(倒装栅格阵列)封装的设计与优化方法,通过对通道模型的仔细优化,在0~30 GHz的宽频带上都实现了良好的反射、插损特性,并在工艺允许的范围内尽量优化了串扰。     

Accurate RF electrical characterization of CSPs using MCM-D thin film technology

The thin film multilayer multichip module-deposited (MCM-D) technology of IMEC is used for characterising the RF electrical performance of two types of chip scale packages (CSPs). The measurement technique called MCM-on-package-on-MCM (MoPoM) enables accurate measurements and de-embedding in the gigahertz (GHz) range of frequencies. Wafer processing of the MCM-D technology allows for several design structures to be integrated on a single mask. The packages chosen are a 120-pin plastic ball grid array (PBGA) and an 80-pin polymer stud grid array (PSGA). Lumped element models extracted from measurements and three-dimensional simulations show good agreement with the measurements up to 6 GHz for the BGA and the PSGA. The electrical performance of the packages is compared at 1.8 GHz (GSM), 2.4 GHz (Bluetooth), and 5.2 GHz (HiperLAN) and at 5.2 GHz both the packages exhibit a return loss of lower than -10 dB and hence cannot be used in most cases without design improvement. We also show that the influence of encapsulant is significant while transmission line detuning due to the package is not significant at microwave frequencies. We also briefly mention about the crosstalk effects. We demonstrate the significant degradation in the performance of a 5.2 GHz MCM-D low noise amplifier (LNA) after packaging. A significant improvement in package performance is observed by conjugate matching the package interconnects.     

Modeling and simulation of core switching noise for ASICs

This paper presents simulation and analysis of core switching noise for a CMOS ASIC test vehicle. The test vehicle consists of a ceramic ball grid array (CBGA) package on a printed circuit board (PCB). The entire test vehicle has been modeled by accounting for all the plane resonances using the cavity resonator method. The models included both the on-chip and off-chip decoupling capacitors. Using both time domain and frequency domain simulations, the role of plane resonances on power supply noise for fast current edge rates has been discussed. The models have been constructed to amplify certain parts of the test vehicle during simulations     

Optimization of board-level thermomechanical reliability of high performance flip-chip package assembly

In this paper, we study board-level thermomechanical reliability of a high performance flip-chip ball grid array package assembly subjected to an accelerated thermal cycling test condition. Different control factors are considered for an optimal design towards enhancement of the thermal fatigue resistance of solder joints. These factors include solder composition, underfill, substrate size, lid thickness, stiffener ring width, test board size, soldermask opening on the substrate side, and pad size on the test board. The shape of solder joints after reflow is estimated using Surface Evolver. The optimal design is obtained using an L₁₈ orthogonal array according to the Taguchi optimization method. Importance of these control factors on the board-level thermomechanical reliability of the package is also ranked.     

Thermal analysis of a flip chip ceramic ball grid array (CBGA) package

The function of an electronic cooling package is to dissipate heat to ensure proper operation and reliability. The flip chip ball grid array package is probably the most suitable package for high-level thermal performance applications. A high thermal performance flip chip ceramic ball grid array (FC-CBGA) package with an aluminum silicon carbide (AlSiC) lid and one without lid were evaluated using the computational fluid dynamics (CFD) technique. This paper compares the thermal performance of a 35 × 35 mm FC-CBGA package with three different die sizes of 5 × 5 mm, 15 × 15 mm and 20 × 20 mm. The performance of a lid fitted with different heat sinks was investigated in standard JEDEC defined natural and in forced convection environments. Thermal measurements were performed using a functional application specific integrated circuit (ASIC) chip, in compliance with the JEDEC standards. Excellent agreement was found between the numerical results and the measured data. Improved thermal performance was observed with a lidded package as compared to the unlidded one. However, no significant improvement was observed between lidded and unlidded packages when fitted with a heat sink subjected to forced convection. This paper also discusses the package thermal budget estimate with and without heat sinks. Printed circuit board and package top surface temperature patterns were measured using an infrared thermal camera. The usefulness of the thermal characterization parameter is demonstrated in system level applications. Parametric studies were carried out to understand the effect of die size, radiation effect, gird size variations and airflow rate on die junction temperature and package thermal resistance. This study also incorporates the effects of substrate, lid, die and PCB temperatures for different die sizes in natural and forced convection environments.     

Power distribution networks for system-on-package: status and challenges

The power consumption of microprocessors is increasing at an alarming rate leading to 2X reduction in the power distribution impedance for every product generation. In the last decade, high I/O ball grid array (BGA) packages have replaced quad flat pack (QFP) packages for lowering the inductance. Similarly, multilayered printed circuit boards loaded with decoupling capacitors are being used to meet the target impedance. With the trend toward system-on-package (SOP) architectures, the power distribution needs can only increase, further reducing the target impedance and increasing the isolation characteristics required. This paper provides an overview on the design of power distribution networks for digital and mixed-signal systems with emphasis on design tools, decoupling, measurements, and emerging technologies.     

Mechanical, thermal, and electrical analysis of a compliant interconnect

Ball grid array (BGA) package styles use solder balls as electrical interconnects between packages and application boards. Solder balls are rigid and tend to fracture under thermal fatigue and/or shock loading. Metalized polymer spheres (MPS) offer a more compliant interconnect, compared to solder balls, thereby increasing the thermal cycling fatigue life. A reduction in thermal and electrical performance may be expected for MPS interconnects as a result of its higher thermal and electrical resistances. A 5% and an 8% increase in MPS thermal resistance was measured for a carrier array ball grid array (CABGA) package and a plastic ball grid array (PBGA) package, respectively, compared to eutectic solder balls. However, this small reduction was offset by large gains in the solder joint life. A 1.6 times increase in the mean thermal fatigue life was measured for a CABGA using MPS interconnects compared to eutectic solder balls. A first-order model showed that eutectic solder balls provide greater process margins, compared to MPS interconnects, due to the ball collapse during reflow.     

Thermal design of a broadband communication system with detailed modeling of TBGA packages

This paper presents a thermal modeling of a broadband network communication box partitioned into two stacked modules. A printed circuit board (PCB) is inside each module where an array of 16 tape ball grid array (TBGA) packages is surface mounted to the PCB. The TBGA package dissipates 6 W power each. In addition, 12 W of power is dissipated from four plastic ball grid array (PBGA) packages on the PCB. Pin-fin heat sinks are attached to the TBGA packages using silica-filled epoxy to enhance heat dissipation. Pin-fin heat sinks are also attached to the PBGA packages. Two exhaust fans are mounted at the flow exit to draw ambient air into the system at approximately 200 linear feet per minute (LFM) of velocity. The full Navier–Stokes equations for airflow are solved to simulate the forced convection cooling in the electronic module. Buoyancy effect was considered in the numerical model by incorporating Boussinesq-approximation. The TBGA packages are modeled in detail in order to obtain the package junction temperatures for system reliability evaluation and thermal design optimization. Detailed models of the attached pin-fin heat sinks and the epoxy interfaces are also utilized in this study. Compact heat sink model composed of a base plate and a resistance fluid volume is applied to model heat dissipation from the heat sinks attached to the four PBGA packages. System fan curve is used to simulate the fan operating conditions. The effect of changing system thermal design on the TBGA package junction temperatures as well as the hydraulic operating conditions of the system fans are examined and reported herein. The effect of radiation heat transfer is also examined. The importance of detailed modeling of the high power TBGA packages is demonstrated in this study. Simulation results were compared with JEDEC thermal test data under similar conditions of airflow.     

Heat transfer from square pin-fin heat sinks using air impingement cooling

Experimental and numerical results are presented for heat transfer from a C4 mounted organic land grid array (OLGA) thermal test chip cooled by air impingement. Five heat sink geometries were investigated for Reynolds numbers ranging from 9,000 to 26,000. The dimensionless nozzle-to-heat sink vertical spacing z/D was varied between 2 and 12. In this study, we investigate the interactions between heat sink geometry, flow conditions and nozzle setting and how they affect the convective heat transfer and overall cooling of the test chip as measured by total thermal resistance /spl theta//sub ja/. Optimizing fin arrays by minimizing the overall heat sink thermal resistance instead of focusing solely on maximizing the heat transfer from the fins is shown to be a better design criterion. We also provide results that show cooling performance gains can be obtained by inserting a deflector plate above the heat sink.     

Measurement and Simulation of Stacked Die Thermal Resistances

Packages with multiple dies provide additional challenges when documenting their thermal performance. One style of multiple dies packages stacks the die on top of each other with a die attach adhesive. This paper explores the thermal performance of such packages in a wire bond plastic ball grid array package with three different die configurations. The thermal performance of the package was determined using the JEDEC JESD51 specifications. Since there were three different effective die sizes, the data allowed a better validation of the finite element thermal simulation techniques than can be obtained with only a single die size. Die size is usually the most important predictor of plastic ball grid array thermal performance. In this case, packages built with the same materials and substrate had a Theta-JA (2s2p board, natural convection) that differed by 100% as a result of a change in effective die size. With a validated simulation method, additional power distributions were simulated and compared to results obtained by superposition techniques.      

Multidisciplinary Electronic Package Design and Optimization Methodology Based on Genetic Algorithm

A new multidisciplinary design and optimization methodology in electronics packaging is presented. A genetic algorithm combined with multidisciplinary design and multiphysics analysis tools are used to optimize key design parameters. This methodology is developed to improve the electronic package design process by performing multidisciplinary design and optimization at an early design stage. To demonstrate its capability, the methodology is applied to a ball grid array (BGA) package design. Multidisciplinary criteria including thermal, thermal strain, electrical, electromagnetic leakage, and cost are optimized simultaneously. A simplified routability analysis criterion is used as a constraint. The genetic algorithm is used for systematic design optimization. The present methodology can be applied to electronics product design at various packaging levels.     

Electrical evaluation of flip-chip package alternatives for nextgeneration microprocessors

Two styles of flip-chip packages for next-generation microprocessors were designed: a low-cost organic ball-grid-array (BGA) and a thin-film-on-ceramic land-grid array (LGA). Simultaneous switching output (SSO) noise, and core noise were measured. Although SSO was improved by a factor of two over the previous generation of packaging, core noise was still quite significant. We found that core noise is best managed by placing low-inductance capacitance close to the noise source, i.e., using on-chip capacitors, coupled planes in the package, or on-package bypass capacitors. Because of the lower impedance of its power planes, the ceramic package showed significantly better electrical performance than the organic. Addition of on-package bypass capacitors greatly narrows the gap between the two packages     

Innovative circuit board level routing designs for BGA packages

Advances in the performance of electronic devices have resulted in high input/output counts both at the chip and the package level, which has led to the development of new packaging technologies that can accommodate these high counts. This paper presents and analyzes a novel method for the placement of ball grid array (BGA) bonding pads and routing wires on printed circuit boards to maximize signal density, which ultimately reduces the number of circuit board layers needed for routing. This method has been termed as the "balls shifted as needed" method and all the ball placement/trace routing designs shown in this paper are based on this method. We also present a performance metric defined as the number of balls routed out divided by the area of package footprint on the circuit board, and we compare various placement/routing schemes using this method.     

A visualization-based approach for bump-pad/IO-ball placement and routing in flip-chip/BGA technology

The routing problem in area array integrated circuit (IC) packaging has become an extremely complex problem in the realm of high I/O count IC packages. With the advent of flip-chip and ball grid array (BGA) technology to meet the current demands of smaller size and high wiring densities, the routing problem lies in the core of electronic design automation process. In this paper, we describe an intuitive computer visualization-based approach for placement and routing of bonding pads that would result in low manufacturing costs and smaller component size compared to conventional approaches. This novel approach is an extension of "balls shifted as needed" method for I/O ball placement in BGA package enabling single-layer board-level routing for any I/O count. The I/O ball/pad layout and routing designs along with results are presented for two routing layers with the inclusion of vias in the design. This routing scheme is shown to be easily extensible to accommodate more practical multilayer routing and can be incorporated in current electronic design automation (EDA) computer-aided design (CAD) tools to offer an integrated routing solution for area array chip-package-board codesign. The results show that different trace routing patterns lead to different area requirements for same number of I/Os. This has led to the formulation of new design paradigms which are presented in the paper for smaller component size.     

A study of dual-mode bandpass filter integrated in BGA package for single-chip RF transceivers

This paper presents a study of a dual-mode bandpass filter integrated in a ball grid array (BGA) package for the single-chip solutions of radio frequency (RF) transceivers. The novel in-package filter, except for the economical advantage of mass production and automatic assembly, has potential benefit to the system-level board miniaturization and the system-level manufacturing facilitation. The simulated and measured performance of the in-package filter is presented. The effects of the different physical parts of the package on the filter performance are investigated. Experimental results show that the in-package filter of size 15/spl times/15/spl times/1.905 mm/sup 3/ achieved 3-dB percentage bandwidth of 14% and insertion loss of 2.07 dB at 5.25 GHz.     

CBGA、CCGA器件植球／柱工艺板级可靠性研究

陶瓷球栅阵列（CBGA）和陶瓷柱栅阵列（CCGA）封装由于其高密度、高可靠性和优良的电热性能,被广泛应用于武器装备和航空航天等电子产品。而CBGA／CCGA焊点由于其材料和结构特性,在温度循环等可靠性试验中焊点容易发生开裂,导致器件失效。本文以CBGA256和CCGA256封装产品为例,通过陶瓷基板与PCB板的菊花链设计来验证CBGA／CCGA焊点的可靠性,并对焊点的失效行为进行分析。结果表明,CCGA焊点可靠性要高于CBGA焊点,焊点主要发生蠕变变形,边角处焊点在温度循环过程中应力最大,容易最先开裂。     

Parameterized physical compact thermal modeling

This paper presents a compact thermal modeling (CTM) approach, which is fully parameterized according to design geometries and material physical properties. While most compact modeling approaches facilitate thermal characterization of existing package designs, our method is better suited for preliminary exploration of the design space at both the silicon level and the package level. We show that our modeling method achieves reasonable boundary condition independence (BCI) by comparing a CTM example with a BCI model for a benchmark ball grid array single-chip package under the same standard set of boundary conditions. In essence, the presented CTM method can act as a convenient medium for enhanced interactions and collaborations among designers at the package, circuit and computer architecture levels, leading to efficient early evaluations of different thermally-related design trade-offs at all the above levels of abstraction before the actual detailed design is available. The presented modeling method can be easily extended to model emerging packaging schemes such as stacked chip-scale packaging and three-dimensional integration.