Ball grid array reliability assessment for aerospace applications

Reliability of ball grid arrays (BGAs) was evaluated with special emphasis on space applications. This work was performed as part of a consortium led by the Jet Propulsion Laboratory (JPL) to help build the infrastructure necessary for implementing this technology. Nearly 200 test vehicles, each with four package types, were assembled and tested using an experiment design. The most critical variables incorporated in this experiment were package type, board material, surface finish, solder volume, and environmental condition. The packages used for this experiment were commercially available packages with over 250 I/Os including both plastic and ceramic BGA packages.The test vehicles were subjected to thermal and dynamic environments representative of aerospace applications. Two different thermal cycling conditions were used, the JPL cycle ranged from −30°C to 100°C and the Boeing cycle ranged from −55°C to 125°C. The test vehicles were monitored continuously to detect electrical failure and their failure mechanisms were characterized. They were removed periodically for optical inspection, scanning electron microscopy (SEM) evaluation, and cross-sectioning for crack propagation mapping. Data collected from both facilities were analyzed and fitted to distributions using the Weibull distribution and Coffin–Manson relationships for failure projection. This paper will describe experiment results as well as those analyses.     

CCGA packages for space applications

Commercial-off-the-shelf (COTS) area array packaging technologies in high reliability versions are now being considered for applications, including use in a number of NASA electronic systems being utilized for both the Space Shuttle and Mars Rover missions. Indeed, recently a ceramic package version specifically tailored for high reliability applications was used to provide the processing power required for the Spirit and Opportunity Mars Rovers built by NASA-JPL. Both Rovers successfully completed their 3-months mission requirements and continued exploring the Martian surface for many more moths, providing amazing new information on previous environmental conditions of Mars and strong evidence that water exists on Mars.Understanding process, reliability, and quality assurance (QA) indicators for reliability are important for low risk insertion of these newly available packages in high reliability applications. In a previous investigation, thermal cycle test results for a non-functional daisy-chained peripheral ceramic column grid array (CCGA) and its plastic ball grid array (PBGA) version, both having 560 I/Os, were gathered and are presented here. Test results included environmental data for three different thermal cycle regimes (−55/125 °C, −55/100 °C, and −50/75 °C). Detailed information on these—especially failure type for assemblies with high and low solder volumes—are presented. The thermal cycle test procedure followed those recommended by IPC-9701 for tin–lead solder joint assemblies. Its revision A covers guideline thermal cycle requirements for Pb-free solder joints. Key points on this specification are also discussed.In a recent investigation a fully populated CCGA with 717 I/Os was considered for assembly reliability evaluation. The functional package is a field-programmable gate array that has much higher processing power than its previous version. This new package is smaller in dimension, has no interposer, and has a thinner column wrapped with copper for reliability improvement. This paper will also present thermal cycle test results for assemblies of this and its plastic package version with 728 I/Os, both of which were exposed to four different cycle regimes. Two of these cycle profiles are specified by IPC-9701A for tin–lead, namely, −55 to 100 °C and −55 to 125 °C. One is a cycle profile specified by Mil-Std-883, namely, −65/150 °C, generally used for ceramic hybrid packages screening and qualification. The last cycle is in the range of −120 to 85 °C, a representative of electronic systems directly exposed to the Martian environment without use in a thermal control enclosure. Per IPC-9701A, test vehicles were built using daisy chain packages and were continuously monitored and/or manually checked for opens at intervals. The effects of many process and assembly variables—including corner staking commonly used for improving resistance to mechanical loading such as drop and vibration loads—were also considered as part of the test matrix. Optical photomicrographs were taken at various thermal cycle intervals to document damage progress and behavior. Representative samples of these are presented along with cross-sectional photomicrographs at higher magnification taken by scanning electron microscopy (SEM) to determine crack propagation and failure analyses for packages.     

Reliability of 80 μm pitch flip chip attachment on flex

The interest toward flip chip technology has increased rapidly during last decade. Compared to the traditional packages and assembly technologies flip chip has several benefits, like less parasitics, the small package size and the weight. These properties emphasize especially when flip chip component is mounted direct to the flexible printed board. In this paper flip chip components with Kelvin four point probe and daisy chain test structure were bonded to the polyimide flex with two different types of anisotropically conductive adhesive films and one anisotropically conductive adhesive paste. The reliability of small pitch flip chip on flex interconnections (pitch 80 μm) was tested in 85°C/85% RH environmental test and −40↔+125°C thermal shock test. According to the results it is possible to achieve reliable and stable ohmic contact, even in small pitch flip chip on flex applications.     

Reliability studies and design improvement of mirror image CSP assembly

In this paper, both simulation and testing techniques were used to address the reliability issue of mirror chip scale package (CSP) assembly. First, finite element modeling was employed to study the stress and strain of a mirror image CSP with comparison to a single-sided CSP. The study clearly illustrates that the strain distribution is not equally distributed across both sides of the CSP. The highest strain on one side of the mirror image CSP is often larger than the other one, which reduced the reliability of the package as a whole. In order to study the effects on the reliability of the mirror image CSP assembly, several parameters, such as PCB board materials selection, board thickness and warpage, PCB via design and routing, were investigated. Moreover, a design of experiment matrix was constructed to identify significant factors to minimize the highest strain in solder joints of mirror image. The test vehicle was then designed and assembled. Thermal cycling (0 to 100 °C) and thermal shock tests were thereafter performed to the mirror image CSPs and single-sided CSPs to compare with the simulation results.     

Wafer level packaging of a tape flip-chip chip scale packages

The advent of chip scale packages (CSPs) within the semiconductor community has led to the development of wafer scale assembly (WSA) or wafer level packaging (WLP) manufacturing in order to raise assembly efficiencies and lower operating costs. Texas Instruments (TI) has developed a unique WLP process for forming flip-chip, ball grid array packages. The die inputs and outputs of the TI CSP are connected through solder bumps to a polyimide film interposer. Solder balls on the other side of the interposer complete the electrical connection to a customer’s printed circuit board. A wafer-sized array of interposers designed to match the pattern of dies on a wafer is aligned and reflowed to a bumped wafer. The TI WLP process is completed by singulating the CSPs from the wafer using standard wafer saw equipment.Attachment of the interposer to the die as well as applying the die and board level solder bumps are carried out in wafer form using a new bumping technology called Tacky Dots™. Tacky Dots uses an array of sticky dots formed in a photosensitive coating laminated to a polyimide film for transferring and attaching solder spheres to semiconductor substrates. A populated film containing one solder sphere per Tacky Dot is positioned over the wafer or interposer and lowered until the spheres contact the pads. A reflow process transfers the spheres from the film to the wafer or interposer and the film is removed once the spheres have frozen.This paper illustrates the process steps and custom equipment developed for forming the TI CSP. The strategic use of finite element modeling for optimizing the design of the package is outlined. The paper concludes by summarizing the current package level reliability results.     

Reliability aspects of high temperature power MOSFETs

Gate oxide reliability and thermal shock resistance of power MOSFETs for high temperature applications, have been investigated by accelerated tests and several analytical and electrical techniques. Thermal shock tests have been performed between -40°C and 200°C with subsequent electrical tests and failure analysis. Time Dependent Dielectric Breakdown (TDDB) of the gate oxide has been studied in detail by means of in-situ leakage current measurements at various voltages and temperatures.A statistical analysis of the results yields information on the underlying failure time distribution, failure mechanisms and lifetime.     

Long time reliability study of soldered flip chips on flexible substrates

Due to the requirements of new light, mobile, small and multifunctional electronic products the density of electronic packages continues to increase. Especially in medical electronics like pace makers the minimisation of the whole product size is an important factor. So flip chip technology becomes more and more attractive to reduce the height of an electronic package. At the same time the use of flexible and foldable substrates offers the possibility to create complex electronic devices with a very high density. In terms of human health the reliability of electronic products in medical applications has top priority.In this work flip chip interconnections to a flexible substrate are studied with regard to long time reliability. Test chips and substrates have been designed to give the possibility for electrical measurements. Solder was applied using conventional stencil printing method. The flip chip contacts on flexible substrates were created in a reflow process and underfilled subsequently.The assemblies have been tested according to JEDEC level 3. The focus in this paper is the long time reliability up to 10,000 h in thermal ageing at 125 °C and temperature/humidity testing at 85 °C/85% relative humidity as well as thermal cycling (0 °C/+100 °C) up to 5000 cycles. Daisy chain and four point Kelvin resistances have been measured to characterise the interconnections and monitor degradation effects.The failures have been analysed in terms of metallurgical investigations of formation and growing of intermetallic phases between underbump metallisation, solder bumps and conductor lines. CSAM was used to detect delaminations at the interfaces underfiller/chip and underfiller/substrate respectively.     

Over GHz electrical circuit model of a high-density multiple line grid array (MLGA) interposer

The multiple line grid array (MLGA) interposer was recently introduced as a future high-density high-speed bonding method. In this paper, we introduce an electrical model and high-frequency characteristics of the MLGA interposer. The high-frequency electrical model was extracted from microwave S-parameter measurements up to 20 GHz as well as from fundamental microwave network analysis. For the parameter fitting process during model extraction, an optimization method was used. Several different types of MLGA interposers were designed, assembled and tested. The test vehicles contained coplanar waveguides, probing pads and an MLGA interposer structure. The height of the MLGA, the conductor shape inside the MLGA, and the dielectric insulator of the MLGA were varied. From the model, an MLGA with a height of 0.4 mm and a polymer dielectric insulator was found to have 203 pH of self inductance, 49 pH of mutual inductance with the nearest ground conductor line, and 186 fF of mutual capacitance. By reducing the height of the MLGA and by using an insulator with a lower dielectric constant, parasitic inductance and capacitance is further reduced. TDR/TDT simulation and measurement showed the validity of the extracted model parameters of the MLGA interposer. Circuit simulation based on the extracted model revealed that the MLGA interposer could be successfully used for microwave device packages up to 20 GHz and for high-speed digital device packages with a clock cycle up to 5 GHz.     

A new methodology for the identification of ball bond degradation during high-temperature aging tests on devices in standard plastic packages

We describe a new methodology for the “in situ” identification of wire-bond degradation at early stages during high-temperature aging tests on devices with standard plastic packages. This methodology is based on the measurement of the changes in wire bond resistance, which is deduced from the I(V) characteristics of the ESD protection diodes on each contact pad of the circuit. In a first stage, the measurement procedure is described, with emphasis on the initial temperature calibration. This procedure allows for an “in situ” measurement sequence, where the packages stay in the aging chamber, at elevated temperature, during the electrical tests on the pad connections performed at different aging durations. By following accurately the package temperature, using a thermocouple, it is possible to correct for slight changes and thus get a reliable I–V measurement for each interconnection. In the second stage, the aging test results are described, showing the evolution of each individual interconnection. We were able to identify the onset of wire-bond degradation through the progressive increase of their resistance. To allow for better determination of the degradation process, once an increase in wire bond resistance was detected, complete I(V) curves were recorded at the pin(s) of interest. For each pin of a TQFP64 package, the tests were performed at least twice a day, with increased density when initial failure is detected (one complete measurement every 3 h). This strategy allowed for the detection of different behaviors on the wire bonds: good ball bonds (i.e. ball bonds with no change in their resistance), ball bond with intermittent opens (these ball bonds are in the process of degradation, and thermo-mechanical stresses induced in the resin by very small temperature changes are sufficient to open or close the circuits) and completely destroyed ball bonds, for which the resistance stays in an “high” level. This approach to wire-bond degradation in plastic packages is very powerful in terms of the number of interconnections which can be followed “in real time” and especially has the advantage, over other classical approaches, that the devices under test stay operational, contrary to what occurs with other types of destructive testing. These electrical test results are compared with metallographic investigations performed after a series of mechanical tests on the ball bonds (wire pull/ball shear tests) on a set of identical devices which undergone exactly the same High Temperature Storage (HTS) aging for 2000 h at 165 °C.     

Structural reliability assessment of multi-stack package (MSP) under high temperature storage (HTS) testing condition

Wire ball open failure at the interface of the gold wire and bonding pad of a multi-stack package (MSP) under high temperature storage (HTS) condition of 150 °C is studied. Failure analysis using FIB-SEM was conducted by in-plane moiré interferometry and FEA to clarify the failure mechanism. The ball open failure due to Kirkendall void that results from metal diffusion at high temperature was accelerated by the tensile stress imposed at the gold wire. The tensile stress developed at the gold wire when packages showing different warpage behaviours were stacked. Mechanical interaction between top and bottom packages caused unstable warpage, readily twisted and saddled. The wire came in contact with the photo-sensitive solder resist (PSR) dam because of the unstable warpage and this contact resulted in tensile stress at the gold wires. Solder flux residues reacted with the encapsulant, and as a result, the encapsulant of the top package adhered to the chip of the bottom package, and this adherence created additional tensile stress at the gold wires. To reduce the tensile stress at the wires, the PSR dam was removed, loop shape was altered from 45° to 90°, water soluble flux was applied, and cleaning process was added. HTS reliability was significantly improved and guaranteed after reducing the tensile stress at the wires.     

Flip chip attachment on flexible LCP substrate using an ACF

In this study the reliability of a flip chip bonding process using anisotropic conductive adhesives (ACA) was evaluated. The flexible substrates used were made of liquid crystal polymer (LCP), which is an interesting new material having excellent properties for flexible printed circuit boards. The test samples were prepared using two different anisotropic conductive films (ACF) having the same fast-cure resin matrix, but different conductive particles. The reliability of the test samples was studied by accelerated environmental tests. In the constant humidity test the temperature was 85 °C and the relative humidity was 85%. The temperature cycling test was carried out between temperatures of −40 °C and 85 °C. To determine the exact time of a failure the resistance of each test sample was measured using continuous real-time measurement. A clear difference between the behaviour of the conductive particles was seen in the test. While the adhesive having polymer particles had only one failure during testing, the adhesive having nickel particles had a considerable number of failures in both tests. Cross sections of the samples were made to analyze the failure mechanisms.     

Application of a combined methodology for extraction of the electrical model of a lead frame chip-scale package

An ultra-miniature interconnect (IC) package such as a chip-scale package (CSP) provides a difficult challenge in electrical model extraction, particularly to multi-GHz frequencies, because the very small parasitics can easily be swamped by test fixture parasitics and/or by small measurement errors that might be negligible in a larger package. Incomplete data for the high-frequency electrical properties of package materials and small dimensional errors in physical model entry into electromagnetic (EM) simulators, again negligible in larger packages, may also cause significant error. Therefore, for ultra-miniature packages it is necessary to cross-correlate multiple measurement and simulation methods to ensure that an accurate package electrical model is obtained. This paper therefore presents a closed-loop cross-correlation of s-parameter and time domain reflectometry (TDR) measurements with EM simulation and TDR simulation for a 16-pin lead frame chip-scale package (LFCSP) and the extraction of a cross-verified electrical model to 10 GHz. The authors are not aware of the previous application of these multiple techniques to a CSP to this bandwidth.     

A simple model for the mode I popcorn effect for IC packages

A simple model for the Mode I popcorn effect is presented here for packages with rectangular die pad (P-DSO). A package “stability parameter”, relating to its moisture sensitivity, is derived from the popcorn model. It describes the critical factors for a robust package - molding compound properties and package, leadframe design for a given preconditioning and soldering process. Furthermore, nomograms generated from the model enable an easy estimation of moisture sensitivity levels (between 1 and 5) of packages with different die pad sizes and molding compound underpad thicknesses and for different soldering temperatures ranging from 220°C to 260°C (Pb-free soldering).     

A simple moisture diffusion model for the prediction of optimal baking schedules for plastic SMD packages

The moisture concentration at the chip surface is the important parameter for the moisture sensitivity of the P-MQFP80 product considered here. When the critical moisture concentration at the die surface is reached, delamination occurs after soldering shock, e.g at 240°C. This critical moisture concentration, which can be determined by experiments conducted at 30°C/60% relative humidity (RH) followed by soldering shock, allows to predict the product’s moisture performance at other ambient conditions. In the case studied here, prediction was done at a customer use condition of 30°C/85% RH. Furthermore, this work showed that preconditioning of plastic packages not only induces the onset of delamination at the die surface but it appears to weaken the adhesion at this interface as well. As a result, delamination failure starts to occur earlier (i.e. within shorter moisture exposure time) in the devices tested after subsequent thermal cycling stress test. A simple moisture diffusion analytical model is proposed here for predicting the optimal baking schedules for plastic SMD packages.     

Development of the green plastic encapsulation for high density wirebonded leaded packages

The push in the electronics industry toward miniaturization and high density wirebonds is a major driving force in integrated circuit (IC) package design. One problem has been the use of conventional mold compounds to encapsulate the high density wirebonded packages, due to performance issues, such as wire sweep and coplanarity. Additionally, in order to match lead-free solutions in the near future, antimony- and halogen-free molding compound must be developed because antimony (Sb) and halogens in current flame retardant systems pose environmental hazardous. This article, discusses a “green” compound that eliminated these environmentally hazardous elements, resolving moldability and reliability issues for high density wirebonded packages.The reliability assessment was conducted at the maximum reflow peak temperature of 240 °C after moisture soaking at 60 °C/60%RH for 40 h, followed by temperature cycle tests. The study aimed for good package integrity, process, and performance to meet the requirements of high volume production and an acceptable moisture sensitivity (level 3) with a reflow temperature of 240 °C. The study indicates that moldability and reliability involved separate issues and offers a solution for high volume production and field application.     

Solder joint fatigue life of fine pitch BGAs – impact of design and material choices

The impact of design and material choices on solder joint fatigue life for fine pitch BGA packages is characterized. Package variables included die size, package size, ball count, pitch, mold compound, and substrate material. Test board variables included thickness, pad configuration, and pad size. Three thermal cycle conditions were used.Fatigue life increased by up to 6× as die size was reduced. For a given die size, fatigue life was up to 2× longer for larger packages with more solder balls. Mold compounds with higher filler content reduced fatigue life by up to 2× due to a higher stiffness and lower thermal expansion coefficient. Upilex S tape with punched holes gave 1.15× life improvement over Kapton E tape with etched holes. Once optimized, tape-based packages have equal board level reliability to laminate-based packages.Solder joint fatigue life was 1.2× longer for 0.9 mm thick test boards compared to 1.6 mm thick boards due to a lower assembly stiffness. The optimum PCB pad design depends on failure location. For CSP applications, NSMD test board pads give up to 3.1× life improvement over SMD pads. For a completely fan-out design, there was a 1.6× acceleration factor between −40125°C, 15 min ramps, 15 min dwells and 0100°C, 10 min ramps, 5 min dwells.     

Reliability evaluation of plastic packaged devices for long life applications by THB test

The reliability of transistors, bipolar and CMOS integrated circuits encapsulated in different types of plastic packages was investigated by using the 85°C/85% R.H. test with applied bias and the results compared with a long term operating life test. Particular attention was devoted to pointing out the influence of technology, process control and working conditions on device reliability and failure mechanisms.In micropackaged transistors the importance of surface passivation in protecting the devices against gold corrosion was forcused, while the need of good process control was confirmed by the results of the test on micropackaged linear integrated circuits.In dual-in-line CMOS integrated circuits silicon nitride and polymide give, in general, a superior protection, but good results were obtained also with normal P-glass passivation when a clever arrangement of layout design rules was adopted. Results obtained exhibit a significant improvement in the reliability of plastic packaged devices, with the best figures showing no failures after 15,000 hours at 85°C/85% R.H. test with bias.     

Reliability studies of two flip-chip BGA packages using power cycling test

Power cycling tests of the second level reliability of two flip-chip BGA packages are discussed in this paper. The first one is for a flip-chip on laminate package (FCPBGA) and the other for a flip-chip on ceramic package (FCCBGA). For the FCPBGA, test strategies will be first discussed and then focus will be given to a unique failure mode associated with this type of packages assembled back to back onto printed circuit board. Instead of anticipated failures of the corner solder joints under the die shadow, as in the case of wire-bonded packages, we found that solder joints failed first in the central region of the package and then failures of solder joints spread out in the radial direction from the center of the package. Explanation will be given to the physical mechanisms that caused this type of failure. For the FCCBGA, the improved test strategies based on what has been learned from the test of FCPBGA will be presented and focus will be given to the effect of different parameters on the second level reliability of the package. Here, because of the increased rigidity of the ceramic substrate solder joints failed as expected first at the corner(s) of the ceramic substrate. Based on the test results and the modified Coffin–Manson equation, predictions or the solder joint fatigue life will be shown.     

Wire-bond failure mechanisms in plastic encapsulated microcircuits and ceramic hybrids at high temperatures

Ceramic hybrids are the preferred solution when long-term high-temperature reliability is required, but standard plastic encapsulated microcircuits (PEMs) are an interesting alternative due to low price and high availability. Test vehicles with standard PEMs were subjected to thermal ageing at 150–175 °C. Six of eight vehicles failed after only three weeks at 175 °C, and the cause of failure was found to be microcracking at the interface between gold ball and aluminium bond pad giving rise to resistance increase. The intermetallic region was formed during high-temperature lead soldering and continued to develop during thermal ageing. The high-temperature performance of aluminium wire bonding to a selection of thick film metallizations on ceramic substrate was also investigated. Gold–palladium has previously been reported as a high-temperature solution, but we found that the mechanical strength of aluminium to gold–palladium (AuPd) degraded seriously at temperatures above 200 °C due to intermetallic formation. Aluminium to silver thick film plated with copper and nickel showed good mechanical strength and unaltered electrical resistance after four weeks thermal ageing at 250 °C.     

Growth of tin whiskers for lead-free plated leadframe packages in high humid environments and during thermal cycling

Growth behavior of tin whiskers from pure tin and tin-bismuth plated leadframe (LF) packages for elevated temperature and high humidity storages and during thermal cycling was observed. In the storage at 60 °C/93% relative humidity (RH) and 85 °C/85%RH the galvanic corrosion occurred at the outer lead toes and shoulders where the base LF material is exposed, forming tin oxide layers of SnO₂. The corroded layers spread inside the film and formed whiskers around the corroded islands. Many whiskers were observed to grow from grain boundaries for the Fe–42Ni alloy (alloy42) LF packages. It was confirmed that the corrosion tends to occur on the side surfaces of outer leads adjacent to the mold flash. The contribution of ionic contaminants in epoxy mold compound (EMC) to the corrosion was not identified. During thermal cycling between −65 °C and +150 °C whiskers grew out of as-deposited grains for pure tin plated alloy42 LF packages and they grew linearly with an increase of number of cycle. Growth mechanisms of the whiskers from grain boundaries and as-deposited grains were discussed from the deformation mechanism map for tin and mathematical calculation with a steady-state diffusion model.