Defect generation statistics in thin gate oxides

We analyze data-retention experiments for flash memory arrays with thin tunnel oxide (t/sub ox/ = 5 nm). These samples show an additional conduction mechanism besides Fowler-Nordheim tunneling and stress-induced leakage current (SILC). The additional leakage contribution is analyzed with respect to the spatial distribution in the array and the shape of the current-voltage characteristics, and is interpreted as an anomalous SILC due to a two-trap leakage path. From the cycling dependence of the distribution tails related to one- and two-trap leakage, we provide evidence that the defect generation statistics is not Poissonian, but is instead correlated. Possible physical mechanisms responsible for correlated generation are also discussed.     

Analysis of the relationship between defect site generation anddielectric breakdown utilizing A-mode stress induced leakagecurrent

The dielectric breakdown mechanism is studied from the viewpoint of the relationship with the generation of defect sites in the oxide film, utilizing the “A-mode” stress induced leakage current (A-mode SILC) under the constant-voltage stressing. It is demonstrated that the breakdown occurs when the A-mode SILC becomes a threshold level, I_th. In spite of that, the constant I_th for various stress fields is expected by the conventional model which assumes that each defect site is generated randomly in the oxide film, I _th, increases with the stress field. To explain this variety of I_th by the stress field, the concept of “breakdown-path creation efficiency” (γ_BPC), is proposed, which represents the amount of defect sites in the whole gate area required to create a breakdown path from one side of oxide film to the other side at a local spot. According to this concept, it is demonstrated that the efficiency becomes smaller with the increase in the stress field. These results require us to take account the nonuniform distribution of defect sites in the oxide film into the model for the breakdown mechanism. The introduction of the stress-field dependent depth profile of defect sites allows to explain the variety of I_th     

Degradation of thin oxides during electrical stress

A bond-breaking phenomenon responsible for oxide degradation during electrical stress is considered as a multi-step process that includes generation of precursor breakdown defects by the injected electrons directly in the bulk oxide and the subsequent breakdown of the defect's bonds. Precursor defect generation is attributed to the capture/scattering of the injected electrons by the localized gap states associated with oxide structural imperfections. These precursor defects, represented by significantly elongated Si–O bonds or Si–Si bonds are shown to be unstable due to their vibrational excitation and polarization induced by temperature and an applied electric field, respectively; breakdown of the weak precursor defect's bonds results in the formation of the E^′ centers. The proposed model suggests that new precursor defects are preferentially created in the vicinity of the previously generated E^′ centers. This leads to the formation of defect clusters, which can grow and coalesce throughout the oxide, contributing to oxide leakage current and eventual oxide breakdown. The model describes the charge-to-breakdown dependence on the electron fluence and energy, electric field, temperature and oxide thickness.     

Correlation of trap generation to charge-to-breakdown (Qbd): a physical-damage model of dielectric breakdown

Ultrathin gate and tunnel oxides in MOS devices are subjected to high-field stress during device operation, which degrades the oxide and eventually causes dielectric breakdown. Oxide reliability, therefore, is a key concern in technology scaling for ultra-large scale integration (ULSI). Here we provide critical new insight into oxide degradation (and consequently, reliability) by a systematic study of five technologically relevant parameters, namely, stress-current density, oxide thickness, stress temperature, charge-injection polarity (gate versus substrate), and nitridation of pure oxide. For all five parameters, a strong correlation has been observed between oxide degradation and the generation of new traps (distinct from the filling of intrinsic traps). Further, we observe that this correlation is independent of the trap polarity (positive versus negative). Based on this correlation, and based on the fundamental link between electronic properties and atomic structure, a physical-damage model of dielectric breakdown has been proposed. The concept of the physical-damage model is that the oxide suffers dielectric breakdown when physical damage due to broken bonds forms a defect-filled filamentary path in the oxide, that conducts excessive current. A good monitor of this physical damage is trap generation, which we believe is caused by physical bond breaking in the oxide and at the interface. The model has been quantified empirically by the correlation between trap generation and Q_bd     

Influence of ISSG tunnel oxide with decoupled plasma nitridation on erase characteristic of NOR-type floating-gate flash memories

This paper investigated the influence of ISSG (in situ steam generation) tunnel oxide layer with decoupled plasma nitridation (DPN) on the erase reliability of NOR-type floating-gate flash memory devices. The experimental results demonstrated that the tunnel oxide with ISSG process achieves better thickness uniformity and higher breakdown voltage than that with conventional dry oxidation process. However, the erase performance of flash cells was significantly degraded when DPN was applied to the ISSG oxide. The higher bulk nitrogen content from DPN process could lead to more bulk traps generation by substituting the strong Si–O bonds for the weak Si–N bonds in the tunnel oxide. During program/erase cycling, the more electrons trapped in the bulk tunnel oxide the less the FN erase electric field will be, which is responsible for the degradation of erase performance.     

Time-dependent dielectric breakdown of ultra-thin silicon oxide

To evaluate the reliability of thin thermally grown oxide films, we examined their intrinsic breakdown characteristics and investigated oxide defects in them using ultra-thin oxides (3-10 nm). It is demonstrated that the breakdown time of oxide films becomes longer as the film thickness is decreased. Through the use of an electron trap generation model, we were able to explain this phenomenon and estimate the breakdown time under low electric field or low current conditions. Furthermore, we were able to determine that, with decreasing film thickness, the defect density of the initial short mode increases, while that of the weak-spot mode decreases.     

Power-law voltage acceleration: A key element for ultra-thin gate oxide reliability

The properties of the so-called time dependent dielectric breakdown (TDDB) of silicon dioxide-based gate dielectric for microelectronics technology have been investigated and reviewed. Experimental data covering a wide range of oxide thickness, stress voltage, temperature, and for the two bias polarities were gathered using structures with a wide range of gate oxide areas, and over very long stress times. Thickness dependence of oxide breakdown was shown to be in excellent agreement with statistical models founded in the percolation theory which explain the drastic reduction of the time-to-breakdown with decreasing oxide thickness. The voltage dependence of time-to-breakdown was found to follow a power-law behavior rather than an exponential law as commonly assumed. Our investigation on the inter-relationship between voltage and temperature dependencies of oxide breakdown reveals that a strong temperature activation with non-Arrhenius behavior is consistent with the power-law voltage dependence. The power-law voltage dependence in combination with strong temperature activation provides the most important reliability relief in compensation for the strong decrease of time-to-breakdown resulting from the reduction of the oxide thickness.Using the maximum energy of injected electrons at the anode interface as breakdown variable, we have resolved the polarity gap of time- and charge-to-breakdown (T_BD and Q_BD), confirming that the fluency and the electron energy at anode interface are the fundamental quantities controlling oxide breakdown. Combining this large database with a recently proposed cell-based analytical version of the percolation model, we extract the defect generation efficiency responsible for breakdown. Following a review of different breakdown mechanisms and models, we discuss how the release of hydrogen through the coupling between vibrational and electronic degrees of freedom can explain the power-law dependence of defect generation efficiency. On the basis of these results, a unified and global picture of oxide breakdown is constructed and the resulting model is applied to project reliability limits. In this regard, it is concluded that SiO₂-based dielectrics can provide reliable gate dielectric, even to a thickness of 1 nm, and that CMOS scaling may well be viable for the 50 nm technology node.     

Hole trapping and trap generation in the gate silicon dioxide

Oxide breakdown has been proposed to be a limiting factor for future generation CMOS. The breakdown is caused by defect generation in the oxide. Although electron trap generation has received much attention, there is little information available on the hole trap generation. The relatively high potential barrier for holes at the oxide/Si interface makes it difficult to achieve a high level of hole injection. Most previous work was limited to an injection level Q_inj of 10¹⁴ cm^-2. In this paper, we investigate the hole trapping and trap generation when Q_inj reaches the order of 10¹⁸ cm^-2. When Q_inj <10¹⁵ cm^-2, the trapping is dominated by the as-grown traps. As Q_inj increases further, however, it is found that the generation of new traps controls the trapping. The trap generation does not saturate up to the oxide breakdown. The trapping kinetics for both the as-grown and the generated traps is studied. The relationship between the density of generated traps and the Q_inj is explored. Attention is paid to how the trapping and trap generation depends on the distance from the interface. In contrast to the uniform generation of electron traps across the oxide, we found that the hole trap generation was not uniform and it moved away from the interface as Q_inj increased     

Correlation between two time-dependent dielectric breakdownmeasurements for the gate oxides damaged by plasma processing

The relationship between two time-dependent dielectric breakdown (TDDB), the charge-to-breakdown under constant-current injection (Q_bd), and the time-to-breakdown under constant-voltage stress (t_bd) is derived from a defect generation model and investigated for the gate oxide damaged by plasma processing such as the antenna effect. It is found that although the Q_bd of the damaged oxide monotonously decreases with antenna ratio (r=exposed antenna surface area/gate area), the t_bd does not apparently decrease in a certain antenna ratio region. The difference between the degradation rate of Q_bd and t_bd along r is explained by taking into account the r- and time dependence of gate current density under constant-voltage stress J and the rand J-dependence of Q_bd     

Accelerated testing of SiO2 reliability

This paper compares several popular accelerated test methods for projecting SiO₂ lifetime distribution or failure rate: constant-voltage and constant-current time-to-breakdown and charge-to-breakdown tests, ramp-voltage breakdown test, and ramp-current charge to-breakdown test. Charge trapping affects the electric field acceleration parameter for time-to-breakdown and the value of breakdown voltage. Practical considerations favor ramp breakdown testing for gate oxide defect characterization. The effective thinning model is used for defect characterization and the ramp-voltage breakdown test is shown to be superior to the ramp-current Q_BD test for extraction of the defect distribution. Measurement issues are also discussed     

On the role of holes in oxide breakdown mechanism in inverted nMOSFETs

Using constant voltage stresses carried out in the inversion regime on nMOS transistors, poly-Si gated to poly-SiGe gated devices are compared. It is shown that charge (and time) to breakdown is significantly increased by the use of silicon–germanium alloy as a gate material. The result is discussed from the anode hole injection and the hydrogen release mechanisms point of view by estimating the expected modifications of each defect generation probability. It is concluded that even in the absence of (minority/majority) hole carrier density at the anode/oxide interface, the hole distribution is likely to impact the breakdown mechanisms.     

Ultrathin gate oxide reliability: physical models, statistics, andcharacterization

The present understanding of wear-out and breakdown in ultrathin (t_ox < 5.0 nm) SiO₂ gate dielectric films and issues relating to reliability projection are reviewed in this article. Recent evidence supporting a voltage-driven model for defect generation and breakdown, where energetic tunneling electrons induce defect generation and breakdown will be discussed. The concept of a critical number of defects required to cause breakdown and percolation theory will be used to describe the observed statistical failure distributions for ultrathin gate dielectric breakdown. Recent observations of a voltage dependent voltage acceleration parameter and non-Arrhenius temperature dependence will be presented. The current understanding of soft breakdown will be discussed and proposed techniques for detecting breakdown presented. Finally, the implications of soft breakdown on circuit functionality and the applicability of applying current reliability characterization and analysis techniques to project the reliability of future alternative gate dielectrics will be discussed     

New insights in the relation between electron trap generation andthe statistical properties of oxide breakdown

In this paper it is demonstrated in a wide stress field range that breakdown in thin oxide layers occurs as soon as a critical density of neutral electron traps in the oxide is reached. It is proven that this corresponds to a critical hole fluence, since a unique relationship between electron trap generation and hole fluence is found independent of stress field and oxide thickness. In this way literature models relating breakdown to hole fluence or to trap generation are linked. A new model for intrinsic breakdown, based on a percolation concept, is proposed. It is shown that this model can explain the experimentally observed statistical features of the breakdown distribution, such as the increasing spread of the Q_BD-distribution for ultrathin oxides. An important consequence of this large spread is the strong area dependence of the Q_BD for ultrathin oxides     

Tunnel barrier properties of stressed ferromagnetic tunneljunctions

The oxide breakdown properties of ultra-thin (-1 nm) naturally oxidised Al₂O₃ tunnel barriers in magnetic tunnel junctions were studied using ramped and constant stress experiments. During stress measurements at 1.35 V, a fast breakdown of the junction was observed. The time-to-breakdown is evaluated using Weibull statistics, as commonly utilised in SiO₂ reliability studies     

Statistics of successive breakdown events in gate oxides

The basic statistics for devices/circuits that can tolerate several breakdown (BD) events without failure are derived. All the presented results are analytical and do not rely on the validity of any model relating breakdown to defect generation. The single requirement is the uniform and uncorrelated generation of breakdown paths. Significant lifetime improvement is anticipated for low failure percentiles and Weibull slopes close to unity, as those found in oxides with the thickness required for sub-100-nm CMOS technologies. The presented results are validated using grouping experiments.     

Physical model for the power-law voltage and current acceleration of TDDB

As gate voltages scale in ultra-thin gate oxide CMOS and single carrier energy drops below the threshold required for defect generation, we postulate that multiple carrier induced defect generation becomes the dominant degradation mechanism resulting in a power-law voltage and local current acceleration of time-dependent dielectric breakdown (TDDB). Data from multiple technology nodes is presented to corroborate our hypothesis, which is also demonstrated to be consistent with literature reports from several different companies. To the best of our knowledge, this is the first time the power-law local gate current acceleration is proposed in contrast to earlier formulations based on total gate current.     

Reliability of ultrathin silicon dioxide under combined substratehot-electron and constant voltage tunneling stress

An experimental investigation of breakdown and defect generation under combined substrate hot-electron and tunneling electrical stress of silicon oxide ranging in thickness from 2.0 nm to 3.5 nm is reported. Using independent control of the gate current for a given substrate and gate bias, the time-to-breakdown of ultrathin silicon dioxide under substrate hot-electron stress is observed to be inversely proportional to the gate current density. The thickness dependence (2.0 nm to 3.5 nm) of substrate hot-electron reliability is reported and shown to be similar to constant voltage tunneling stress. The build-up of defects measured using stress-induced-leakage-current and charge-pumping for both tunneling and substrate hot-electron stress is reported. Based on these and previous results, a model is proposed to explain the time-to-breakdown behavior of ultrathin oxide under simultaneous tunneling and substrate hot-electron stress. The results and model provide a coherent understanding for describing the reliability of ultrathin SiO₂ under combined substrate hot-electron injection and constant voltage tunneling stress     

Impact of the trapping of anode hot holes on silicon dioxide breakdown

Hot holes are injected from the anode and trapped in thin silicon dioxide using constant voltage stress at large gate voltage. By comparing oxides having trapped holes with oxides in which the holes were detrapped, it is shown that the presence of trapped holes does not affect the breakdown of the oxide. Furthermore, as the temperature during stress is increased, less hole trapping is observed whereas the charge-to-breakdown of the oxide is decreased. The results show that although the trapping of hot holes injected using anode hole injection (AHI) may be partly responsible for defect generation in silicon dioxide, breakdown cannot be limited by the number of holes trapped in the oxide.     

Characteristics of sub-1/4-μm gate surface channel PMOSFET'susing a multilayer gate structure of boron-doped poly-Si on thinnitrogen-doped poly-Si

This paper reports the effects of a new p⁺ gate structure (MBN gate) on the properties of surface channel PMOSFET's with an extremely thin gate oxide. The MBN gate is a multilayer gate structure of boron-doped poly Si on thin nitrogen-doped poly-Si. The thin nitrogen-doped Si layer effectively suppresses boron diffusion, so that the gate poly Si can be doped with boron in high concentration without the fear of boron penetration. Gate depletion effects are well suppressed. Effective hole mobility is improved due to the reduction of the initial interface state density. The hot-hole induced interface state generation is shown to be the dominant clause of degradation in the 1/4-μm level PMOSFET's, and less Gm degradation is found in the MBN-gate PMOSFET's than in conventional p⁺-gate PMOSFET's. Finally, with respect to the reliability of the gate oxide, a conventional p⁺ gate with boron penetration exhibits an increase in short-time defect related breakdown during constant-current FN stressing. Short-time defect-related breakdown is not observed in the MBN gate but a slight decrease in charge to breakdown     

Electrical performance and reliability improvement by using compositionally varying bi-Layer structure of PVD HfSi/sub x/O/sub y/ dielectric

The effect of a bi-layer structure by varying the Hf composition in Hf-silicate dielectric in improving the electrical performance and reliability of high-/spl kappa/ gate stack n-MOSFETs has been investigated. Introducing Hf-silicate with 19.5% of Hf composition at the bottom layer and 28.5% of Hf on the top of it reduces the leakage current dramatically, while it minimally sacrifices increase in equivalent oxide thickness. Moreover, the structure reduces defect generation rate under gate injection and improves breakdown voltage in comparison to the control samples. Increase in Si-O bonds at the bottom interface, decrease in Coulomb scattering, and increase in dielectric constant in the top layer have been attributed to the overall performance increase of the gate stack.