Nonlinear control of mechatronic systems with permanent-magnet DC motors

The current trends in development and deployment of advanced electromechanical systems have facilitated the unified activities in the analysis and design of state-of-the-art motion devices, electric motors, power electronics, and digital controllers. This paper attacks the motion control problem (stabilization, tracking, and disturbance attenuation) for mechatronic systems which include permanent-magnet DC motors, power circuity, and motion controllers. By using an explicit representation of nonlinear dynamics of motors and switching converters, we approach and solve analysis and control problems to ensure a spectrum of performance objectives imposed on advanced mechatronic systems. The maximum allowable magnitude of the applied armature voltage is rated, the currents are limited, and there exist the lower and upper limits of the duty ratio of converters. To approach design tradeoffs and analyze performance (accuracy, settling time, overshoot, stability margins, and other quantities), the imposed constraints, model nonlinearities, and parameter variations are thoroughly studied in this paper. Our goal is to attain the specified characteristics and avoid deficiencies associated with linear formulation. To solve these problems, an innovative controller is synthesized to ensure performance improvements, robust tracking, and disturbance rejection. One cannot neglect constraints, and a bounded control law is designed to improve performance and guarantee robust stability. The offered approach uses a complete nonlinear mechatronic system dynamics with parameter variations, and this avenue allows one to avoid the conservative results associated with linear concept when mechatronic system dynamics is mapped by a linear constant-coefficient differential equation. To illustrate the reported framework and to validate the controller, analytical and experimental results are presented and discussed. In particular, comprehensive analysis and design with experimental verification are performed for an electric drive. A nonlinear bounded controller is designed, implemented, and experimentally tested.     

Transfer-function matrix of multivariable systems with cascade and feedback controllers

Simple expressions relating the closed-loop transfer function matrix to the cascade and feedback controller matrices are derived for a multivariable system. An important result is deduced which can simplify some of the design procedures of linear multivariable systems.     

Modeling and simulation of VLSI digital systems

Discrete simulation of digital circuits is a vital tool in the design process. However, few people are aware of the modeling assumptions inherent in discrete simulation. Nor is there a widely accepted and consistent theory of modeling and simulation of discrete/digital systems. In this paper we concentrate on the basic ideas behind discrete modeling and present a discussion of the most popular algorithms used in writing simulators. In addition, we use the characteristics of discrete models to define the logic, functional, and behavioral levels of simulation. In closing, we discuss new issues in modeling and simulation.     

A VLSI Architecture and Algorithm for Lucas–Kanade-Based Optical Flow Computation

Optical flow computation in vision-based systems demands substantial computational power and storage area. Hence, to enable real-time processing at high resolution, the design of application-specific system for optic flow becomes essential. In this paper, we propose an efficient VLSI architecture for the accurate computation of the Lucas–Kanade (L-K)-based optical flow. The L-K algorithm is first converted to a scaled fixed-point version, with optimal bit widths, for improving the feasibility of high-speed hardware implementation without much loss in accuracy. The algorithm is mapped onto an efficient VLSI architecture and the data flow exploits the principles of pipelining and parallelism. The optical flow estimation involves several tasks such as Gaussian smoothing, gradient computation, least square matrix calculation, and velocity estimation, which are processed in a pipelined fashion. The proposed architecture was simulated and verified by synthesizing onto a Xilinx Field Programmable Gate Array, which utilize less than 40% of system resources while operating at a frequency of 55 MHz. Experimental results on benchmark sequences indicate 42% improvement in accuracy and a speed up of five times, compared to a recent hardware implementation of the L-K algorithm.      

Discretization of cascaded continuous-time controllers and uncertain systems

This paper presents a new method for the digital modeling of a continuous-time uncertain system and a new method for the digital redesign of a sampled-data uncertain system. The system matrices characterizing the state-space representation of the original uncertain system are assumed to be interval matrices. The Chebyshev quadrature formula together with the interval arithmetic are used for the digital interval modeling, and a dual concept of digital interval modeling is utilized to discretize a predesigned cascaded analog controller for robust digital control of a continuous-time uncertain system. Using the newly developed digital interval models and digitally redesigned controllers, the resulting dynamic states of the digitally controlled sampled-data uncertain systemsare able to closely match those of the originally analogously controlled continuous-time uncertain systems for a relatively longer sampling period.This work was supported inpart by the U.S. Army Research Office under Grant DAAG-55-98-1-0198.     

ATM in B-ISDN communication systems and VLSI realization

The Asynchronous Transfer Mode (ATM) is considered to be a key technology for B-ISDN. This paper discusses VLSI trends and how VLSI's can be applied to realize ATM switching node systems for B-ISDN. Implementing a practical ATM node system will require the development of technologies such as high-throughput ATM switch LSI's with up to 10 Gb/s capacity and SDH termination technology based on optical fiber transmission. An ATM traffic-handling mechanism with Quality of Service (QoS) controls such as ATM layer performance monitoring, virtual channel handling, usage parameter control, and VP shaping requires several hundred thousand logic gates and several megabytes of high-speed static RAM; VLSI's must be introduced if such mechanisms are to be implemented. ATM node system architecture is based on design principles of a building-block-type structure and hierarchical multiplexing. The basic ATM call handling module, the AHM, is composed mainly of a line termination block and a self-routing switch block; we analyzed this module from the viewpoint of the amount of hardware it requires. Finally, future ATM node systems are discussed on the basis of 0.2-μm VLSI development trends and hardware requirements such as the need for ultrahigh integration of logic gate with memory, multichip modules, and low power dissipation technology     

Quantifying and enhancing power awareness of VLSI systems

An increasingly important figure-of-merit of a VLSI system is "power awareness," which is its ability to scale power consumption in response to changing operating conditions. These changes might be brought about by the time-varying nature of inputs, desired output quality, or just environmental conditions. Regardless of whether they were engineered for being power aware, systems display variations in power consumption as conditions change. This implies, by the definition above, that all systems are naturally power aware to some extent. However, one would expect that some systems are "more" power aware than others. Equivalently, we should be able to re-engineer systems to increase their power awareness. In this paper, we attempt to quantitatively define power awareness and how such awareness can be enhanced using a systematic technique. We illustrate this technique by applying it to VLSI systems at several levels of the system hierarchy - multipliers, register files, digital filters, dynamic voltage-scaled processors, and data-gathering wireless networks. It is seen that, as a result, the power awareness of these preceding systems can be significantly enhanced leading to increases in battery lifetimes in the range of 60-200%     

Efficient VLSI Architecture for Soft-Decision Decoding of Reed–Solomon Codes

Reed–Solomon (RS) codes have very broad applications in digital communication and storage systems. The recently developed algebraic soft-decision decoding (ASD) algorithms of RS codes can achieve substantial coding gain with polynomial complexity. Among the ASD algorithms with practical multiplicity assignment schemes, the bit-level generalized minimum distance (BGMD) decoding algorithm can achieve similar or higher coding gain with lower complexity. ASD algorithms consist of two major steps: the interpolation and the factorization. In this paper, novel architectures for both steps are proposed for the BGMD decoder. The interpolation architecture is based on the newly proposed Lee-O'Sullivan (LO) algorithm. By exploiting the characteristics of the LO algorithm and the multiplicity assignment scheme in the BGMD decoder, the proposed interpolation architecture for a (255, 239) RS code can achieve 25% higher efficiency in terms of speed/area ratio than prior efforts. Root computation over finite fields and polynomial updating are the two main steps of the factorization. A low-latency and prediction-free scheme is introduced in this paper for the root computation in the BGMD decoder. In addition, novel coefficient storage schemes and parallel processing architectures are developed to reduce the latency of the polynomial updating. The proposed factorization architecture is 126% more efficient than the previous direct root computation factorization architecture.      

Permanent-magnet linear actuator for static and reciprocatingshort-stroke electromechanical systems

With the rapid progress in permanent-magnet technology, through the use of high-energy-density rare-earth materials a range of compact and high-performance linear actuators is now available. The paper presents simulated and experimental results from an investigation into the performance of such a device, in which the internal operating conditions are first modeled using a finite-element approach. Information obtained from this investigation is used, together with equations for both the electrical circuit and the mechanical motion, to enable both the static and the dynamic characteristics to be predicted. The most significant parameters affecting the performance of the actuator are identified, and an optimized design is produced     

T-S fuzzy controllers for nonlinear interconnected systems with multiple time delays

This paper investigates the effectiveness of a passive tuned mass damper (TMD) and fuzzy controller in reducing the structural responses subject to the external force. In general, TMD is good for linear systems. We proposed here an approach of Takagi-Sugeno (T-S) fuzzy controller to deal with the nonlinear system. To overcome the effect of modeling error between nonlinear multiple time-delay systems and T-S fuzzy models, a robustness design of fuzzy control via model-based approach is proposed in this paper. A stability criterion in terms of Lyapunov's direct method is derived to guarantee the stability of nonlinear multiple time-delay interconnected systems. Based on the decentralized control scheme and this criterion, a set of model-based fuzzy controllers is then synthesized via the technique of parallel distributed compensation (PDC) to stabilize the nonlinear multiple time-delay interconnected system and the H/sup /spl infin// control performance is achieved at the same time. Finally, the proposed methodology is illustrated by an example of a nonlinear TMD system.     

一种与VLSI技术兼容的新型三维集成射频干扰滤波器

基于双π型电磁干扰滤波器(EMIF)的电路结构，借鉴集成电路超微细加工技术，提出了与等平面超大规模集成电路工艺完全兼容的一种新型三维集成射频干扰滤波器电路；简要介绍了该电路的绝缘层上金属薄膜三维集成制造方法，建立了电路传递函数模型，并进行了简要分析。该电路可用于制作适合未来电子系统高频化、小型化、轻型化和片式化信号处理的RF片上系统。     

Miriã: a CAD tool to synthesize multi-burst controllers for heterogeneous systems

This paper presents the Miriã tool that synthesizes multi-burst mode asynchronous controllers. An important feature of our solution is its capability of handling pairs of input burst that satisfy a set of properties. Such multi-burst may be formally described by two burst operators: OR and concurrence. A formal specification, which we called multi-burst graph (MBG), was developed to capture these features. The Miriã tool starts from a MBG specification producing asynchronous controllers as generalized RS architectures. This type of architecture handles efficiently edge-sensitive, non-monotonic (conditional) level sensitive, directed don’t-care and undetermined signals, which may occur when designing asynchronous circuits for heterogeneous systems. When compared to asynchronous controllers generated by the 3D tool, our experimental results frequently present a shorter cycle time, a reduced area and a faster interaction with the external environment.     

Cochannel interference probability for micro- and picocellular systems at 60 GHz

Cochannel interference probability is evaluated for micro- and picocellular systems considering the oxygen absorption at 60 GHz. For a picocellular system both desired and interfering signals are Rician distributed, whereas for a microcellular system the desired and interfering signals are Rician and Rayleigh distributed, respectively.<>     

Yield and performance enhancement through redundancy in VLSI and WSI multiprocessor systems

New challenges have been brought to fault-tolerant computing and processor architecture research because of developments in IC technology. One emerging area is development of architectures, built by interconnecting a large number of processing elements on a single chip or wafer. Two important areas, related to such VLSI processor arrays, are the focus of this paper; they are fault-tolerance and yield improvement techniques. Fault tolerance in these VLSI processor arrays is of real practical significance; it provides for much-needed reliability improvement. Therefore, we first describe the underlying concepts of fault tolerance at work in these multiprocessor systems. These precepts are useful to then present certain techniques that will incorporate fault tolerance integrally into the design. In the second part of the paper we discuss models that evaluate how yield enhancement and reliability improvement may be achieved by certain fault-tolerant techniques.     

Integrated design methodology of ball-screw driven servomechanisms with discrete controllers. Part I: Modelling and performance analysis

In order to ensure high-speed and high-precision specifications in ball-screw driven servomechanisms, an integrated design methodology in which driving mechanisms and motion controllers are designed simultaneously is required. As a prior study of the integrated design procedure, it is necessary to obtain not only mathematical models of servomechanisms but also proper formulation of the integrated design problem. In this paper, the feedback and feedforward controllers described in discrete-time domain are incorporated in the motion controller. Design requirements of the servomechanism such as stability, geometric errors, resonance of the driving mechanism, deformation of the structure, actuator saturation and so on are described in detail. Numerical simulations of the servomechanism performance according to design and operating parameters are performed based on the developed mathematical model. An accurate identification process of the driving mechanism is introduced to verify the mathematical subsystem model. Circular motion experiments are conducted to investigate interactions between parameters of the driving mechanism and controller gains, as well as analyze the influence of the interactions on the servomechanism performance. Results of the analysis and experiments let us understand accurate dynamic characteristics of the ball-screw driven servomechanism and render an integrated design possible.     

Identification and tuning fractional order proportional integral controllers for time delayed systems with a fractional pole

First order plus time delay model is widely used to model systems with S-shaped reaction curve. Its generalized form is the model with a single fractional pole replacing the integer order pole, which is believed to better characterize the reaction curve. In this paper, using time delayed system model with a fractional pole as the starting point, fractional order controllers design for this class of fractional order systems is investigated. Integer order PID and fractional order PI and [PI] controllers are designed and compared for these class of systems. The simulation comparison between PID controller and fractional order PI and [PI] controllers show the advantages of the properly designed fractional order controllers. Experimental results on a heat flow platform are presented to validate the proposed design method in this paper.     

High Efficiency Blue Organic LEDs Achieved By an Integrated Fluorescence–Interlayer–Phosphorescence Emission Architecture

This paper presents a new strategy to develop efficient organic light‐emitting devices (OLEDs) by doping fluorescent‐ and phosphorescent‐type emitters individually into two different hosts separated by an interlayer to form a fluorescence–interlayer–phosphorescence (FIP) emission architecture. One blue OLED with FIP emission structure comprising p‐bis(p‐N,N‐diphenylaminostyryl)benzene (DSA‐Ph) and bis[(4,6‐di‐fluorophenyl)‐pyridinate‐N,C²']picolinate (FIrpic) exhibiting a peak luminance efficiency of 15.8 cd A^?1 at 1.54 mA cm^?2 and a power efficiency of 10.2 lm W^?1 at 0.1 mA cm^?2 is successfully demonstrated. The results are higher than those of typical phosphorescent OLEDs with a single emission layer by 34% and 28%, respectively. From experimental and theoretical investigations on device performance, and the functions of the used emitters and interlayer, such enhancement should ascribe to the appropriate utilization of the two types of emitters. The fluorescent emitter of DSA‐Ph is used to facilitate the carrier transport, and thus accelerate the generation of excitons, while the phosphorescent emitter of FIrpic could convert the generated excitons into light efficiently. The method proposed here can be applied for developing other types of red, green, and white OLEDs.