一种能够提高驱动能力和ESD保护能力的亚微米CMOS输出晶体管的新设计方法

本文给出了一种新的输出驱动器的设计方法，利用这种方法可以有效地减少CMOS输出驱动器的面积、同时提高驱动能力和ESD可靠性，输出驱动器是由许多电路单元组成的，电路单元有正方形、六边形和八边形三种形状。利用这种新的设计风格制成的输出晶体管结构更加对称，在ESD过程中触发更一致。理论计算和实验证明，在非硅化物CMOS工艺中，在小的设计面积内，利用新的设计方法研制成的CMOS输出缓冲器的输出驱动能力更高，ESD保护能力更强，有许多电路单元组成的输出晶体管和传统的指状设计相比，栅电阻更低，漏电容更小。     

输入保护设计典型应用

论述了CMOS集成电路 ESD保护的必要性.接着介绍了CMOS集成电路ESD保护的各种设计技术,包括电流分流技术、电压箝位技术、电流均衡技术、ESD设计规则、ESD注入掩膜等,采用适当的ESD保护技术,1.2μm CMOS集成电路的ESD能力可以达到2000V.     

CMOS集成电路ESD设计

主要介绍了人体的静电模型和IC中ESD(Electric Static Discharge)保护设计的防护电路以及注意事项,包括输入端口两级ESD保护结构和版图要求,输出端、电源与地之间的ESD保护设计,ESD保护可以增强电路的可靠性。同时简要介绍了输入、输出端口电源、地,以及必须遵循的ESD规则。     

衬底触发层叠式NMOS实现混合I/O静电保护机制研究

衬底触发技术可以大幅度提高大尺寸NMOS器件的ESD级别.将衬底触发技术融合到层叠式NMOS器件中来产生衬底触发层叠式NMOS器件,理论分析结果表明衬底触发技术可以提高混合电压I/O电路中层叠式NMOS器件的ESD稳健性,基于0.35μm CMOS工艺的模拟结果表明应用带有衬底触发技术的层叠式NMOS器件的HBM模型ESD级别提高约60%,这就验证了衬底触发设计对提高混合电压I/O电路的ESD级是有效的.     

高清多媒体接口的静电放电保护设计

通过对静电放电(ESD)保护原理的研究,合理地选取了瞬态电压抑制二极管的参数,在Multisim软件中对ESD的保护电路进行了模型仿真。利用瞬态电压抑制二极管分别设计出高清多媒体接口的最小化传输差分信号保护电路、电源保护电路以及电平转换保护电路,并建立了ESD人体放电模型来对电路进行仿真分析,仿真结果表明本设计方案可行。     

一种单节锂电池保护IC设计

介绍了锂电池保护IC的工作原理,设计了适合CMOS工艺的锂电池保护电路,符合低功耗,高精度的要求。     

一种通用的CMOS单管脚振荡器

本文所描述的设计实现了基于0.18-μm CMOS工艺的单端振荡器.由于应用了本文中介绍的电路结构并且其片内集成了15pF用CMOS栅电容实现的电容(包括负载电容),芯片的面积非常小.这种电路可以工作在电源电压1.6-3.6V的电路中,要求的晶体振荡器的频率范围为3-30MHz.电路在27MHz,3.3V的振荡频率下电流功耗为900μA,产生轨到轨的方波输出,拥有与普通皮尔兹振荡器类似的应用灵活和简易的特点,在电路应用要求不十分严格的情况下,设计可以产生满足VLSI芯片数字时钟要求的非常好的波形.     

0.6 um工艺NMOS ESD保护电路版图优化

本文研究了在0.6um工艺下,数个版图参数对NMOS ESD保护器件性能的影响,并给出了这些版图参数适宜值的范围:提出了用于I/O PAD的ESD保护电路的版图优化方法,并证明了版图优化在提高ESD保护电路性能上的作用.     

浅谈锂离子电池保护电路应用中存在的问题及改进

单节锂离子电池保护电路的工作原理是通过对单节锂离子电池保护电路在应用中保护IC和CMOS容易损坏的问题分析得出的,要对锂离子保护IC和CMOS起到有效的保护作用就得对外围电路进行改进设计。     

栅接地NMOS管的ESD特性研究

ESD电路的作用是保护集成电路,使静电不损坏芯片内部电路,不造成集成电路失效,因此ESD研究是集成电路可靠性研究的重点方向之一。在新工艺下根据电路特点,设计GGNMOS器件的防护单元,为提供有效可靠的ESD防护起到至关重要的作用。     

A novel ESD power supply clamp circuit with double pull-down paths

Electrostatic-discharge(ESD)protection design is one of the key challenges of advanced CMOS processes.RC-triggered and MOSFET-based power supply ESD clamp circuits have been widely used to obtain the desired ESD protection ability.In this paper,a MOSFET-based ESD power clamp circuit with only10 ns RC time constant for 0.18-μm process is presented.A double pull-down path is proposed to avoid false triggering,reject power supply noise and reduce energy consumption.The performance of the novel clamp circuit is excellent,consuming very small layout area.The simulation results show that this clamp circuit can be used in industry.     

Area-efficient transient power-rail electrostatic discharge clamp circuit with mis-triggering immunity in a 65-nm CMOS process带误触发免疫力的节省版图面积型电源钳位静电放电保护电路

A novel, area-efficient transient power-rail electrostatic discharge (ESD) clamp circuit is proposed in this work. Current-mirror capacitors are used to reduce the layout area. Logic threshold voltages of inverters are modified to ensure a fully active on-state for the clamp device in ESD conditions. The proposed circuit reduces the layout area by about 56% compared with a circuit without current-mirror capacitors. Transmission line pulse (TLP) test results based on a 65-nm CMOS process demonstrate that the proposed circuit is an efficient on-chip ESD protection scheme for this process. In addition, the proposed circuit achieves a good immunity to mis-triggering with respect to fast power-up transitions.     

Design of a novel static-triggered power-rail ESD clamp circuit in a 65-nm CMOS process基于65纳米CMOS工艺的静态触发型电源钳位ESD保护电路设计

This work presents the design of a novel static-triggered power-rail electrostatic discharge (ESD) clamp circuit. The superior transient-noise immunity of the static ESD detection mechanism over the transient one is firstly discussed. Based on the discussion, a novel power-rail ESD clamp circuit utilizing the static ESD detection mechanism is proposed. By skillfully incorporating a thyristor delay stage into the trigger circuit (TC), the proposed circuit achieves the best ESD-conduction behavior while consuming the lowest leakage current (I_leak) at the normal bias voltage among all investigated circuits in this work. In addition, the proposed circuit achieves an excellent false-triggering immunity against fast power-up pulses. All investigated circuits are fabricated in a 65-nm CMOS process. Performance superiorities of the proposed circuit are fully verified by both simulation and test results. Moreover, the proposed circuit offers an efficient on-chip ESD protection scheme considering the worst discharge case in the utilized process.     

一种用于线性稳压器的限流电路

介绍一种电路结构简单、限流保护功能可靠、可用于线性稳压电路的限流保护电路,在0.6μm CMOS工艺下流片,测量结果显示该限流电路可在驱动输出超过额定值(100mA)后,有效启动以保护电源芯片安全.     

人体静电放电(ESD)及保护电路的设计

随着集成电路及电子设备的广泛应用,人体静电放电的危害性日益引起人们的重视。首先介绍人体静电放电模型及测试方法,然后阐述几种新型集成化静电放电保护器件的原理与应用。     

一种计算机串行接口保护电路的设计

基于ESD保护的原理及TVS二极管的特性,设计了一种计算机串行接口的专用保护电路,并对电路板的PCB布线及器件的布置提出了一些原则要求,最后对此接口电路进行静电放电抗扰度试验。结果表明该保护电路具有一定的抗接触放电及空间放电能力,满足IEC61000-4-2标准的要求,此串行接口具有热插拔功能。     

低功耗多系列的锂离子电池保护IC

设计了一种CMOS工艺的锂离子电池保护芯片,采用整个电路工作在亚阈值区的电路设计,特别是基准电路和偏置电路,从而使电路具有非常低的功耗;采用电阻网络分压,使同一种型号可以产生不同系列。这种设计可以在较宽的电压范围内工作,且经仿真表明,结果是满足实际要求的。     

网络适配器静电放电问题分析

提出了网络适配器产品静电放电问题的分析及解决方法,并就器件的寄生电容及寄生电感参数对高速电路的影响进行分析总结,为高频滤波、防护电路的器件选型提供了一定的指导.     

A low power fully differential RF receiver front-end for 2.4 GHz wireless sensor networks

In this paper, a novel merged LNA-mixer denoted as LNMA is proposed. The proposed LNMA consisting of a folded cascode LNA using improved derivative superposition technique and folded double-balanced subthreshold mixer using capacitor cross-coupled common-gate transconductor and it is integrated with on-chip LC voltage controlled oscillator (LC-VCO). In LNMA, a diode and power clamp based on-chip ESD protection circuit is used to tolerate ESD current of human-body-model specifications. To evaluate its performance, it is implemented in 0.18-µm MMRF CMOS process with 1-V supply, studied through post layout simulation and compared the results with other reported works. It achieves higher conversion gain of 27 dB, lower noise figure of 9.5 dB, lower input return loss (S11) of − 20 dB, higher third-order input intercept point (IIP₃) of – 16 dBm and higher IIP₂ of + 29.9 dBm compared to the works reported in the literature. The on-chip oscillator has the lower phase noise of – 114 dBc/Hz. The proposed LNMA and the LC-VCO achieves the power consumptions of 1.6 and 1.72 mW, respectively at 1-V power supply.