共查询到17条相似文献,搜索用时 109 毫秒
1.
Analog Devices公司的AD6644是一种14位ADC(模数转换器),为实现下一代通信设备——可编程数字无线电接收机(通称软件无线电)提供了高性能。文中主要介绍了AD6644的性能特点和工作原理,也说明了它的一些极限参数并与其他相关产品作了比较。举例介绍了AD6644的在一种可行的软件无线电接收机系统中的实际应用,同时给出了应用电路图。 相似文献
2.
3.
4.
5.
6.
7.
软件无线电接收机多速率信号的多段处理方法研究 总被引:1,自引:1,他引:0
在软件无线电数字接收机中,为了支持多种速率的信号处理,通常采用分数倍重采样,在硬件实现时,非常耗时和耗资源,这也成为软件无线电数字接收机的难点。在分析传统实现模型的基础上,提出一种基于整数倍重采样的新方法,即按照一定的分段方法,实现多速率的多段动态处理,可以避免分数倍重采样,节省运算时间和硬件资源。通过Matlab仿真证明,该方法性能良好,实用可行,可以用于数字接收机的多速率处理系统,在其工程实现上有较大的参考意义。 相似文献
8.
数字下变频技术是软件无线电的关键技术之一.本文介绍了AD公司新近推出的高性能数字下变频(DDC)器件AD6636的主要特性和工作原理,通过对宽带和窄带信号滤波器的仿真结果,提出了在数字中频接收机(DIFR)的设计中,能够利用AD6636片内高精度的数字正交下变频器和抽取滤波器,同时利用FPGA实现宽带滤波,可以弥补AD6636的宽带滤波性能较差的缺陷,从而实现宽带数字滤波. 相似文献
9.
10.
基于FPGA的数字中频系统设计 总被引:1,自引:0,他引:1
针对当前软件无线电技术发展的中频数字化,提出了一种基于FPGA的中频数字接收机设计方案。利用MATLAB仿真验证该方案实际可行,并用AD6645和低成本的EP2C5T144C8为核心芯片构建一个通用的数字接收机平台,更好地体现软件无线电体系结构的开放性和全面可编程性。从系统的参数选择到软硬件设计,给出了详细的说明。最后,进行了联合测试,给出了关键的测试结果,试验结果表明,该接收机系统结构简单,成本低,有良好的实用性和通用性。 相似文献
11.
12.
13.
Sungkyung Park 《International Journal of Electronics》2018,105(3):473-486
A composite radio receiver back-end and digital front-end, made up of a delta-sigma analogue-to-digital converter (ADC) with a high-speed low-noise sampling clock generator, and a fractional sample rate converter (FSRC), is proposed and designed for a multi-mode reconfigurable radio. The proposed radio receiver architecture contributes to saving the chip area and thus lowering the design cost. To enable inter-radio access technology handover and ultimately software-defined radio reception, a reconfigurable radio receiver consisting of a multi-rate ADC with its sampling clock derived from a local oscillator, followed by a rate-adjustable FSRC for decimation, is designed. Clock phase noise and timing jitter are examined to support the effectiveness of the proposed radio receiver. A FSRC is modelled and simulated with a cubic polynomial interpolator based on Lagrange method, and its spectral-domain view is examined in order to verify its effect on aliasing, nonlinearity and signal-to-noise ratio, giving insight into the design of the decimation chain. The sampling clock path and the radio receiver back-end data path are designed in a 90-nm CMOS process technology with 1.2V supply. 相似文献
14.
15.
介绍了码分多址( CDMA)系统空时信号联合处理技术和软件无线电技术,提出了一种将CDMA空时(ST)处理软件化的方案,并从模数变换(A C)和数字信号处理(DSP)角度分析了实现软件无线电的前景。 相似文献
16.
介绍了一种基于软件无线电技术的中频数字接收机的实现方案,它主要由数字正交调谐器和数字科斯塔斯环构成,通过配置不同的软件即可实现不同频带、不同调制类型信号的全数字接收。 相似文献
17.
This article has provided a brief overview of the SigmaDelta ADC conversion technologies for SDRs. The wireless receiver challenges were identified, the ADC design considerations and SigmaDelta solutions were discussed, and a low-distortion CT BP SigmaDelta modulator architecture was presented. The article has shown that the proposed CT BP SigmaDelta modulator is suitable for implementing high-IF ADC, making possible the software radio in handhelds. The major challenges in implementing such a high-IF ADC are the power dissipation and the degree of configurability, programmability, and adaptability that can be achieved by applying digital tuning and adaptive calibration 相似文献