A 10 b 50 MHz pipelined CMOS A/D converter with S/H

A single 5 V, 10 b, 50 MHz pipelined CMOS analog-to-digital (A/D) converter with internal sample-and-hold (S/H) circuits was developed. The A/D converter features a newly developed S/H circuit with an 80 dB, 300 MHz operational amplifier, three-stage pipelined 4 b flash A/D converters with digital error correction functions, and double analog signal conversion paths whose operations are interleaved. The new A/D converter was fabricated with 0.8 μm CMOS technology     

Superconductive A/D converters

A number of superconductive A/D (analog/digital) converter designs that show promise for superiority in high-bandwidth or high-resolution applications are known. On the high-resolution side, counting-type converters appear quite attractive. Voltage-to-frequency and tracking A/D converters are reviewed in this category. On the ultra-high-bandwidth side (greater than about 1 GHz) the parallel-type A/D converters seem to be advantageous. A number of parallel periodic-threshold A/D converters that have been attempted over the years as well as a fully parallel (2^N-1 comparators) A/D converter are reviewed     

A high-speed and high-resolution CMOS comparator with three-stage preamplifier

The accuracy of A/D and D/A converters depend largely upon their inner comparators. To guarantee 12-bit high resolution for an A/D converter, a precise CMOS comparator consisting of a three-stage differential preamplifier together with a positive feedback latch is proposed. Circuit structure, gain, the principle of input offset voltage storage and latching time constant for the comparator will be analyzed and optimized in this article. With 0.5 μm HYNIX mixed signal technology, the simulation result shows that the circuit has a precision of 400 μV at 20 MHz. The test result shows that the circuit has a precision of 600 μV at 16 MHz, and dissipates only 78 μW of power dissipation at 5 V. The size of the chip is 210 × 180 μm2. The comparator has been successfully used in a 10 MSPS 12-bit A/D converter. The circuit can be also used in a less than 13-bit A/D converter.     

A 5-bit building block for 20 MHz A/D converters

Describes a monolithic, fully parallel 5-bit A/D converter. The chip is fabricated using a standard metal-gate enhancement depletion NMOS technology with 7 /spl mu/m minimum features. The chip contains 31 strobed comparators, latches, combinational logic, a 5/spl times/31 bit ROM, TTL buffers and a 4-bit DAC. This makes it a building block for two-step parallel 8-bit A/D converters. Maximum conversion rate is 20 MHz and DC linearity is better than /SUP 1///SUB 4/ LSB for 80 mV quantization step size.     

An ultra low die area 8-b ADC and its generic calibration logic

The 8-bit voltage mode subrange A/D converter described in this paper operates in a mid-input signal frequency range of up to 20 MHz and requires at least an order of magnitude lower die area (0.06 mm²) than other A/D converters with a similar resolution. Moreover, it dissipates only 4.5 mW power and is supported by a calibration logic that is general enough to be used by several other measurement and instrumentation applications that require a real time adjustment of the amplitude and the level of their differential signals. This voltage mode subrange A/D converter architecture is actually an asynchronous two-step A/D converter that is based on a novel integer division operation. The current mode implementation of such an integer divider has already been employed by the authors in an innovative low area/power binary tree A/D conversion architecture. The voltage mode implementation of the integer divider allows the realization of the higher speed and lower power/area subrange A/D converter that is presented in this article.     

A 10-bit 200-MS/s CMOS parallel pipeline A/D converter

This paper describes a 10-bit 200-MS/s CMOS parallel pipeline analog-to-digital (A/D) converter that can sample input frequencies above 200 MHz. The converter utilizes a front-end sample-and-hold (S/H) circuit and four parallel interleaved pipeline component A/D converters followed by a digital offset compensation. By optimizing for power in the architectural level, incorporating extensively parallelism and double-sampling both in the S/H circuit and the component ADCs, a power dissipation of only 280 mW from a 3.0-V supply is achieved. Implemented in a 0.5-μm CMOS process, the circuit occupies an area of 7.4 mm². The converter achieves a differential nonlinearity and integral nonlinearity of ±0.8 LSB and ±0.9 LSB, respectively, while the peak spurious-free-dynamic-range is 55 dB and the total harmonic distortion better than 46 dB at a sampling rate of 200 MS/s     

A 10-b 15-MHz CMOS recycling two-step A/D converter

A two-step recycling technique is applied to implement a 10-b CMOS analog-to-digital (A/D) converter with a video conversion rate of 15 Msample/s. In a prototype digitally corrected converter, one capacitor-array multiplying digital-to-analog converter (MDAC) is used repeatedly as a sample-and-hold (S/H) amplifier, a DAC, and a residue amplifier so that the proposed converter may obtain linearity with the capacitor-array matching. An experimental fully differential A/D converter implemented using a double-poly 1-μm CMOS technology consumes 250 mW with a 5-V single supply, and its active die area, including all digital logic and output buffers, is 1.75 mm² (2700 mil²). Because the conversion accuracy of the proposed architecture relies on a capacitor-array MDAC linearity, high-resolution CMOS A/D conversions are feasible at high frequencies if sophisticated circuit techniques are further developed. For high-speed two-phase versions, the system can be easily modified to use multiplexing and/or pipelining techniques with a separate S/H amplifier and/or two separate flash converters     

A 16-b 160-kHz CMOS A/D converter using sigma-delta modulation

The design and measured performance of a third-order sigma-delta analog-to-digital (A/D) converter sampling at 10.24 MHz that achieves a 91-dB signal-to-noise-plus-distortion ratio (RMS/RMS) with a 160-kHz output rate are discussed. The converter consists of three cascaded first-order sigma-delta modulators and a fourth-order comb decimation filter. A special autozeroed integrator having low pole error is required to achieve the 10.24-MHz sampling rate and high S/N. The modulator is implemented with fully differential switched-capacitor circuits and is manufactured using a 1.5-μm double-metal double-poly CMOS process     

A 150-mW, 8-bit video-frequency A/D converter

The authors describe an 8-bit, extremely low-power, flash A/D converter LSI for video-frequency image signal processing. This converter uses a shallow-groove-isolated bipolar VLSI technology. It consumes only 150 mW, which is half the amount of the lowest power consumption so far reported. This low level of power consumption is achieved by the use of a comparator circuit, which is newly designed. This converter can digitize video signals of up to 10 MHz at a conversion rate of 30 MHz. A differential gain (DG) error of 1% and a differential phase (DP) error of less than 0.5/spl deg/ were observed.     

Reference refreshing cyclic analog-to-digital and digital-to-analog converters

A method of cyclic analog-to-digital (A/D) and digital-to-analog (D/A) conversion using switched-capacitor techniques is described. By periodically modifying the reference voltage to compensate for the nonideal signal-transfer-loop gain, it is possible in principle to build A/D and D/A converters whose linearity is independent of component ratios and that occupy only a small die area. These converters require two moderate-gain MOS operational amplifiers, one comparator, and a few capacitors. A test chip for A/D conversion was built and evaluated. The test data show that the A/D performs as a monotonic 13-bit converter with maximum 1-LSB differential and 2-LSB integral nonlinearity.     

A 14-bit 80-kHz sigma-delta A/D converter: modeling, design andperformance evaluation

The development is described of a sigma-delta A/D (analog-to-digital) converter. Included is a brief overview of sigma-delta conversion. The A/D converter achieves an 88.5-dB dynamic range and a maximum signal-to-noise ratio of 81.5 dB. The harmonic distortion is negligible. This level of performance is about 10 dB higher than previously reported results for oversampled A/D converters in this frequency range. The analog modulator uses a double-integration switched-capacitor architecture with an oversampling rate of 10.24 MHz. Transconductance amplifiers having a 160-MHz f_t were developed for the integrators. The circuit is implemented in a 1.75-μm 5-V CMOS process. The analog circuitry occupies 2 mm² of silicon area and consumes 75 mW of power. Some of the difficult problems associated with evaluating the performance of sigma-delta converters are described. The design of a sigma-delta development and performance evaluation system is presented. This system includes a custom interface board linking the chip to a Sun workstation, and extensive digital signal processing and analysis software     

A 10-bit pipelined switched-current A/D converter

A modified RSD algorithm has been implemented in a switched-current pipelined A/D converter. The offset insensitivity of the RSD Converter reduces the effect of several nonidealities proper to current copier cells. Moreover, the benefits resulting from the large tolerances inherent to the RSD algorithm and the pipelined architecture result in an improved conversion rate. Measurements on a first prototype give an integral nonlinearity error less than 0.8 LSB for 10-bit accuracy. Power dissipation is 20 mW and silicon area is 2.5 mm² . The measured sampling rate is 550 kS/s. It is an improvement by a factor of twenty compared to known equivalent CMOS switched-current converters. It is nevertheless still well below the predicted conversion rate of 4.5 MHz, which should be obtained once this A/D converter is integrated into an analog front-end. Full compatibility with standard digital technologies makes this kind of converter attractive for low power, medium-fast converters with 10-bit accuracy     

A 10-b 75-MSPS subranging A/D converter with integrated sample andhold

The design of a fully differential two-step analog-to-digital converter (ADC) is presented. A sample-and-hold (S/H) circuit based on a unity-gain feedback amplifier, flash ADCs driven by differential resistor ladders, and a differential digital-to-analog converter (DAC) combined with the subtractor are described. The chip has been fabricated in a standard high-speed bipolar process and, by extensively utilizing compensation techniques, achieves ±1 LSB integral nonlinearity and low harmonic distortion. A 75 Msample/s conversion rate not yet exceeded even by full-flash 10-b ADCs, has been achieved with a power consumption of 2 W. Due to the S/H circuit, the input bandwidth of 250 MHz; the effective resolution of 9 b at 5 MHz exhibits a gradual decrease over input frequency but still remains above 8 b up to 50 MHz     

A 12-b 5-Msample/s two-step CMOS A/D converter

Two-step flash architectures are an effective means of realizing high-speed high-resolution analog-to-digital converters (ADCs) because they can be implemented without the need for operational amplifiers having either high gain or a large output swing. Moreover, with conversion rates approaching half those of fully parallel designs, such half-flash architectures provide both a relatively small input capacitance and low power dissipation. The authors describe the design of a 12-b 5-Msample/s A/D converter that is based on a two-step flash topology and has been integrated in a 1-μm CMOS technology. Configured as a fully differential circuit, the converter performs a 7-b coarse flash conversion followed by a 6-b fine flash conversion. Both analog and digital error correction are used to achieve a resolution of 12 b. The converter dissipates only 200 mW from a single 5-V supply and occupies an area of 2.5 mm × 3.7 mm     

全差分BiCMOS采样/保持电路仿真设计

在全差分折叠式共栅-共源运放的基础上,设计了一款BiCMOS采样/保持电路。该款电路采用输入自举开关来提高线性度,同时设计的高速、高精度运放,其建立时间tS只有1.37 ns,提升了电路的速度和精度。所设计的运放中的双通道共模反馈电路使共模电压稳定输出时间tW约达1.5 ns。采用SMIC公司的0.25μmBiCMOS工艺参数,在Cadence Spectre环境下进行了仿真实验,结果表明,当输入正弦电压频率fI为10 MHz、峰-峰值UP-P为1 V,且电源电压VDD为3 V、采样频率fS为250 MHz时,所设计的采样/保持电路的无杂散动态范围SFDR约为-61 dB,信噪比SNR约为62 dB,整个电路的功耗PD约为10.85 mW,适用于10位低压、高速A/D转换器的设计。     

A monolithic charge-balancing successive approximation A/D technique

A new multiple-differential-voltage input, MOS, sampled-data, `charge-balance' comparator which can `weight' or scale each of many input voltage pairs has been developed. This comparator easily allows a differential analog input voltage capability on a monolithic A/D converter and greatly reduces the required number of resistors and decoding switches of a potentiometric successive approximation register (SAR) A/D design. An 8 bit converter has been built which uses 20 Rs and 32 switches as compared to the 256 Rs and 512 switches of a standard 2/SUP N/R ladder design. Measurements made on the 8 bit A/D converter are reported and indicate that at least 12 bit converters are possible with this technique. Therefore, a 13 bit converter has been designed which exhibits even greater component reductions-33 Rs and 64 switches instead of 8192 Rs and 16384 switches. A simple interface to microprocessors is provided for both converters which makes use of the standard logic signals of the control bus where the A/D is designed to appear as memory or an I/O port to the microprocessor. A new flexible reference voltage circuit is presented which, in combination with the analog differential input voltage feature, can accommodate arbitrary analog input voltage spans with any desired zero scale offset.     

Design of A/D converters with hierarchic networks

A methodology for designing analog to digital (A/D) converters based on a hierarchic network is explored. The principle of this methodology and design procedure are presented. The characteristics and performances of the converter are compared with the converter based on the Hopfield network. Two circuit models for the A/D converters are described in this paper. As a hierarchic network is used, the A/D converters designed have no local minima in their operation, With the method proposed in the paper, high bit number A/D converters can be easily designed, and the converters designed are fast in signal conversion and stable in operation     

A 10-b 20-Msample/s analog-to-digital converter

A 10-b 20-Msample/s analog-to-digital converter fabricated in a 0.9-μm CMOS technology is described. The converter uses a pipelined nine-stage architecture with fully differential analog circuits and achieves a signal-to-noise-and-distortion ratio (SNDR) of 60 dB with a full-scale sinusoidal input at 5 MHz. It occupies a 8.7 mm² and dissipates 240 mW     

An 800-MHz low-power direct digital frequency synthesizer with an on-chip D/a converter

An 800-MHz low-power direct digital frequency synthesizer (DDFS) with an on-chip digital-to-analog (D/A) converter is presented. The DDFS consists of a phase accumulator, two phase-to-sine converters, and a D/A converter. The high-speed operation of the DDFS is enabled by applying parallelism to the phase-to-sine converter and by including a D/A converter in a single chip. The on-chip D/A converter saves delay and power consumption due to interchip interconnections. The DDFS considerably reduces power consumption by using several low-power techniques. The pipelined parallel accumulator consumes only 22% power of a conventional pipelined accumulator with the same throughput. The quad line approximation (QLA) and the quantization and error ROM (QE-ROM) minimize the ROM to generate a sine wave. The QLA saves 4 bits of the sine amplitude by approximating the sine function with four lines. The QE-ROM quantizes the ROM data by magnitude and address and then it stores the quantized values and the quantization errors separately. The ROM size for a 9-bit sine output is only 368 bits. A DDFS chip is fabricated in a 0.35-/spl mu/m CMOS process. It consumes only 174 mW at 800 MHz with 3.3 V. The chip core area is 1.47 mm/sup 2/. The spurious-free dynamic range (SFDR) is 55 dBc.