倒装焊SnPb焊点热循环失效和底充胶的影响

采用实验方法,确定了倒装焊SnPb焊点的热循环寿命．采用粘塑性和粘弹性材料模式描述了SnPb焊料和底充胶的力学行为,用有限元方法模拟了SnPb焊点在热循环条件下的应力应变过程．基于计算的塑性应变范围和实验的热循环寿命,确定了倒装焊SnPb焊点热循环失效Coffin-Manson经验方程的材料参数．研究表明,有底充胶倒装焊SnPb焊点的塑性应变范围比无底充胶时明显减小,热循环寿命可提高约20倍,充胶后的焊点高度对可靠性的影响变得不明显．     

倒装焊封装中无铅焊点在封装工艺中的热机械力学分析

采用粘塑性Garofalo—Arrhenius模型描述无铅焊料的蠕变行为，确定了96．5Sn3.5Ag焊点材料的模型参数。采用与固化过程相关的粘弹性力学模型描述倒装焊底充胶的力学行为。利用有限元法模拟了无铅板上倒装焊在封装工艺及热循环条件下的应力应变行为。结果表明由于无铅技术在封装中的引入，封装工艺对倒装焊器件的影响更为重要。     

凸点材料的选择对器件疲劳特性的影响

为了研究凸点材料对器件疲劳特性的影响,采用非线性有限元分析方法、统一型黏塑性本构方程和Coffin-Manson修正方程,对Sn3.0Ag0.5Cu,Sn63Pb37和Pb90Sn10三种凸点材料倒装焊器件的热疲劳特性进行了系统研究,对三种凸点的疲劳寿命进行了预测,并对Sn3.0Ag0.5Cu和Pb90Sn10两种凸点材料倒装焊器件进行了温度循环试验.结果表明,仿真结果与试验结果基本吻合.在热循环过程中,凸点阵列中距离器件中心最远的焊点,应力和应变变化最剧烈,需重点关注这些危险焊点的可靠性;含铅凸点的热疲劳特性较无铅凸点更好,更适合应用于高可靠的场合;而且随着铅含量的增加,凸点的热疲劳特性越好,疲劳寿命越长.     

湿热环境下倒装焊无铅焊点的可靠性

对板上倒装芯片底充胶进行吸湿实验,并结合有限元分析软件研究了底充胶在湿敏感元件实验标准MSL—1条件下吸湿和热循环阶段的解吸附过程,测定了湿热环境对Sn3.8Ag0.7Cu焊料焊点可靠性的影响,并用蠕变变形预测了无铅焊点的疲劳寿命。结果表明:在湿热环境下,底充胶材料内部残留的湿气提高了焊点的应力水平。当分别采用累积蠕变应变和累积蠕变应变能量密度寿命预测模型时,无铅焊点的寿命只有1740和1866次循环周期。     

倒装焊焊点形态及其可靠性研究

本文采用Surface Evolver软件对倒装焊复合焊点的几何形态进行了模拟。通过非线性有限元方法研究有铅和无铅两种焊点在热循环作用下的应力应变关系，基于疲劳寿命C—M预测公式对焊点的热疲劳寿命进行预测与比较。     

球栅阵列封装中SnPb焊点的应力应变分析

基于SnPb焊料的统一粘塑性Anand本构模型,运用ANSYS有限元软件分析了球栅阵列封装中复合SnPb焊点在热循环过程中的应力、应变的分布,观察到SnPb焊料的蠕变行为和应力松弛现象,结果证明:外侧焊点经受的应力、应变范围比内侧焊点大;焊点的最高应力区域出现在Sn60Pb40焊料的最外缘处,最高应变区域出现在Pb90Sn10焊料与UBM层接触面的最上缘处.     

陶瓷封装倒装焊器件Sn-Pb微焊点的电迁移行为

高密度陶瓷封装倒装焊器件的焊点尺寸已降低至100μm以下,焊点电流密度达到10~4 A/cm~2以上,由此引发的电迁移失效成为不可忽视的问题。以陶瓷封装菊花链倒装焊器件为研究对象,开展了Sn10Pb90、Sn63Pb37焊点热电环境可靠性评估试验,通过电连接检测及扫描电子显微镜(SEM)等方法对焊点互连情况进行分析。结果表明,Sn63Pb37焊点阴极侧金属间化合物(IMC)增长明显,表现出明显的极化现象,IMC厚度的平方与通电时间呈线性关系。通电时间达到576 h后Sn63Pb37焊点阴极侧产生微裂纹,而Sn10Pb90焊点在通电576 h后仍未出现异常,表现出优异的电迁移可靠性。研究结果对于直径100μm微焊点的陶瓷封装倒装焊器件的应用具有重要的意义。     

模板对倒装焊焊点形态的影响及其可靠性研究

本文通过用于焊点形态预测软件SURFACE EVOLVER的输入数据文件,得到倒装焊焊点形态.参考模板开口指导说明(IPC-7525),拟定模板开口方案,得到相应的焊点形态.通过建立有限元模型,运用ANSYS软件对含铅焊点在热循环加载条件下的应力应变和疲劳寿命进行分析.根据预测得到的热疲劳寿命,找出了适合本文模型的模板结构参数,同时分析了其它设计与工艺参数和焊点可靠性之间的关系.     

热循环条件下空洞对PBGA焊点热疲劳寿命的影响

球栅阵列(ball grid array, BGA)封装器件的广泛应用使空洞对焊点可靠性的影响成为业界关注的焦点之一.采用非线性有限元分析方法和统一型粘塑性本构方程,以PBGA组装焊点为对象,建立了互连焊点热应变损伤的三维有限元模型,并基于修正的Coffin-Manson方程,分析了在热循环加裁条件下不同位置和大小的空洞对焊点疲劳寿命的影响.研究结果显示,位于原应力集中区的空洞将降低焊点疲劳寿命,基于应变失效机理,焊点裂纹易在该类空洞周围萌生和扩展;位于焊球中心和远离原应力集中区的空洞,在一定程度上可提高焊点的疲劳寿命.     

无铅倒装焊封装工艺中的芯片应力及开裂分析

采用粘塑性Garofalo-Arrhenius模型描述无铅焊料的非弹性力学行为,确定了Sn3.5Ag焊料该模型的材料参数。采用与固化过程相关的粘弹性力学模型描述倒装焊底充胶的力学行为。利用有限元仿真的方法,模拟了无铅倒装封装器件封装的工艺及可靠性测试。结果表明:由于无铅技术在封装中的引入,芯片破裂的可能性随之增加,破裂出现时裂纹的尺寸更小。     

The effects of underfill and its material models onthermomechanical behaviors of a flip chip package

In this paper, the effects of underfill on thermomechanical behavior of two types of flip chip packages with different bumping size and stand-off height were investigated under thermal cycling both experimentally and two-dimensional (2-D) finite element simulation. The materials inelasticity, i.e., viscoelasticity of underfill U8437-3 and viscoplasticity of 60 Sn40 Pb solder, were considered in the simulations. The results show that the use of underfill encapsulant increases tremendously (~20 times) the thermal fatigue lifetime of SnPb solder joint, weakens the effects of stand-off height on the reliability, and changes the deformation mode of the package. It was found that the thermal fatigue crack occurs in the region with maximum plastic strain range, and the Coffin-Manson type equation could then be used for both packages with and without underfill. Solder joint crack initiation occurred before delamination when using underfill with good adhesion (75 MPa) and the underfill delamination may not be a dominant failure mode in the present study. The interfacial stresses at the underfill/chip interface were calculated to analyze delamination sites, which agree with the results from acoustic image. Moreover, the effects of material models of underfill, i.e., constant elasticity (EC) and temperature dependent elasticity (ET) as well as the viscoelasticity (VE), on the thermomechanical behaviors of flip chip package were also studied in the simulation. The VE model gives comparatively large plastic strain range and large displacements in the shear direction, as well as decreased solders joint lifetime. The ET model gives similar results as the VE model and could be used instead of VE in simulations for the purpose of simplicity     

Influence of underfill materials on the reliability of coreless flip chip package

A flip chip package was assembled by using 6-layer laminated polyimide coreless substrate, eutectic Sn37Pb solder bump, two kinds of underfill materials and Sn_3.0Ag_0.5Cu solder balls. Regarding to the yield, the peripheral solder joints were often found not to connect with the substrate due to the warpage at high temperature, modification of reflow profile was benefit to improve this issue. All the samples passed the moisture sensitive level test with a peak temperature of 260 °C and no delamination at the interface of underfill and substrate was found. In order to know the reliability of coreless flip chip package, five test items including temperature cycle test (TCT), thermal shock test (TST), highly accelerated stress test (HAST), high temperature storage test (HTST) and thermal humidity storage test (THST) were done. Both of the two underfill materials could make the samples pass the HTST and THST, however, in the case of TCT, TST and HAST, the reliability of coreless flip chip package was dominated by underfill material. A higher Young’s modules of underfill, the more die crack failures were found. Choosing a correct underfill material was the key factor for volume production of coreless flip chip package.     

Parametric reliability analysis of no-underfill flip chip package

This research proposes a parametric analysis for a flip chip package with a constraint-layer structure. Previous research has shown that flip-chip type packages with organic substrates require underfill for achieving adequate reliability life. Although underfill encapsulant is needed to improve the reliability of flip chip solder joint interconnects, it will also increase the difficulty of reworkability, increase the packaging cost and decrease the manufacturing throughput. This research is based on the fact that if the thermal mismatch between the silicon die and the organic substrate could be minimized, then the reliability of the solder joint could be accordingly enhanced. This research proposes a structure using a ceramic-like material with CTE close to silicon, mounted on the backside of the substrate to constrain the thermal expansion of the organic substrate. The ceramic-like material could reduce the thermal mismatch between silicon die and substrate, thereby enhancing the reliability life of the solder joint. Furthermore, in order to achieve better reliability design of this flip chip package, a parametric analysis using finite element analysis is performed for package design. The design parameters of the flip chip package include die size, substrate size/material, and constraint-layer size/material, etc. The results show that this constraint-layer structure could make the solder joints of the package achieve the same range of reliability as the conventional underfill material. More importantly, the flip chip package without underfill material could easily solve the reworkability problem, enhance the thermal dissipation capability and also improve the manufacturing throughput     

Reliability analysis and design for the fine-pitch flip chip BGA packaging

The geometry of solder joints in the flip chip technologies is primarily determined by the associated solder volume and die/substrate-side pad size. In this study, the effect of these parameters on the solder joint reliability of a fine-pitched flip chip ball grid array (FCBGA) package is extensively investigated through finite element (FE) modeling and experimental testing. To facilitate thermal cycling (TC) testing, a simplified FCBGA test vehicle with a very high pin counts (i.e., 2499 FC solder joints) is designed and fabricated. By the vehicle, three different structural designs of flip chip solder joints, each of which consists of a different combination of these design parameters, are involved in the investigation. Furthermore, the associated FE models are constructed based on the predicted geometry of solder joints using a force-balanced analytical approach. By way of the predicted solder joint geometry, a simple design rule is created for readily and qualitatively assessing the reliability performance of solder joints during the initial design stage. The validity of the FE modeling is extensively demonstrated through typical accelerated thermal cycling (ATC) testing. To facilitate the testing, a daisy chain circuit is designed, and fabricated in the package for electrical resistance measurement. Finally, based on the validated FE modeling, parametric design of solder joint reliability is performed associated with a variety of die-side pad sizes. The results show that both the die/substrate-side pad size and underfill do play a significant role in solder joint reliability. The derived results demonstrate the applicability and validity of the proposed simple design rule. It is more surprising to find that the effect of the contact angle in flip chip solder joint reliability is less significant as compared to that of the standoff height when the underfill is included in the package.     

Failure analysis of solder bumped flip chip on low-cost substrates

Failure analyses of 63/37 Sn/Pb solder bumped flip chip assemblies with underfill encapsulant are presented in this study, Emphasis is placed on solder flowed-out, nonuniform underfill and voids, and delaminations. The X-ray, scanning acoustic microscope (SAM), and tomographic acoustic micro imaging (TAMI) techniques are used to analyze the failed samples. Also, cross sections are examined for a better understanding of the failure mechanisms. Furthermore, temperature dependent nonlinear finite element analyses together with fracture mechanics are used to determine the effects of underfill void sizes on the flip chip solder joint reliability     

Numerical Investigation of Underfill Failure Due to Phase Change of Pb-Free Flip Chip Solders During Board-Level Reflow

In this paper, the effects of phase change of Pb-free flip chip solders during board-level interconnect reflow are investigated using numerical technique. Most of the current Pb-free solder candidates are based on Sn and their melting temperatures are in the range of 220 $^{circ}$ C–240 $^{circ}$ C. Thus, Pb-free flip chip solders melt again during subsequent board-level interconnect (BGA) reflow cycle. Since solder volume expands as much as 4% during the phase change from solid to liquid, the volumetric expansion of solder in a predefined volume by chip, substrate, and underfill creates serious reliability issues. One issue is the shorting between neighboring flip chip interconnects by the interjected solder through underfill crack or delaminated interfaces. The authors have observed the interjection of molten solder and the interfacial failure of underfill during solder reflow process. In this paper, a flip chip package is modeled to quantify the effect of the volumetric expansion of Pb-free solder. Three possible cases are investigated. One is without existence of micro crack and the other two are with the interfacial crack between chip and underfill and the crack through the underfill. The strain energy release rate around the crack tip calculated by the modified crack closure integral method is compared with interfacial fracture toughness. Parametric studies are carried out by changing material properties of underfill and interconnect pitch. Also, the effects of solder interconnect geometry and crack length are explored. For the case with interfacial crack, the configuration of a large bulge with small pitch is preferred for the board-level interconnect, whereas a large pitch is preferred for cracks in the mid plane of the underfill.      

Mechanical loading of flip chip joints before underfill: the impact on yield and reliability

The underfill-facilitated migration from ceramic to lower cost laminate substrates has become a powerful enabler of direct chip attach by offering lower cost, greater electrical functionality, and a smaller system footprint over comparable packaging technologies. Once underfilled, flip chip on laminate has proven extremely reliable even in severe automotive environments. However, between the process steps of reflow and underfill cure, unprotected flip chip solder joints assembled to laminate boards are susceptible to damage and breakage if mishandled. Here, the survivability and long-term reliability of flip chip joints was studied over a range of applied strains. Mechanical loading of joints was applied via beam deflections of populated, but nonunderfilled, laminate boards. Electrical continuity was monitored before and after testing to determine when the load applied to the flip chip exceeded the joint fracture strength. The propensity for solder joint fracture was then calculated as a function of solder bump size and also as a function of strain rate. Analysis of the mechanical properties of solder revealed assembly strategies which reduce bump damage and eliminate yield loss during the process steps leading up to underfill cure. Both strained and unstrained units were then underfilled and cycled between −50 and +150 °C. While mechanical damage was evident in bump cross-sections of strained flip chip assemblies, the fatigue lives of underfilled solder joints were found to be independent of the size of mechanical loads applied before underfill.     

Dependence of Flip Chip Solder Reliability on Filler Settling

Thermomechanical reliability of solder joints in flip-chip packages is usually analyzed by assuming a homogeneous underfill ignoring the settling of filler particles. However, filler settling does impact flip chip reliability. This paper reports a numerical study of the influence of filler settling on the fatigue estimation of flip-chip solder joints. In total, nine underfill materials ( 35 vol% silica filler in three epoxies with three filler settling profiles for each epoxy) are individually introduced in a 2-D finite element (FE) model to compare the thermal response of flip chip solder joints that are surrounded by the underfill. The results show that the fatigue indicators for the solder joints (inelastic shear strain increments and inelastic shear strain energy density) corresponding to a gradual, nonuniform filler profile studied in this paper can be smaller than those associated with the uniform filler profile, suggesting that certain gradual filler settling profiles in conjunction with certain resin grades may favor a longer solder fatigue lifetime. The origin of this intriguing observation is in the fact that the solder fatigue indicators are a function of the thermal mismatch among the die, substrate, solder, and underfill materials. The thermal mechanics interplayed among these materials along with a gradual filler profile may allow for minimizing thermal mismatch; and thus lead to lower fatigue indicators.