Hybrid Morphology Processing Unit Architecture for Moving Object Segmentation Systems

Video segmentation is a key operation in MPEG-4 content-based coding systems. For real-time applications, hardware implementation of video segmentation is inevitable. In this paper, we propose a hybrid morphology processing unit architecture for real-time moving object segmentation systems, where a prior effective moving object segmentation algorithm is implemented. The algorithm is first mapped to pixel-based operations and morphological operations, which makes the hardware implementation feasible. Then the high computation load, which is more than 4.2 GOPS, can be overcome with a dedicated morphology engine and a programmable morphology PE array. In addition, the hardware cost, memory size, and memory bandwidth can be reduced with the partial-result-reuse concept. This chip is designed with TSMC 0.35 μm 1P4M technology, and can achieve the processing speed of 30 QCIF frames or 7,680 morphological operations per second at 26 MHz. Simulation shows that the proposed hardware architecture is efficient in both hardware complexity and memory organization. It can be integrated into any content-based video processing and encoding systems. Shao-Yi Chien was born in Taipei, Taiwan, R.O.C., in 1977. He received the B.S. and Ph.D. degrees from the Department of Electrical Engineering, National Taiwan University (NTU), Taipei, in 1999 and 2003, respectively. During 2003 to 2004, he was a research staff in Quanta Research Institute, Tao Yuan Shien, Taiwan. In 2004, he joined the Graduate Institute of Electronics Engineering and Department of Electrical Engineering, National Taiwan University, as an Assistant Professor. His research interests include video segmentation algorithm, intelligent video coding technology, image processing, computer graphics, and associated VLSI architectures. Bing-Yu Hsieh was born in Taichung, Taiwan, in 1979. He received the B.S.E.E and M.S.E.E degrees from National Taiwan University (NTU), Taipei, in 2001 and 2003, respectively. He joined MediaTek, Inc., Hsinchu, Taiwan, in 2003, where he develops integrated circuits related to multimedia systems and optical storage devices. His research interests include object tracking, video coding, baseband signal processing, and VLSI design. Yu-Wen Huang was born in Kaohsiung, Taiwan, in 1978. He received the B.S. degree in electrical engineering and Ph. D. degree in the Graduate Institute of Electronics Engineering from National Taiwan University (NTU), Taipei, in 2000 and 2004, respectively. He joined MediaTek, Inc., Hsinchu, Taiwan, in 2004, where he develops integrated circuits related to video coding systems. His research interests include video segmentation, moving object detection and tracking, intelligent video coding technology, motion estimation, face detection and recognition, H.264/AVC video coding, and associated VLSI architectures. Shyh-Yih Ma received the B.S.E.E, M.S.E.E, and Ph.D. degrees from National Taiwan University in 1992, 1994, and 2001, respectively. He joined Vivotek, Inc., Taipei County, in 2000, where he developed multimedia communication systems on DSPs. His research interests include video processing algorithm design, algorithm optimization for DSP architecture, and embedded system design. Liang-Gee Chen was born in Yun-Lin, Taiwan, in 1956. He received the BS, MS, and Ph.D degrees in Electrical Engineering from National Cheng Kung University, in 1979, 1981, and 1986, respectively. He was an Instructor (1981–1986), and an Associate Professor (1986–1988) in the the Department of Electrical Engineering, National Cheng Kung University. In the military service during 1987 and 1988, he was an Associate Professor in the Institute of Resource Management, Defense Management College. From 1988, he joined the Department of Electrical Engineering, National Taiwan University. During 1993 to 1994 he was Visiting Consultant of DSP Research Department, AT&T Bell Lab, Murray Hill. At 1997, he was the visiting scholar of the Department of Electrical Engineering, University, of Washington, Seattle. Currently, he is Professor of National Taiwan University. From 2004, he is also the Executive Vice President and the General Director of Electronics Research and Service Organization (ERSO) in the Industrial Technology Research Institute (ITRI). His current research interests are DSP architecture design, video processor design, and video coding system. Dr. Chen is a Fellow of IEEE. He is also a member of the honor society Phi Tan Phi. He was the general chairman of the 7th VLSI Design CAD Symposium. He is also the general chairman of the 1999 IEEE Workshop on Signal Processing Systems: Design and Implementation. He serves as Associate Editor of IEEE Trans. on Circuits and Systems for Video Technology from June 1996 until now and the Associate Editor of IEEE Trans. on VLSI Systems from January 1999 until now. He was the Associate Editor of the Journal of Circuits, Systems, and Signal Processing from 1999 until now. He served as the Guest Editor of The Journal of VLSI Signal Processing Systems for Signal, Image, and Video Technology, November 2001. He is also the Associate Editor of the IEEE Trans. on Circuits and Systems II: Analog and Digital Signal Processing. From 2002, he is also the Associate Editor of Proceedings of the IEEE. Dr. Chen received the Best Paper Award from ROC Computer Society in 1990 and 1994. From 1991 to 1999, he received Long-Term (Acer) Paper Awards annually. In 1992, he received the Best Paper Award of the 1992 Asia-Pacific Conference on Circuits and Systems in VLSI design track. In 1993, he received the Annual Paper Award of Chinese Engineer Society. In 1996, he received the Out-standing Research Award from NSC, and the Dragon Excellence Award for Acer. He is elected as the IEEE Circuits and Systems Distinguished Lecturer from 2001–2002.     

VLSI Architecture for Forward Discrete Wavelet Transform Based on B-spline Factorization

Based on B-spline factorization, a new category of architectures for Discrete Wavelet Transform (DWT) is proposed in this paper. The B-spline factorization mainly consists of the B-spline part and the distributed part. The former is proposed to be constructed by use of the direct implementation or Pascal implementation. And the latter is the part introducing multipliers and can be implemented with the Type-I or Type-II polyphase decomposition. Since the degree of the distributed part is usually designed as small as possible, the proposed architectures could use fewer multipliers than previous arts, but more adders would be required. However, many adders can be implemented with smaller area and lower speed because only few adders are on the critical path. Three case studies, including the JPEG2000 default (9, 7) filter, the (6, 10) filter, and the (10, 18) filter, are given to demonstrate the efficiency of the proposed architectures.Chao-Tsung Huang was born in Kaohsiung, Taiwan, R.O.C., in 1979. He received the B.S. degree from the Department of Electrical Engineering, National Taiwan University, Taipei, Taiwan, R.O.C., in 2001. He currently is working toward the Ph.D. degree at the Graduate Institute of Electronics Engineering, National Taiwan University. His major research interests include VLSI design and implementation for signal processing systems.Po-Chih Tseng was born in Tao-Yuan, Taiwan in 1977. He received the B.S. degree in Electrical and Control Engineering from National Chiao Tung University in 1999 and the M.S. degree in Electrical Engineering from National Taiwan University in 2001. He currently is pursuing the Ph.D. degree at the Graduate Institute of Electronics Engineering, Department of Electrical Engineering, National Taiwan University. His research interests include VLSI design and implementation for signal processing systems, energy-efficient reconfigurable computing for multimedia systems, and power-aware image and video coding systems.Liang-Gee Chen received the B.S., M.S., and Ph.D. degrees in electrical engineering from National Cheng Kung University, Tainan, Taiwan, R.O.C., in 1979, 1981, and 1986, respectively.In 1988, he joined the Department of Electrical Engineering, National Taiwan University, Taipei, Taiwan, R.O.C. During 1993–1994, he was a Visiting Consultant in the DSP Research Department, AT&T Bell Labs, Murray Hill, NJ. In 1997, he was a Visiting Scholar of the Department of Electrical Engineering, University of Washington, Seattle. Currently, he is Professor at National Taiwan University, Taipei, Taiwan, R.O.C. His current research interests are DSP architecture design, video processor design, and video coding systems.Dr. Chen has served as an Associate Editor of IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS FOR VIDEO TECHNOLOGY since 1996, as Associate Editor of the IEEE TRANSACTIONS ON VLSI SYSTEMS since 1999, and as Associate Editor of IEEE TRANSACTIONS CIRCUITS AND SYSTEMS II since 2000. He has been the Associate Editor of the Journal of Circuits, Systems, and Signal Processing since 1999, and a Guest Editor for the Journal of Video Signal Processing Systems. He is also the Associate Editor of the PROCEEDINGS OF THE IEEE. He was the General Chairman of the 7th VLSI Design/CAD Symposium in 1995 and of the 1999 IEEE Workshop on Signal Processing Systems: Design and Implementation. He is the Past-Chair of Taipei Chapter of IEEE Circuits and Systems (CAS) Society, and is a member of the IEEE CAS Technical Committee of VLSI Systems and Applications, the Technical Committee of Visual Signal Processing and Communications, and the IEEE Signal Processing Technical Committee of Design and Implementation of SP Systems. He is the Chair-Elect of the IEEE CAS Technical Committee on Multimedia Systems and Applications, During 2001-2002, he served as a Distinguished Lecturer of the IEEE CAS Society. He received the Best Paper Award from the R.O.C. Computer Society in 1990 and 1994. Annually from 1991 to 1999, he received Long-Term (Acer) Paper Awards. In 1992, he received the Best Paper Award of the 1992 Asia-Pacific Conference on circuits and systems in the VLSI design track. In 1993, he received the Annual Paper Award of the Chinese Engineer Society. In 1996 and 2000, he received the Outstanding Research Award from the National Science Council, and in 2000, the Dragon Excellence Award from Acer. He is a member of Phi Tan Phi.     

An Efficient Embedded Bitstream Parsing Processor for MPEG-4 Video Decoding System

In this paper, the bitstream parsing analysis and an efficient and flexible bitstream parsing processor are presented. The bitstream parsing analysis explores the critical part in bitstream parsing. Based on the result, the novel approaches to parse data partitioned bitstreams are presented. An efficient instruction set optimized for bitstream processing, especially for DCT coefficient decoding, is designed and the processor architecture can be programmed for various video standards. It has been integrated into an MPEG-4 video decoding system successfully and can achieve real time bitstream decoding with bitstream coded under 4CIF frame size with 30 fps, 8Mbps, which is the specification of MPEG-4 Advanced Simple Profile Level 5.Yung-Chi Chang was born in Kaohsiung, Taiwan, R.O.C., in 1975. He received the B.S. and M.S. degrees from the Department of Electrical Engineering, National Taiwan University, Taipei, Taiwan, R.O.C., in 1998 and 2000, respectively, where he is currently pursuing the Ph.D. degree in the Graduate Institute of Electrical Engineering. His research interests include video coding algorithms and VLSI architectures for image/video processing.Chao-Chih Huang was born in Taiwan, R.O.C., in 1977. He received the B.S. and M.S. degree in electrical engineering from National Taiwan University in 2000 and 2002, respectively. In Oct 2002, he has joined the multimedia team of Realtek Taiwan, to be a system design engineer and researched on video coding algorithms. His research interests include video compression/coding and image processing.Wei-Min Chao was born in Taoyuan, Taiwan, R.O.C., in 1977. He received the B.S. and M.S. degrees from the Department of Electronics Engineering, National Taiwan University in 2000 and 2002 separately. His research interests include video coding algorithms and VLSI architecture for image and video processing.Liang-Gee Chen was born in Yun-Lin, Taiwan, in 1956. He received the B.S., M.S., and Ph.D. degrees in electrical engineering from National Cheng Kung University, Tainan, Taiwan, in 1979, 1981, and 1986, respectively. He was an Instructor (1981–1986), and an Associate Professor (1986–1988) in the Department of Electrical Engineering, National Cheng Kung University. In the military service during 1987 to 1988, he was an Associate Professor in the Institute of Resource Management, Defense Management College. In 1988, he joined the Department of Electrical Engineering, National Taiwan University. During 1993 to 1994 he was a Visiting Consultant of DSP Research Department, AT&T Bell Lab, Murray Hill. In 1997, he was a visiting scholar of the Department of Electrical Engineering, University of Washington, Seattle. During 2001 to 2004, he was the first director of the Graduate Institute of Electronics Engineering (GIEE) in National Taiwan University (NTU). Currently, he is a Professor of the Department of Electrical Engineering and GIEE in NTU, Taipei, Taiwan. He is also the director of the Electronics Research and Service Organization in Industrial Technology Research Institute, Hsinchu, Taiwan. His current research interests are DSP architecture design, video processor design, and video coding systems.Dr. Chen has served as an Associate Editor of IEEE Transactions on Circuits and Systems for Video Technology since 1996, as Associate Editor of IEEE Transactions on VLSI Systems since 1999, and as Associate Editor of IEEE Transactions on Circuits and Systems II since 2000. He has been the Associate Editor of the Journal of Circuits, Systems, and Signal Processing since 1999, and a Guest Editor for the Journal of Video Signal Processing Systems. He is also the Associate Editor of the Proceedings of the IEEE. He was the General Chairman of the 7th VLSI Design/CAD Symposium in 1995 and of the 1999 IEEE Workshop on Signal Processing Systems: Design and Implementation. He is the Past-Chair of Taipei Chapter of IEEE Circuits and Systems (CAS) Society, and is a member of the IEEE CAS Technical Committee of VLSI Systems and Applications, the Technical Committee of Visual Signal Processing and Communications, and the IEEE Signal Processing Technical Committee of Design and Implementation of SP Systems. He is the Chair-Elect of the IEEE CAS Technical Committee on Multimedia Systems and Applications. During 2001–2002, he served as a Distinguished Lecturer of the IEEE CAS Society. He received the Best Paper Award from the R.O.C. Computer Society in 1990 and 1994. Annually from 1991 to 1999, he received Long-Term (Acer) Paper Awards. In 1992, he received the Best Paper Award of the 1992 Asia-Pacific Conference on circuits and systems in the VLSI design track. In 1993, he received the Annual Paper Award of the Chinese Engineer Society. In 1996 and 2000, he received the Outstanding Research Award from the National Science Council, and in 2000, the Dragon Excellence Award from Acer. He is a member of Phi Tan Phi.     

Platform-Based MPEG-4 SOC Design for Video Communications

An MPEG-4 video coding SOC design is presented in this paper. We adopt platform-based architecture with an embedded RISC core and efficient memory organization. A motion estimator supporting predictive diamond search and spiral full search is implemented for compromise between compression performance and design cost. The proposed data reuse scheme reduces required memory access bandwidth. For texture coding path, an interleaving DCT/IDCT scheduling with substructure sharing technique is proposed. Several key modules are integrated into an efficient platform in hardware/software co-design fashion. The cost-efficient video encoder SOC consumes 256.8 mW at 40 MHz and achieves real-time encoding of 30 CIF (352×288) frames per second. Yung-Chi Chang was born in Kaohsiung, Taiwan, R.O.C., in 1975. He received the B.S. and M.S. degrees from the Department of Electrical Engineering, National Taiwan University, Taipei, Taiwan, R.O.C., in 1998 and 2000, respectively, where he is currently pursuing the Ph.D. degree in the Graduate Institute of Electrical Engineering. His research interests include video coding algorithms and VLSI architectures for image/video processing. Wei-Min Chao was born in Taoyuan, Taiwan, R.O.C., in 1977. He received the B.S. and M.S. degrees from the Department of Electronics Engineering, National Taiwan University in 2000 and 2002 separately. His research interests include video coding algorithms and VLSI architecture for image and video processing. Chih-Wei Hsu was born in Taipei, Taiwan, in 1979. He received the B.S.E.E and M.S.E.E degrees from National Taiwan University (NTU), Taipei, in 2001 and 2003, respectively. He joined MediaTek, Inc., Hsinchu, Taiwan, in 2003, where he develops integrated circuits related to multimedia systems and optical storage devices. His research interests include object tracking, video coding, baseband signal processing, and VLSI design. Liang-Gee Chen was born in Yun-Lin, Taiwan, in 1956. He received the B.S., M.S., and Ph.D. degrees in electrical engineering from National Cheng Kung University, Tainan, Taiwan, in 1979, 1981, and 1986, respectively. He was an Instructor (1981-1986), and an Associate Professor (1986-1988) in the Department of Electrical Engineering, National Cheng Kung University. In the military service during 1987 to 1988, he was an Associate Professor in the Institute of Resource Management, Defense Management College. In 1988, he joined the Department of Electrical Engineering, National Taiwan University. During 1993 to 1994 he was a Visiting Consultant of DSP Research Department, AT & T Bell Lab, Murray Hill. In 1997, he was a visiting scholar of the Department of Electrical Engineering, University of Washington, Seattle. During 2001 to 2004, he was the first director of the Graduate Institute of Electronics Engineering (GIEE) in National Taiwan University (NTU). Currently, he is a Professor of the Department of Electrical Engineering and GIEE in NTU, Taipei, Taiwan. He is also the director of the Electronics Research and Service Organization in Industrial Technology Research Institute, Hsinchu, Taiwan. His current research interests are DSP architecture design, video processor design, and video coding systems. Dr. Chen has served as an Associate Editor of IEEE Transactions on Circuits and Systems for Video Technology since 1996, as Associate Editor of IEEE Transactions on VLSI Systems since 1999, and as Associate Editor of IEEE Transactions on Circuits and Systems II since 2000. He has been the Associate Editor of the Journal of Circuits, Systems, and Signal Processing since 1999, and a Guest Editor for the Journal of Video Signal Processing Systems. He is also the Associate Editor of the Proceedings of the IEEE. He was the General Chairman of the 7th VLSI Design/CAD Symposium in 1995 and of the 1999 IEEE Workshop on Signal Processing Systems: Design and Implementation. He is the Past-Chair of Taipei Chapter of IEEE Circuits and Systems (CAS) Society, and is a member of the IEEE CAS Technical Committee of VLSI Systems and Applications, the Technical Committee of Visual Signal Processing and Communications, and the IEEE Signal Processing Technical Committee of Design and Implementation of SP Systems. He is the Chair-Elect of the IEEE CAS Technical Committee on Multimedia Systems and Applications. During 2001--2002, he served as a Distinguished Lecturer of the IEEE CAS Society. He received the Best Paper Award from the R.O.C. Computer Society in 1990 and 1994. Annually from 1991 to 1999, he received Long-Term (Acer) Paper Awards. In 1992, he received the Best Paper Award of the 1992 Asia-Pacific Conference on circuits and systems in the VLSI design track. In 1993, he received the Annual Paper Award of the Chinese Engineer Society. In 1996 and 2000, he received the Outstanding Research Award from the National Science Council, and in 2000, the Dragon Excellence Award from Acer. He is a member of Phi Tan Phi.     

Traffic Models and Blocking Probabilities for Two-Fold and Three-Fold SDMA Communication Systems

Spectrum efficiency is a constant challenge in the design of wireless networks. Space-division-multiple-access (SDMA) is a promising approach to achieve higher spectral efficiency which reuses bandwidth via multiplexing signals based on their spatial signature. Several different studies have shown that SDMA can effectively improve system capacity in a mobile environment. In this paper, we present a new Markov chain traffic model for a duplicate-at-last (DL) approach [IEE Proceedings on Communication 146 (1999) 303] in two-fold and three-fold SDMA systems. Simplified blocking probability formulations for two-fold and three-fold SDMA are also derived. Simulations based on a common method of spatial separation check for channel allocation in SDMA are presented to evaluate the probability of successfully creating two-fold and three-fold SDMA channels. The simulation, as well as analytical, results indicate that the SDMA system can reduce the blocking probability of the calls and result in more traffic loading than a traditional cellular system. The results also show that our simplified approaches not only can reduce the computational complexity, but can also accurate approximate two-fold and three-fold SDMA performance. Wen-Jye Huang received the B.S. degree in electrical engineering from Tatung Institute of Technology, Taipei, Taiwan, in 1991, the M.S. degree in electrical engineering from Ohio University, Athens, OH, in 1997, and the Ph.D. degree in electrical engineering from The Pennsylvania State University, University Park, PA, in 2001. Since 2002, he joined the Department of Electrical Engineering, Chang Gung University, Kwei-San, Tao-Yuan, Taiwan, as an assistant professor. His research activities include smart antenna, SDMA, and MC-CDMA techniques. John F. Doherty received the B.S. degree (with honors) in engineering science from the College of Staten Island, City University of New York, in 1982, the M.Eng. degree in electrical engineering from Stevens Institute of Technology, Hoboken, NJ, in 1985, and the Ph.D. degree in electrical engineering from Rutgers University, New Brunswick, NJ, in 1990. He was an integrated circuit reliability engineer with IBM, from 1982 to 1984. From 1985 to 1988, he was member of the technical staff at AT&T Bell Laboratories, working in sonar signal processing. In 1990, he joined the Electrical and Computer Engineering Department, Iowa State University, Ames, as an assistant professor and Harpole Entair fellow. He is currently an associate professor of electrical engineering with The Pennsylvania State University, University Park. His current research activities include interference rejection in wireless communication systems, spatial-division multiple-access techniques, and radar target detection techniques. He is a former AFOSR summer faculty research fellow at the Rome Laboratory, Rome, NY, and an Army Research Office Young Investigator.     

Characteristic Investigation of New Pathological Elements

A characteristic investigation of the new pathological elements (i.e voltage mirror and current mirror) has been presented. Many nullor-mirror equivalences are explored. The circuit cascadability is discussed with nullor and mirror concepts. Also, the conventional inverse network transformation has been extended for applying to the circuits with current mirror output. To demonstrate the use of presented properties, practical examples have been given. The derived circuits have been verified with HSPICE simulation and the simulation results confirm with our theoretical prediction.Hung-Yu Wang was born in Kaohsiung, Taiwan, Republic of China, on January 4, 1969. He received the Ph.D. degree in optical sciences from National Central University, Chung-Li, Taiwan in 2002.Since 1993 he has worked on promoting the prototyping IC implementation of academic researches, and propelling the collaboration of the academia and industries in Chip Implementation Center (CIC), National Science Council of the Republic of China. In 2003 he became a researcher and the deputy director in Division of Chip Implementation Service of CIC. He is currently working on South Region Office of National Chip Implementation Center, National Applied Research Laboratories as a researcher and the department manager. His research interests are in current-mode circuits design, analog IC design and analog IP design.Ching-Ting Lee was born in Taoyuan, Taiwan, R.O.C., on November 1, 1949. He received his B.S. and M.S. in Electrical Engineering Department of the National Cheng-Kung University, Taiwan, in 1972 and 1974, respectively. He received Ph.D. degree in Electrical Engineering Department from the Carnegie-Mellon University, Pittsburgh, PA, in 1982.He worked on Chung Shan Institute of Science and Technology, before he joined the Institute of Optical Sciences, National Central University, Chung-Li, Taiwan, as a Professor in 1990. He works on National Cheng-Kung University as the dean of Electrical Engineering and Computer Science and the professor or the Institute of Microelectronics, Department of Electrical Engineering in 2003. His current research interests include theory, design, and application of guided-wave structures and devices for integrated optics and waveguide lasers. His research activities have also involved in the research concerning semiconductor lasers, photodetectors and high-speed electronic devices, and their associated integration for electrooptical integrated circuits. He received the outstanding Research Professor Fellowship from the National Science Council (NSC), R.O.C. in 2000 and 2002. He also received the Optical Engineering Medal from Optical Engineering Society and Distinguish Electrical Engineering professor award from Chinese Institute of Electrical Engineering Society in 2003.Chun-Yueh Huang was born in Taichung, Taiwan, Republic of China, on March 24, 1967. He received the B.S. degree in industrial education from National Chang Hwa Normal University, Chang Hwa, Taiwan in 1991, M.S. and Ph.D. degrees both in electrical engineering from the National Cheng Kung University, Tainan, Taiwan in 1993 and 1997, respectively. Since 1999 he has been with the Kan Shan University of Technology, where he is currently Associate Professor and Chairman of Department of Electronic Engineering. His biography is included in the 7th Edition (2003–2004) of Who’s Who in Science and Engineering.His current researches include current-mode circuits design, VLSI design, analog IC design and analog IP design.     

Reconfigurable Discrete Wavelet Transform Processor for Heterogeneous Reconfigurable Multimedia Systems

In this paper, a novel reconfigurable discrete wavelet transform processor architecture is proposed to meet the diverse computing requirements of future generation multimedia SoC. The proposed architecture mainly consists of reconfigurable processing element array and reconfigurable address generator, featuring dynamically reconfigurable capability where the wavelet filters and wavelet decomposition structures can be reconfigured as desired at run-time. The lifting-based reconfigurable processing element array possesses better computation efficiency than convolution-based architectures, and a systematic design method is provided to generate the hardware configurations of different wavelet filters for it. The reconfigurable address generator handles flexible address generation for data I/O access in different wavelet decomposition structures. A prototyping chip has been fabricated by TSMC 0.35 μm 1P4M CMOS process. At 50 MHz, this chip can achieve at most 100 M pixels/sec transform throughput, together with energy efficiency and unique reconfigurability features, proving it to be a universal and extremely flexible computing engine for heterogeneous reconfigurable multimedia systems.Po-Chih Tseng was born in Tao-Yuan, Taiwan in 1977. He received the B.S. degree in Electrical and Control Engineering from National Chiao Tung University in 1999 and the M.S. degree in Electrical Engineering from National Taiwan University in 2001. He currently is pursuing the Ph.D. degree at the Graduate Institute of Electronics Engineering, Department of Electrical Engineering, National Taiwan University. His research interests include VLSI design and implementation for signal processing systems, energy-efficient reconfigurable computing for multimedia systems, and power-aware image and video coding systems.Chao-Tsung Huang was born in Kaohsiung, Taiwan, R.O.C., in 1979. He received the B.S. degree from the Department of Electrical Engineering, National Taiwan University, Taipei, Taiwan, R.O.C., in 2001. He currently is working toward the Ph.D. degree at the Graduate Institute of Electronics Engineering, National Taiwan University. His major research interests include VLSI design and implementation for signal processing systems.Liang-Gee Chen (S’84–M’86–SM’94–F’01) received the B.S., M.S., and Ph.D. degrees in electrical engineering from National Cheng Kung University, Tainan, Taiwan, R.O.C., in 1979, 1981, and 1986, respectively. In 1988, he joined the Department of Electrical Engineering, National Taiwan University, Taipei, Taiwan, R.O.C. During 1993–1994, he was a Visiting Consultant in the DSP Research Department, AT&T Bell Labs, Murray Hill, NJ. In 1997, he was a Visiting Scholar of the Department of Electrical Engineering, University of Washington, Seattle. Currently, he is Professor at National Taiwan University, Taipei, Taiwan, R.O.C. His current research interests are DSP architecture design, video processor design, and video coding systems.Dr. Chen has served as an Associate Editor of IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS FOR VIDEO TECHNOLOGY since 1996, as Associate Editor of the IEEE TRANSACTIONS ON VLSI SYSTEMS since 1999, and as Associate Editor of IEEE TRANSACTIONS CIRCUITS AND SYSTEMS II since 2000. He has been the Associate Editor of the Journal of Circuits, Systems, and Signal Processing since 1999, and a Guest Editor for the Journal of VLSI Signal Processing Systems. He is also the Associate Editor of the PROCEEDINGS OF THE IEEE. He was the General Chairman of the 7th VLSI Design/CAD Symposium in 1995 and of the 1999 IEEE Workshop on Signal Processing Systems: Design and Implementation. He is the Past-Chair of Taipei Chapter of IEEE Circuits and Systems (CAS) Society, and is a member of the IEEE CAS Technical Committee of VLSI Systems and Applications, the Technical Committee of Visual Signal Processing and Communications, and the IEEE Signal Processing Technical Committee of Design and Implementation of SP Systems. He is the Chair-Elect of the IEEE CAS Technical Committee on Multimedia Systems and Applications. During 2001–2002, he served as a Distinguished Lecturer of the IEEE CAS Society. He received the Best Paper Award from the R.O.C. Computer Society in 1990 and 1994. Annually from 1991 to 1999, he received Long-Term (Acer) Paper Awards. In 1992, he received the Best Paper Award of the 1992 Asia-Pacific Conference on circuits and systems in the VLSI design track. In 1993, he received the Annual Paper Award of the Chinese Engineer Society. In 1996 and 2000, he received the Outstanding Research Award from the National Science Council, and in 2000, the Dragon Excellence Award from Acer. He is a member of Phi Tan Phi.     

Location-aware routing protocol with dynamic adaptation of request zone for mobile ad hoc networks

One possibility direction to assist routing in Mobile Ad Hoc Network (MANET) is to use geographical location information provided by positioning devices such as global positioning systems (GPS). Instead of searching the route in the entire network blindly, position-based routing protocol uses the location information of mobile nodes to confine the route searching space into a smaller estimated range. The smaller route searching space to be searched, the less routing overhead and broadcast storm problem will occur. In this paper, we proposed a location-based routing protocol called LARDAR. There are three important characteristics be used in our protocol to improve the performance. Firstly, we use the location information of destination node to predict a smaller triangle or rectangle request zone that covers the position of destination in the past. The smaller route discovery space reduces the traffic of route request and the probability of collision. Secondly, in order to adapt the precision of the estimated request zone, and reduce the searching range, we applied a dynamic adaptation of request zone technique to trigger intermediate nodes using the location information of destination node to redefine a more precise request zone. Finally, an increasing-exclusive search approach is used to redo route discovery by a progressive increasing search angle basis when route discovery failed. This progressive increased request zone and exclusive search method is helpful to reduce routing overhead. It guarantees that the areas of route rediscovery will never exceed twice the entire network. Simulation results show that LARDAR has lower routing cost and collision than other protocols. Tzay-Farn Shih was with Department of Electrical Engineering, National Taiwan University. Tzay-Farn Shih received the B.S. degree in Information Management from Chinese Culture University, Taiwan, in 1992, the M.S. degree in Computer Science Engineering from Tatung University, Taiwan, in 1996, and the Ph.D. degree in Electrical Engineering from National Taiwan University, Taiwan, in 2006. He is presently an assistant professor of Computer Science and Information Engineering at Chaoyang University of Technology, where he initially joined in August 2006. He is currently an overseas member of the Institute of Electronics, Information and Communication Engineers (IEICE). His current research interests include computer simulation, computer networks routing protocol, wireless networks, Mobile Ad Hoc networks and sensor networks. Hsu-Chun Yen was born in Taiwan, Republic of China, on May 29, 1958. He received the B.S. degree in electrical engineering from National Taiwan University, Taiwan, in 1980, the M.S. degree in computer engineering from National Chiao-Tung University, Taiwan, in 1982, and the Ph.D. degree in computer science from the University of Texas at Austin, U.S.A., in 1986. He is presently a Professor of Electrical Engineering at National Taiwan University, where he initially joined in August 1990. From August 1986 to July 1990, he was an Assistant Professor of Computer Science at Iowa State University, Ames, Iowa, U.S.A. His current research interests include Petri net theory, formal methods, design and analysis of algorithms, and complexity theory. Dr. Yen is an editor of International Journal of Foundations of Computer Science (IJFCS, World Scientific Publisher).     

Interactive Content-aware Video Streaming System with Fine Granularity Scalability

Video streaming with varying transmission bandwidth is becoming increasingly important. In this paper, an interactive video streaming system is proposed. Fine Granularity Scalability (FGS) is applied to be the streaming video format. The computational complexity of FGS coding is analyzed to explore an efficient FGS implementation. A new transmission model is proposed for the realization of a content-aware video streaming. At encoder side, the current MPEG-4 FGS coding flow is reordered such that the picture-level maximum can be acquired in advance and bit-plane data can be dynamically adapted. With these proposed hardware-oriented optimization approaches, a hardwired FGS block-level processing core is proposed to achieve a cost-effective solution to FGS implementation. The streaming server can adaptively decide quality-enhanced region by selective enhancement according to both object information from encoding side and user-defined region from receiver side. From the simulation results, it’s demonstrated that the proposed approach can provide better quality in users’ interest regions with no bit-rate or complexity overhead. Yung-Chi Chang was born in Kaohsiung, Taiwan, R.O.C., in 1975. He received the B.S., M.S., and Ph.D. degrees from the Department of Electrical Engineering, National Taiwan University, Taipei, Taiwan, R.O.C., in 1998, 2000, and 2005, respectively. He serves as senior engineer in SoC Solutions Dept., Vivotek Inc. now. His research interests include video coding algorithms and VLSI architectures for image/video processing. Chih-Wei Hsu was born in Taipei, Taiwan, in 1979. He received the B.S.E.E and M.S.E.E degrees from National Taiwan University (NTU), Taipei, in 2001 and 2003, respectively. He joined MediaTek, Inc., Hsinchu, Taiwan, in 2003, where he develops integrated circuits related to multimedia coding standard and digital consumer devices. His research interests include video coding, video processing and VLSI design. Wei-Min Chao was born in Taoyuan, Taiwan, R.O.C., in 1977. He received the B.S. and M.S. degrees from the Department of Electronics Engineering, National Taiwan University in 2000 and 2002 separately. His research interests include video coding algorithms and VLSI architecture for image and video processing. Liang-Gee Chen was born in Yun-Lin, Taiwan, in 1956. He received the B.S., M.S., and Ph.D. degrees in electrical engineering from National Cheng Kung University, Tainan, Taiwan, in 1979, 1981, and 1986, respectively. He was an Instructor (1981–1986), and an Associate Professor (1986–1988) in the Department of Electrical Engineering, National Cheng Kung University. In the military service during 1987 to 1988, he was an Associate Professor in the Institute of Resource Management, Defense Management College. In 1988, he joined the Department of Electrical Engineering, National Taiwan University. During 1993 to 1994 he was a Visiting Consultant of DSP Research Department, AT&T Bell Lab, Murray Hill. In 1997, he was a visiting scholar of the Department of Electrical Engineering, University of Washington, Seattle. During 2001 to 2004, he was the first director of the Graduate Institute of Electronics Engineering (GIEE) in National Taiwan University (NTU). Currently, he is a Professor of the Department of Electrical Engineering and GIEE in NTU, Taipei, Taiwan. He is also the director of the Electronics and Optoelectronics Research Laboratories in Industrial Technology Research Institute, Hsinchu, Taiwan. His current research interests are DSP architecture design, video processor design, and video coding systems. Dr. Chen has served as an Associate Editor of IEEE Transactions on Circuits and Systems for Video Technology since 1996, as Associate Editor of IEEE Transactions on VLSI Systems since 1999, and as Associate Editor of IEEE Transactions on Circuits and Systems II since 2000. He has been the Associate Editor of the Journal of Circuits, Systems, and Signal Processing since 1999, and a Guest Editor for the Journal of Video Signal Processing Systems. He is also the Associate Editor of the Proceedings of the IEEE. He was the General Chairman of the 7th VLSI Design/CAD Symposium in 1995 and of the 1999 IEEE Workshop on Signal Processing Systems: Design and Implementation. He is the Past-Chair of Taipei Chapter of IEEE Circuits and Systems (CAS) Society, and is a member of the IEEE CAS Technical Committee of VLSI Systems and Applications, the Technical Committee of Visual Signal Processing and Communications, and the IEEE Signal Processing Technical Committee of Design and Implementation of SP Systems. He is the Chair-Elect of the IEEE CAS Technical Committee on Multimedia Systems and Applications. During 2001–2002, he served as a Distinguished Lecturer of the IEEE CAS Society. He received the Best Paper Award from the R.O.C. Computer Society in 1990 and 1994. Annually from 1991 to 1999, he received Long-Term (Acer) Paper Awards. In 1992, he received the Best Paper Award of the 1992 Asia-Pacific Conference on circuits and systems in the VLSI design track. In 1993, he received the Annual Paper Award of the Chinese Engineer Society. In 1996 and 2000, he received the Outstanding Research Award from the National Science Council, and in 2000, the Dragon Excellence Award from Acer. He is a member of Phi Tan Phi.     

VLSI Architecture for Lifting-Based Shape-Adaptive Discrete Wavelet Transform with Odd-Symmetric Filters

In this paper, a VLSI architecture for lifting-based shape-adaptive discrete wavelet transform (SA-DWT) with odd-symmetric filters is proposed. The proposed architecture is comprised of a stage-based boundary extension strategy and the shape-adaptive boundary handling units. The former could reduce the complexity of multiplexers that are introduced to solve the shape-adaptive boundary extension. The latter consists of two multiplexers and can solve the shape-adaptive boundary extension locally without any additional register. Two case studies are presented, including the JPEG 2000 default (9, 7) filter and MPEG-4 default (9, 3) filter. According to comparison results with previous architectures, the efficiency of the proposed architectures is proven.Chao-Tsung Huang was born in Kaohsiung, Taiwan in 1979. He received the B.S. degree from the Department of Electrical Engineering, National Taiwan University, Taipei, Taiwan in 2001. He is currently working toward the Ph.D. degree at the Graduate Institute of Electronics Engineering, National Taiwan University. His major research interests include VLSI design and implementation for 1-D, 2-D, and 3-D Discrete Wavelet Transform. cthuang@video.ee.ntu.edu.twPo-Chih Tseng was born in Tao-Yuan, Taiwan in 1977. He received the B.S. degree in Electrical and Control Engineering from National Chiao Tung University in 1999 and the M.S. degree in Electrical Engineering from National Taiwan University in 2001. He currently is pursuing the Ph.D. degree at the Graduate Institute of Electronics Engineering, Department of Electrical Engineering, National Taiwan University. His research interests include VLSI design and implementation for signal processing systems, energy-efficient reconfigurable computing for multimedia systems, and power-aware image and video coding systems. pctseng@video.ee.ntu.edu.twLiang-Gee Chen (S84–M86–SM94–F01) received the B.S., M.S., and Ph.D. degrees in electrical engineering from National Cheng Kung University, Tainan, Taiwan, R.O.C., in 1979, 1981, and 1986, respectively.In 1988, he joined the Department of Electrical Engineering, National Taiwan University, Taipei, Taiwan, R.O.C. During 1993–1994, he was a Visiting Consultant in the DSP Research Department, AT&T Bell Labs, Murray Hill, NJ. In 1997, he was a Visiting Scholar of the Department of Electrical Engineering, University of Washington, Seattle. Currently, he is Professor at National Taiwan University, Taipei, Taiwan, R.O.C. His current research interests are DSP architecture design, video processor design, and video coding systems.Dr. Chen has served as an Associate Editor of IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS FOR VIDEO TECHNOLOGY since 1996, as Associate Editor of the IEEE TRANSACTIONS ON VLSI SYSTEMS since 1999, and as Associate Editor of IEEE TRANSACTIONS CIRCUITS AND SYSTEMS II since 2000. He has been the Associate Editor of the Journal of Circuits, Systems, and Signal Processing since 1999, and a Guest Editor for the Journal of Video Signal Processing Systems. He is also the Associate Editor of the PROCEEDINGS OF THE IEEE. He was the General Chairman of the 7th VLSI Design/CAD Symposium in 1995 and of the 1999 IEEE Workshop on Signal Processing Systems: Design and Implementation. He is the Past-Chair of Taipei Chapter of IEEE Circuits and Systems (CAS) Society, and is a member of the IEEE CAS Technical Committee of VLSI Systems and Applications, the Technical Committee of Visual Signal Processing and Communications, and the IEEE Signal Processing Technical Committee of Design and Implementation of SP Systems. He is the Chair-Elect of the IEEE CAS Technical Committee on Multimedia Systems and Applications. During 2001–2002, he served as a Distinguished Lecturer of the IEEE CAS Society. He received the Best Paper Award from the R.O.C. Computer Society in 1990 and 1994. Annually from 1991 to 1999, he received Long-Term (Acer) Paper Awards. In 1992, he received the Best Paper Award of the 1992 Asia-Pacific Conference on circuits and systems in the VLSI design track. In 1993, he received the Annual Paper Award of the Chinese Engineer Society. In 1996 and 2000, he received the Outstanding Research Award from the National Science Council, and in 2000, the Dragon Excellence Award from Acer. He is a member of Phi Tan Phi. lgchen@video.ee.ntu.edu.tw     

Run-Time Reconfigurable Systems for Digital Signal Processing Applications: A Survey

Todays digital signal processing (DSP) applications use computationally complex and/or adaptive algorithms and have stringent requirements in terms of speed, size, cost, power consumption, and throughput. Efficient hardware implementation techniques should be employed to meet the requirements of these applications. Run-Time Reconfiguration (RTR) is a promising technique for reducing the hardware required for implementing DSP systems as well as improving the performance, speed and power consumption of these systems. In this survey, we explain different issues in run-time reconfigurable systems and list the implemented systems which support run-time reconfiguration. We also describe different applications of run-time reconfiguration and discuss the improvements achieved by applying run-time reconfiguration.Alireza Shoa received his B.Sc degree in Electrical Engineering from Sharif University of Technology, Tehran, Iran in 2001 and M.A.Sc degree in Electrical Engineering from McMaster University, Hamilton, Canada in 2003. Currently, he is a PhD candidate in Electrical Engineering at McMaster University. His research interests include VLSI circuits for signal processing and communication applications and image and video processing.Shahram Shirani received his B.S. in Electrical Engineering from Isfahan University of Technology, Isfahan, Iran, and M.Sc. in Biomedical Engineering from Amirkabir University of Technology, Tehran, Iran, and Ph.D. in Electrical Engineering from University of British Columbia, Vancouver, Canada, in 1989, 1994 and 2000 respectively. Since 2000 he has been with the department of Electrical and Computer Engineering, McMaster University, where he is an assistant professor. His research interests include image and video compression, multimedia communications, and ultrasonic imaging. He is a member of technical committee of IEEE International Conference on Image Processing (ICIP). He is a licensed professional engineer and a member of Institute of Electrical and Electronics Engineers (IEEE).     

Survey on Block Matching Motion Estimation Algorithms and Architectures with New Results

Block matching motion estimation is the heart of video coding systems. During the last two decades, hundreds of fast algorithms and VLSI architectures have been proposed. In this paper, we try to provide an extensive exploration of motion estimation with our new developments. The main concepts of fast algorithms can be classified into six categories: reduction in search positions, simplification of matching criterion, bitwidth reduction, predictive search, hierarchical search, and fast full search. Comparisons of various algorithms in terms of video quality and computational complexity are given as useful guidelines for software applications. As for hardware implementations, full search architectures derived from systolic mapping are first introduced. The systolic arrays can be divided into inter-type and intra-type with 1-D, 2-D, and tree structures. Hexagonal plots are presented for system designers to clearly evaluate the architectures in six aspects including gate count, required frequency, hard-ware utilization, memory bandwidth, memory bitwidth, and latency. Next, architectures supporting fast algorithms are also reviewed. Finally, we propose our algorithmic and architectural co-development. The main idea is quick checking of the entire search range with simplified matching criterion to globally eliminate impossible candidates, followed by finer selection among potential best matched candidates. The operations of the two stages are mapped to the same hardware for resource sharing. Simulation results show that our design is ten times more area-speed efficient than full search architectures while the video quality is competitively the same. Yu-Wen Huang was born in Kaohsiung, Taiwan, in 1978. He received the B.S. degree in electrical engineering and the Ph.D. degree in electronics engineering from National Taiwan University, Taipei, in June 2000 and December 2004, respectively. He joined MediaTek, Inc., Hsinchu, Taiwan, in 2004, where he develops integrated circuits related to video coding systems. His research interests include video segmentation, moving object detection and tracking, intelligent video coding technology, motion estimation, face detection and recognition, H.264/AVC video coding, and associated VLSI architectures. Ching-Yeh Chen was born in Taipei, Taiwan, in 1980. He received the B.S. degree from the Department of Electrical Engineering, National Taiwan University, Taipei, Taiwan, in 2002. He currently is pursuing the Ph.D. degree at the Graduate Institute of Electronics Engineering, National Taiwan University. His research interests include intelligent video signal processing, global/local motion estimation, scalable video coding, and associated VLSI architectures. Chen-Han Tsai received the B.S. degree in electrical engineering from National Taiwan University in 2002. Now he is working toward the Ph.D. degree in the Graduate Institute of Electronics Engineering, National Taiwan University. His major research interests include face detection and recognition, motion estimation, H.264/AVC video coding, digital TV systems, and related VLSI architectures. Chun-Fu Shen received the B.S. and M.S. degrees in electrical engineering from National Taiwan University in 1996 and 1998, respectively. After two years of military service, he joined VIVOTEK, Inc., Taipei County, Taiwan, in 2000. He developed many video coding systems and IP camera products on DSP platforms and ASICs. His major research interests include JPEG, H.263, MPEG-4, and H.264/AVC coding systems, network camera SOC, and embedded systems. Liang-Gee Chen was born in Yun-Lin, Taiwan, in 1956. He received the B.S., M.S., and Ph.D. degrees in electrical engineering from National Cheng Kung University, in 1979, 1981, and 1986, respectively. He was an instructor (1981–1986), and an associate professor (1986–1988) in the Department of Electrical Engineering, National Cheng Kung University. In the military service during 1987 and 1988, he was an associate professor in the Institute of Resource Management, Defense Management College. From 1988, he joined the Department of Electrical Engineering, National Taiwan University. During 1993 to 1994 he was a visiting consultant of DSP Research Department, AT&T Bell Lab, Murray Hill. In 1997, he was the visiting scholar of the Department of Electrical Engineering, University, of Washington, Seattle. Currently, he is a professor of National Taiwan University. From 2004, he is also the executive vice president and the general director of Electronics Research and Service Organization (ERSO) in the Industrial Technology Research Institute (ITRI). His current research interests are DSP architecture design, video processor design, and video coding systems. Dr. Chen is a Fellow of IEEE. He is also a member of the honor society Phi Tau Phi. He was the general chairman of the 7th VLSI Design CAD Symposium. He was also the general chairman of the 1999 IEEE Workshop on Signal Processing Systems: Design and Implementation. He has served as the associate editor of IEEE Transactions on Circuits and Systems for Video Technology since 1996, the associate editor of IEEE Transactions on VLSI Systems since 1999, the associate editor of Journal of Circuits, Systems, and Signal Processing since 1999, and the guest editor of Journal of VLSI Signal Processing Systems for Signal, Image, and Video Technology since 2001. Now he is also the associate editor of IEEE Transactions on Circuits and Systems II: Analog and Digital Signal Processing and the associate editor of Proceedings of the IEEE. Dr. Chen received the Best Paper Awards from ROC Computer Society in 1990 and 1994. From 1991 to 2005, he received Long-Term (Acer) Paper Awards annually. In 1992, he received the Best Paper Award of the 1992 Asia-Pacific Conference on Circuits and Systems in VLSI design track. In 1993, he received the Annual Paper Award of Chinese Engineer Society. In 1996, he received the Outstanding Research Award from National Science Council (NSC) and the Dragon Excellence Award from Acer. He was elected as the IEEE Circuits and Systems Distinguished Lecturer from 2001–2002.     

New Paradigms in Wireless Communication Systems

This paper discusses what a new paradigm can be in wireless communication systems of the twenty-first century. First, it suggests two directions for the new paradigm; one is “micro- and nano-device communication system” which is the projected scenario considering that the entities in source and destination have been shrinking throughout the history of wireless communication systems. The second direction is “networked robot system”, which emerges as a natural extension of mobile ad hoc networking where the networking is closely related to motion control of robots. Secondly, it shows two interesting research topics, “the new communication protocol design” and “signal processing”, respectively, that arise in the wake of the fusion between the two directions in the novel communication paradigm. Finally, it considers a new science of wireless communications in the twenty-first century. Shinsuke Hara received the B.Eng., M.Eng. and Ph.D. degrees in communications engineering from Osaka University, Osaka, Japan, in 1985, 1987 and 1990, respectively. From April 1990 to March 1997, he was an assistant professor in the Department of Communication Engineering, School of Engineering, Osaka University, and from October 1997 to September 2005, he was an associate professor in the Department of Electronic, Information and Energy Engineering, Graduate School of Engineering, Osaka University. Since October 2005, he has been a professor in the Department of Physical Electronics and Informatics, Graduate School of Engineering, Osaka City University. In addition, from April 1995 to March 1996, he was a visiting scientist at Telecommunications and Traffic Control Systems Group, Delft University of Technology, Delft, The Netherlands. His research interests include wireless communications systems and digital signal processing. Hiroyuki Yomo received B.S. degree in communication engineering from Department of Communication Engineering, Osaka University, Osaka, Japan, in 1997, and M.S. and Ph.D. degrees in communication engineering from Department of Electronic, Information, and Energy Engineering, Graduate School of Engineering, Osaka University, Osaka Japan, in 1999 and 2002, respectively. From April 2002 to March 2004, he was a Post-doctoral Fellow in Department of Communication Technology, Aalborg University, Denmark. From April 2004 to September 2004, he was at Internet System Laboratory, NEC Corporation, Japan. Since October 2004, he has been an Assistant Research Professor in Center for TeleInfrastructure (CTIF), Aalborg University, Denmark. His main research interests are access technologies, radio resource management, and link-layer techniques in the area of short-range communication, cellular network, cognitive radio, and sensor network. Petar Popovski received the Dipl.-Ing. in electrical engineering and M.Sc. in communication engineering from the Faculty of Electrical Engineering, Sts. Cyril and Methodius University, Skopje, Republic of Macedonia, in 1997 and 2000, respectively. He received a Ph.D. degree from Aalborg University, Denmark, in 2004. From 1998 to 2001 he was a teaching and research assistant at the Institute of Telecommunications, Faculty of Electrical Engineering in Skopje. He is currently Assistant Professor at the Department of Communication Technology at the Aalborg University. His research interests are related to the PHY-MAC aspects of wireless protocols, wireless sensor networks, random access protocols, and network coding. Kazunori Hayashi received the B.E., M.E. and Ph.D. degrees in communication engineering from Osaka University, Osaka, Japan, in 1997, 1999 and 2002, respectively. He spent 3 months in 2000 at Aalborg University, Denmark, as a Visiting Scholar. Since 2002, he has been with the Department of Systems Science, Graduate School of Informatics, Kyoto University. He is currently an Assistant Professor there. His research interests include digital signal processing for communications systems.     

Theoretical Analysis and Performance of NC-PRMA Protocol for Multichannel Wireless Networks

In this paper, we analyze the effect of duplexing schemes on the throughput and the average packet dropping probability of a new multichannel wireless access protocol which allows for non-collision packet reservation multiple access with multiple channel (NC-PRMA/MC). N _C equal-capacity, orthogonal, traffic channels are shared by M mobile users on the uplink. Transmission attempts on the uplink are made by using time-frequency signaling in every frame, which enables transmission attempts of mobile users to be conveyed to the base station without collisions. Two kinds of duplexing schemes, frequency division duplexing and shared time division duplexing, are considered in the performance analysis. Using a discrete-time Markov chain analysis, we derive the analytic expressions for the average per channel throughput and the average packet dropping probability. Computer simulation results verify the analysis. Analytical evaluation and computer simulation show that NC-PRMA/MC with shared time division duplexing improves the channel capacity, which approaches the theoretical upper bound. Jenn-Kaie Lain born in Taiwan, R.O.C., in 1973. He received the B.E. degree in engineering science from the National Cheng Kung University, Tainan, Taiwan, R.O.C., and the Ph.D. degree in electrical engineering from the National Chung Cheng University, Chiayi, R.O.C., in 1995 and 2001, respectively. Since August 2001, he joined the faculty of Department of Computer Science and Information Engineering at Shu-Te University, Kaohsiung, Taiwan, R.O.C., as an Assistant Professor. He has been on the Faculty at National Yunlin University of Science and Technology, Yunlin, Taiwan, R.O.C., since August 2002 and currently holds the position of Assistant Professor in the Institute of Electronic and Information Engineering. His current research interest is in the field of coding and modulation as well as efficient receiver designs for broadband wireless communications. Jyh-HorngWen received his B.S. degree in Electronic Engineering from the National Chiao Tung University, Hsing-Chu, Taiwan, in 1979 and the Ph.D. degree in Electrical Engineering from the National Taiwan University, Taipei, in 1990. From 1981 to 1983, he was a Research Assistant with the Telecommunication Laboratory, Ministry of Transportation and Communications, Chung-Li, Taiwan. From 1983 to 1991, he was a Research Assistant with the Institute of Nuclear Energy Research, Taoyun, Taiwan. Since February 1991, he has been with the Institute of Electrical Engineering, National Chung Cheng University, Chia-Yi, Taiwan, first as an Associate Professor and, since 2000, as a Professor. He was also the Managing Director of the Center for Telecommunication Research, National Chung Cheng University, from Aug. 2000 to July 2004. Currently, he is also the Dean of General Affairs, National Chi Nan University. He is an Associate Editor of the Journal of the Chinese Grey System Association. His current research interests include computer communication networks, cellular mobile communications, personal communications, spread-spectrum techniques, wireless broadband systems, and gray theory. Prof.Wen is a member of the IEEE Communication Society, the IEEE Vehicular Technology Society, the International Association of Science and Technology for Development,the Chinese Grey System Association, and the Chinese Institute of Electrical Engineering.     

A State-Space Approach to Multiuser Parameters Estimation Using Central Difference for CDMA Systems

In this paper, it is shown that a state-space model applies to the code-division multiple-access (CDMA) channel, and Central Difference Filter (CDF) produces channel estimates with the minimum mean-square error (MMSE). This result may be used as compare to Extended Kalman Filter (EKF) which used as channel estimator in CDMA system. The main purpose of this paper is to compare robustness of channel estimator for realistic rapidly time-varying Rayleigh fading channels. To overcome the highly nonlinear nature of time delay estimation and also improve the accuracy, consistency and efficiency of channel estimation, an iterative nonlinear filtering algorithm, called the CDF has been applied in the field of CDMA System. The proposed channel estimator has a more near-far resistant property than the conventional Extended Kalman Filter (EKF). Thus, it is believed that the proposed estimator can replace well-known filters, such as the EKF. The Cramer-Rao lower bound (CRLB) is derived for the estimator, and simulation result show that it is nearly near-far resistant and clearly outperforms the EKF. Jang Sub Kim was born June 15, 1974, in Yeongdeok, Korea. He received the M.S. degree in school of electrical and computer engineering from Sungkyunkwan University, Seoul, Korea. He is currently with the School of Information and Communication Engineering, Sungkyunkwan University, where he was a Ph. D. student since 1999. His research interests include code-division multiple access, channel estimation, position location, and wireless communications. Seokho Yoon (S‘99–M‘1) received the B.S.E. (summa cum laude), M.S.E., and Ph.D. degrees in electrical engineering from KAIST, Daejeon, Korea, in 1997, 1999, and 2002, respectively. From April 2002 to June 2002, he was with the Department of Electrical Engineering and Computer Sciences, Massachusetts Institute of Technology, Cambridge, MA, and from July 2002 to February 2003, he was with the Department of Electrical Engineering, Harvard University, Cambridge, MA, as a Postdoctoral Research Fellow. In March 2003, he joined the School of Information and Communication Engineering, Sungkyunkwan University, Suwon, Korea, where he is currently an Assistant Professor. His research interests include spread spectrum systems, mobile communications, detection and estimation theory, and statistical signal processing. Dr. Yoon is a member of the IEEK and KICS. He was the recipient of a Bronze Prize at Samsung Humantech Paper Contest in 2000. Dong-Ryeol Shin (M‘97) was born in Seoul, Korea, in 1957. He received the B.S., M.S. and Ph.D degree in electrical engineering from the Sungkyunkwan University in 1980, and the Korea Advanced Institute of Science and Technology (KAIST) in 1982 and the Georgia Institute of Technology in 1992, respectively. During 1992-1994, he had worked for Samsung Data Systems, Ltd., Korea. Since 1994, he has been with network research group at the Sungkyunkwan University, Korea, as a professor. His current research interests include wireless communications and ubiquitous computing.     

Design of Current-Mode Square-Root Domain Band-Pass Filter with Reduced Voltage

A design technique for current-mode square-root domain band-pass filter fabricated in a 0.25 μ m CMOS process is presented. The basic building block consists of current-mode current mirrors, square-root circuits and capacitors, and in which the overall supply voltage is reduced by adopting low-voltage level-shift current mirror. Both of the simulation and measured results, which are in good agreement, indicate that the prototype of the band-pass provides tunable center frequency of 4–10 MHz with bias-current-tunable, −26.7 dB total harmonic distortion (THD), and approximately 1.598 mW power dissipation with a 1.5 V supply voltage. Advantages of the proposed filter include high frequency operation, tuneability, low supply voltage operation, low power consumption, and low third order intermodulation distortion. Gwo-Jeng Yu was born in Kaohsiung, Taiwan, R.O.C., in 1954. He received the B.S. and M.S. degrees in the Department Electronic Engineering in 1972 and 1976, respectively, from National Chiao Tung University, HsinChu, Taiwan, R.O.C., and he is currently working toward the Ph.D. degree in the Department of Electrical Engineering of National Cheng Kung University, Tainan, Taiwan, R.O.C. Since 1978, he has been on the Faculty of Institute of Cheng Shiu Technology, Kaohsiung, Taiwan, R.O.C., where he is currently a Associate Professor in the Department of Electronic Engineering. During 1979–1990, he was the Chairman of the Electronic Engineering Department and the Chairman of the Microelectronics and Information Technology Center during 1996–2000. His current researches include current-mode circuits design, analog IC design and VLSI circuit design. Chun-Yueh Huang was born in Taichung, Taiwan, Republic of China, on March 24, 1967. He received the B.S. degree in industrial education from the National Chang Hwa Normal University, Chang Hwa, Taiwan in 1991, M.S. and Ph.D. degrees both in electrical engineering from the National Cheng Kung University, Tainan, Taiwan, in 1993 and 1997, respectively. Since 1999 he has been with the Kan Shan University of Technology, where he is currently Associate Professor and Chairman of the Department of Electronic Engineering. His current researches include current-mode circuits design, VLSI design, analog IC design, and analog IP design. Jenn-Jiun Chen received the B.S. and M.S. degrees both in electrical engineering from the National Cheng Kung University, Tainan, Taiwan, in 2001 and 2003, respectively. His research interests are design and modeling of current mode circuit, low power analog circuit design, current mode filters, and instrumental amplifier in micro sensor applications. He received Chip Design Award from the Chip Implementation Center, National Applied Research Laboratories, in 2002. Bin-Da Liu received the B.S., M.S., and Ph.D. degrees all in electrical engineering from the National Cheng Kung University, Tainan, Taiwan, in 1973, 1975, and 1983, respectively. Since 1977 he has been on the faculty of the National Cheng Kung University, where he is currently Distinguished Professor in the Department of Electrical Engineering and Director of the SoC Research Center. During 1983–1984, he was a Visiting Assistant Professor in the Department of Computer Science, University of Illinois at Urbana-Champaign. During 1988–1992, he was the Director of Electrical Laboratories, National Cheng Kung University. He was the Associate Chair of the Electrical Engineering Department during 1996–1999 and the Chair during 1999–2002. Since 1995 he has been a consultant of the Chip Implementation Center, National Applied Research Laboratories. He has published more than 190 technical papers. He also contributed chapters in the book Neural Networks and Systolic Array Design (D. Zhang Ed. Singapore: World Scientific Publisher, 2002) and the book Accuracy Improvements in Linguistic Fuzzy Modeling (J. Casillas, O. Cordn, F. Herrera, and L. Magdalena Eds. Heidelberg, Germany: Springer-Verlag, 2003). He is currently a CAS Associate Editor of the IEEE Circuits & Devices Magazine and an Associate Editor of the IEEE Transactions on Circuits and Systems-I. His current research interests include low power circuit design, SoC system integration and verification, and VLSI implementation for fuzzy-neural networks and audio/video signal processors.     

Repacking on Demand for Hierarchical Cellular Networks

In mobile telecommunications operation, radio channels are scarce resources and should be carefully assigned. One possibility is to deploy the hierarchical cellular network (HCN). This paper studies a HCN channel assignment scheme called repacking on demand (RoD). RoD was originally proposed for wireless local loop networks. We expend this work to accommodate mobile HCN. A simulation model is proposed to study the performance of HCN with RoD and some previously proposed schemes. Our study quantitatively indicates that RoD may significantly outperform the previous proposed schemes. Hsien-Ming Tsai was born in Tainan, Taiwan, R.O.C., in 1973. He received the double B.S. degrees in Computer Science & Information Engineering (CSIE) and Communication Engineering, the M.S. degree in CSIE, and the Ph.D. degree in CSIE from National Chiao-Tung University (NCTU), Taiwan, in 1996, 1997, and 2002, respectively. He is currently a research specialist in Quanta Research Institute, Quanta Computer Inc. His research interests are in the areas of cellular protocols (UMTS/GPRS/GSM/DECT), cellular multimedia (MPEG-4 Audio/Speech), and embedded systems. He is an IEEE member. Ai-Chun Pang was born in Hsinchu, Taiwan, R.O.C., in 1973. She received the B.S., M.S. and Ph.D. degrees in Computer Science and Information Engineering from National Chiao Tung University (NCTU) in 1996, 1998 and 2002, respectively. She joined the Department of Computer Science and Information Engineering, National Taiwan University (NTU), Taipei, Taiwan, as an Assistant Professor in 2002. Her research interests include design and analysis of personal communications services network, mobile computing, voice over IP and performance modeling. Yung-Chun Lin was born in Kaohsiung, Taiwan, R.O.C., in 1978. He received the B.S. and M.S. degrees in Computer Science and Information Engineering (CSIE) from National Chiao-Tung University (NCTU), Taiwan, in 2001, 2003, respectively. He is currently pursuing the Ph.D. degree in CSIE. His research interests include design and analysis of a personal communications services network, the cellular protocols (UMTS/GPRS/GSM), and mobile computing. Yi-Bing Lin received his BSEE degree from National Cheng Kung University in 1983, and his Ph.D. degree in Computer Science from the University of Washington in 1990. From 1990 to 1995, he was with the Applied Research Area at Bell Communications Research (Bellcore), Morristown, NJ. In 1995, he was appointed as a professor of Department of Computer Science and Information Engineering (CSIE), National Chiao Tung University (NCTU). In 1996, he was appointed as Deputy Director of Microelectronics and Information Systems Research Center, NCTU. During 1997-1999, he was elected as Chairman of CSIE, NCTU. His current research interests include design and analysis of personal communications services network, mobile computing, distributed simulation, and performance modeling. Dr. Lin has published over 150 journal articles and more than 200 conference papers. Lin is an Adjunct Research Fellow of Academia Sinica, and is Chair Professor of Providence University. Lin serves as consultant of many telecommunications companies including FarEasTone and Chung Hwa Telecom. Lin is an IEEE Fellow and an ACM Fellow.     

Scheduling Sleeping Nodes in High Density Cluster-based Sensor Networks

In order to conserve battery power in very dense sensor networks, some sensor nodes may be put into the sleep state while other sensor nodes remain active for the sensing and communication tasks. In this paper, we study the node sleep scheduling problem in the context of clustered sensor networks. We propose and analyze the Linear Distance-based Scheduling (LDS) technique for sleeping in each cluster. The LDS scheme selects a sensor node to sleep with higher probability when it is farther away from the cluster head. We analyze the energy consumption, the sensing coverage property, and the network lifetime of the proposed LDS scheme. The performance of the LDS scheme is compared with that of the conventional Randomized Scheduling (RS) scheme. It is shown that the LDS scheme yields more energy savings while maintaining a similar sensing coverage as the RS scheme for sensor clusters. Therefore, the LDS scheme results in a longer network lifetime than the RS scheme. Jing Deng received the B.E. and M.E. degrees in Electronic Engineering from Tsinghua University, Beijing, P. R. China, in 1994 and 1997, respectively, and the Ph.D. degree in Electrical and Computer Engineering from Cornell University, Ithaca, NY, in 2002. Dr. Deng is an assistant professor in the Department of Computer Science at the University of New Orleans. From 2002 to 2004, he visited the CASE center and the Department of Electrical Engineering and Computer Science at Syracuse University, Syracuse, NY as a research assistant professor, supported by the Syracuse University Prototypical Research in Information Assurance (SUPRIA) program. He was a teaching assistant from 1998 to 1999 and a research assistant from 1999 to 2002 in the School of Electrical and Computer Engineering at Cornell University. His interests include mobile ad hoc networks, wireless sensor networks, wireless network security, energy efficient wireless networks, and information assurance. Wendi B. Heinzelman is an assistant professor in the Department of Electrical and Computer Engineering at the University of Rochester. She received a B.S. degree in Electrical Engineering from Cornell University in 1995 and M.S. and Ph.D. degrees in Electrical Engineering and Computer Science from MIT in 1997 and 2000 respectively. Her current research interests lie in the areas of wireless communications and networking, mobile computing, and multimedia communication. Dr. Heinzelman received the NSF Career award in 2005 for her work on cross-layer optimizations for wireless sensor networks, and she received the ONR Young Investigator award in 2005 for her research on balancing resource utilization in wireless sensor networks. Dr. Heinzelman was co-chair of the 1st Workshop on Broadband Advanced Sensor Networks (BaseNets '04), and she is a member of Sigma Xi, the IEEE, and the ACM. Yunghsiang S. Han was born in Taipei, Taiwan, on April 24, 1962. He received the B.S. and M.S. degrees in electrical engineering from the National Tsing Hua University, Hsinchu, Taiwan, in 1984 and 1986, respectively, and the Ph.D. degree from the School of Computer and Information Science, Syracuse University, Syracuse, NY, in 1993. From 1986 to 1988 he was a lecturer at Ming-Hsin Engineering College, Hsinchu, Taiwan. He was a teaching assistant from 1989 to 1992 and from 1992 to 1993 a research associate in the School of Computer and Information Science, Syracuse University. From 1993 to 1997 he was an Associate Professor in the Department of Electronic Engineering at Hua Fan College of Humanities and Technology, Taipei Hsien, Taiwan. From 1997 to 2004 he was with the Department of Computer Science and Information Engineering at National Chi Nan University, Nantou, Taiwan. He was promoted to Full Professor in 1998. From June to October 2001 he was a visiting scholar in the Department of Electrical Engineering at University of Hawaii at Manoa, HI, and from September 2002 to January 2004 he was the SUPRIA visiting research scholar in the Department of Electrical Engineering and Computer Science and CASE center at Syracuse University, NY. He is now with the Graduate Institute of Communication Engineering at National Taipei University, Taipei, Taiwan. His research interests are in wireless networks, security, and error-control coding. Dr. Han is a winner of 1994 Syracuse University Doctoral Prize. Pramod K. Varshney was born in Allahabad, India on July 1, 1952. He received the B.S. degree in electrical engineering and computer science (with highest honors), and the M.S. and Ph.D. degrees in electrical engineering from the University of Illinois at Urbana-Champaign in 1972, 1974, and 1976 respectively. Since 1976 he has been with Syracuse University, Syracuse, NY where he is currently a Professor of Electrical Engineering and Computer Science and the Research Director of the New York State Center for Advanced Technology in Computer Applications and Software Engineering. His current research interests are in distributed sensor networks and data fusion, detection and estimation theory, wireless communications, intelligent systems, signal and image processing, and remote sensing he has published extensively. He is the author of Distributed Detection and Data Fusion, published by Springer-Verlag in 1997 and has co-edited two other books. Dr. Varshney is a member of Tau Beta Pi and is the recipient of the 1981 ASEE Dow Outstanding Young Faculty Award. He was elected to the grade of Fellow of the IEEE in 1997 for his contributions in the area of distributed detection and data fusion. In 2000, he received the Third Millennium Medal from the IEEE and Chancellor's Citation for exceptional academic achievement at Syracuse University. He serves as a distinguished lecturer for the AES society of the IEEE. He is on the editorial board Information Fusion. He was the President of International Society of Information Fusion during 2001.     

Design of Square-Root Domain Filters

In this paper, a square-root domain band-pass filter and biquad filter which are based on the MOSFET square law are proposed. Both of the square-root domain filters operated at 2.5 V supply voltage are constituted by current mirrors, current-mode square-root circuits and capacitors. The circuits presented have been simulated and fabricated using 0.25 m CMOS process. Both of simulation and measured results which are in good agreement indicate that the center frequency f₀ is not only attainable at megahertz frequencies but also tunable electronically. The proposed circuits have the merits of high frequency operation, tuneability, low power supply voltage operation, low third order intermodulation distortion and low total harmonic distortion.Gwo-Jeng Yu was born in Kaohsiung, Taiwan, R.O.C., in 1954. He received the B.S. and M.S. degrees in the Department Electronic Engineering in 1972 and 1976, respectively, from National Chiao Tung University, HsinChu, Taiwan, R.O.C., and he is currently working toward the Ph.D. degree in the Department of Electrical Engineering of National Cheng Kung University, Tainan, Taiwan, R.O.C.Since 1978, he has been on the Faculty of Institute of Cheng Shiu Technology, Kaohsiung, Taiwan, R.O.C., where he is currently a Associate Professor in the Department of Electronic Engineering. During 1979–1990, he was the Chairman of the Electronic Engineering Department and the Chairman of the Microelectronics and Information Technology Center during 1996–2000.His current researches include current-mode circuits design, analog IC design and VLSI circuit design.Chun-Yueh Huang was born in Taichung, Taiwan, Republic of China, on March 24, 1967. He received the B.S. degree in industrial education from the National Chang Hwa Normal University, Chang Hwa, Taiwan in 1991, M.S. and Ph.D. degrees both in electrical engineering from the National Cheng Kung University, Tainan, Taiwan, in 1993 and 1997, respectively. Since 1999 he has been with the Kan Shan University of Technology, where he is currently Associate Professor and Chairman of the Department of Electronic Engineering. His current researches include current-mode circuits design, VLSI design, analog IC design, and analog IP design.Bin-Da Liu received the B.S., M.S., and Ph.D. degrees all in electrical engineering from the National Cheng Kung University, Tainan, Taiwan, in 1973, 1975, and 1983, respectively.Since 1977 he has been on the faculty of the National Cheng Kung University, where he is currently Distinguished Professor in the Department of Electrical Engineering and Director of the SoC Research Center. During 1983–1984, he was a Visiting Assistant Professor in the Department of Computer Science, University of Illinois at Urbana-Champaign. During 1988–1992, he was the Director of Electrical Laboratories, National Cheng Kung University. He was the Associate Chair of the Electrical Engineering Department during 1996–1999 and the Chair during 1999–2002. Since 1995 he has been a consultant of the Chip Implementation Center, National Applied Research Laboratories. He has published more than 190 technical papers. He also contributed chapters in the book Neural Networks and Systolic Array Design (D. Zhang, Ed. Singapore: World Scientific Publisher, 2002) and the book Accuracy Improvements in Linguistic Fuzzy Modeling (J. Casillas, O. Cordón, F. Herrera, and L. Magdalena, Eds. Heidelberg, Germany: Springer-Verlag, 2003). He is currently a CAS Associate Editor of the IEEE Circuits {&} Devices Magazine and an Associate Editor of the IEEE Transactions on Circuits and Systems-I. His current research interests include low power circuit design, SoC system integration and verification, and VLSI implementation for fuzzy-neural networks and audio/video signal processors.Jenn-Jiun Chen received the B.S. and M.S. degrees both in electrical engineering from the National Cheng Kung University, Tainan, Taiwan, in 2001 and 2003, respectively. His research interests are design and modeling of current mode circuit, low power analog circuit design, current mode filters, and instrumental amplifier in micro sensor applications. He received Chip Design Award from the Chip Implementation Center, National Applied Research Laboratories, in 2002.     

FGMOS Current Mirror: Behaviour and Bandwidth Enhancement

This paper presents a high performance, resistively compensated low voltage current mirror using floating gate MOSFETs (FGMOS). The compensation technique desensitizes the output current and input compliance voltage with respect to the process generated variations in the threshold voltages of the mirroring transistors. Theoretical and simulation results exhibit an appreciable increase in bandwidth of the current mirror for this compensation technique. The operation of these circuits has been verified using PSpice simulations for 0.5 μ m CMOS technology at a supply voltage of ±0.75 V. A part of this paper has appeared in IEEE APCCAS 2002 and NSM 2003. S. Sharma was born on 6th July 1967 at village Bhagta, district Udhampur, J and K (India). He received MSc Physics (Electronics) degree from University of Jammu in 1991 and was awarded University Gold Medal. After qualifying NET (CSIR), he joined as Lecturer in 1995 in the department of Physics and Electronics of the same University. He is presently a Senior Lecturer and pursuing for Ph.D. degree in the area of Analog Integrated Circuits. He has eight papers published in National/International Conferences/Journals. He is a life member of IETE (India). S.S. Rajput was born on July 1, 1957, at village Bashir Pur, District Bijnor UP India. He received his B. E. in Electronics and Communication Engineering and M. E. in Solid State Electronics Engineering from University of Roorkee, Roorkee, India (Now IIT, Roorkee) in 1978 and 1981 respectively and was awarded University gold medal in 1981. He earned his Ph.D. degree from Indian Institute of Technology, Delhi in 2002 and his topic of research was “Low voltage current mode analog circuit structures and their applications”. He joined National Physical Laboratory, New Delhi, India as Scientist B in 1983, where he is presently serving as Scientist EII. He has worked for the design, development, testing and fabrication of an instrument meant for space exploration under the ISRO-NPL joint program for development of scientific instruments for the Indian Satellite SROSS-C and SROSS-C2 missions. His research interests include low voltage analog VLSI, instrument design for space applications, Digital Signal Processing, Fault tolerant design, and fault detection. He has chaired the many sessions in Indian as well as International conferences. He is Fellow member of IETE (India). He has been awarded best paper award for IETE Journal of Education for the year 2002. He has delivered many invited talks on Low Voltage Analog VLSI. Few tutorials have been presented in International Conferences on his Research Work. He has more than 30 publications in national and international journals. L.K. Mangotra was born on 14th April 1944 at Jammu, India. He received M.Sc. (Physics) from University of Kashmir in 1968 and Ph.D. (High Energy Physics) from University of Jammu in 1974. He worked as Assistant Director in Forensic Laboratory of J and K Govt. from 1974–78. He joined Physics Department, University of Jammu as Lecturer in 1978 and became Professor in 1988. He has 131 publications in International Journals and 41 papers in proceedings of International/National Conferences. He has number of visits to foreign Universities in connection with research and has been awarded various Fellowships. He is a member of various Professional/Academic/Administrative bodies. Presently, Prof. Mangotra is an Advisor to University of Jammu for Modernization of University Infrastructure and Principal Investigator for Jammu University and Coordinator of All India Universities in the International Collaborative research project “ALICE” in High Energy Physics sponsored by Department of Atomic Energy and Department of Science and Technology, Govt. of India. S.S. Jamuar was born on 27th November 1949. He received his BSc. Engineering Degree in Electronics and Communication from Bihar Institute of Technology, Sindri in 1967, M. Tech and Ph.D. in Electrical Engineering from Indian Institute of Technology, Kanpur, India in 1970 and 1977 respectively. He worked as Research Assistant, Senior Research Fellow and Senior Research Assistant from 1969 to 1975 at IIT Kanpur. During 1975–76, he was with Hindustan Aeronautics Ltd., Lucknow. Subsequently he joined the Lasers and Spectroscopy Group in the Physics Department at IIT Kanpur, where he was involved in the design of various types of Laser Systems. He joined department of Electrical Engineering of IIT Delhi in 1977, where he became Professor in 1991. He is presently Professor in the department of Electrical and Electronic Engineering Department, Faculty of Engineering, University Putra Malaysia, Malaysia. His area of research interest includes Electronic Circuit Design, Instrumentation and Communication systems. He is recipient of Meghnad Saha Memorial Award 1976 from IETE, Distinguished Alumni Award from BIT Sindri in 1999. Dr. Jamuar is senior member of IEEE and Fellow member of IETE (India). He is presently the Chair for CASS Chapter of IEEE Malaysia Section.