Cache存储器的结构选择与实现

本文主要从结构、选择与实现等方面讨论Cache的设计问题.     

双核处理器性能最优的共享Cache划分

文中使用模拟器模拟的方法,测试IPC-CP对多道程序的吞吐率、加权加速比和公平性的影响.实验结果表明:以IPC最优为目标的Cache划分在三个评估指标中都优于以失效率最优为目标的Cache划分.其中,IPC-CP的吞吐率最高比失效率最优的Cache划分高出54%,平均高出27%.     

Design Space Exploration for NoC‐Style Bus Networks

With the number of IP cores in a multicore system‐on‐chip increasing to up to tens or hundreds, the role of on‐chip interconnection networks is vital. We propose a networks‐on‐chip‐style bus network as a compromise and redefine the exploration problem to find the best IP tiling patterns and communication path combinations. Before solving the problem, we estimate the time complexity and validate the infeasibility of the solution. To reduce the time complexity, we propose two fast exploration algorithms and develop a program to implement these algorithms. The program is executed for several experiments, and the exploration time is reduced to approximately 1/22 and 7/1,200 at the first and second steps of the exploration process, respectively. However, as a trade‐off for the time saving, the time cost (TC) of the searched architecture is increased to up to and , respectively, at each step compared with that of the architecture obtained through full‐case exploration. The reduction ratio can be decreased to 1/4,000 by simultaneously applying both the algorithms even though the resulting TC is increased to up to when compared with that obtained through full‐case exploration.     

An Ameliorated Design Method of ML‐AHB BusMatrix

The multi‐layer advanced high‐performance bus (ML‐AHB) BusMatrix proposed by ARM is an excellent architecture for applying embedded systems with low power. However, there is one clock cycle delay for each master in the ML‐AHB BusMatrix of the advanced microcontroller bus architecture (AMBA) design kit (ADK) whenever a master starts new transactions or changes the slave layers. In this letter, we propose an improved design method to remove the one clock cycle delay in the ML‐AHB BusMatrix of an ADK. We also remarkably reduce the total area and power consumption of the ML‐AHB BusMatrix of an ADK with the elimination of the heavy input stages.     

A New Automatic Compensation Network for System‐on‐Chip Transceivers

This paper proposes a new automatic compensation network (ACN) for a system‐on‐chip (SoC) transceiver. We built a 5 GHz low noise amplifier (LNA) with an on‐chip ACN using 0.18 µm SiGe technology. This network is extremely useful for today's radio frequency (RF) integrated circuit devices in a complete RF transceiver environment. The network comprises an RF design‐for‐testability (DFT) circuit, capacitor mirror banks, and a digital signal processor. The RF DFT circuit consists of a test amplifier and RF peak detectors. The RF DFT circuit helps the network to provide DC output voltages, which makes the compensation network automatic. The proposed technique utilizes output DC voltage measurements and these measured values are translated into the LNA specifications such as input impedance, gain, and noise figure using the developed mathematical equations. The ACN automatically adjusts the performance of the 5 GHz LNA with the processor in the SoC transceiver when the LNA goes out of the normal range of operation. The ACN compensates abnormal operation due to unusual thermal variation or unusual process variation. The ACN is simple, inexpensive and suitable for a complete RF transceiver environment.     

Germanium on sapphire substrates for system on a chip

Germanium on sapphire (GeOS) is proposed for system on a chip applications. Sapphire substrates are demonstrated to exhibit lower rf losses and superior crosstalk suppression compared with oxidised silicon handle wafers. Inductors on sapphire also show higher quality factor and better frequency response than those manufactured on an SOI platform. GeOS substrates have been manufactured by wafer bonding. Bond strengths of greater than 2900 mJ m⁻² have been obtained. Thin GeOS has been achieved by He/H₂ ion cut processes. A self-aligned W gate process on Ge has been established with processing temperature limited to 400 °C. P channel MOSTs exhibit low threshold voltage and a carrier mobility of about 400 cm² V⁻¹ s⁻¹.     

LBCCP:一种符合UNIX语义的文件缓存一致性协议及其证明

机群文件系统是机群操作系统的一个重要组成部分，而具有不同语义的文件系统的性能会有显著的差异。高效的客户端缓存协议是机群文件系统性能的关键问题之一。文章提出了一种新型文件缓存一致性协议，该协议通过扩展POSIX文件锁的API来实现UNIX语义模型，并利用I/O自动机理论证明了协议的正确性，在DCFS(Dawning Cluster Fils System)上实现了这个协议。     

总线监视器的设计

随着集成电路设计规模的不断增加，传统的验证方法学由于无法提供足够的能力来检查系统所有可能功能的正确性，已经不能满足SoC验证的需求。验证重用方法学是解决这一问题的有效途径。在SoC的验证过程中．利用总线监视器对片上总线上发生的事务进行实时监视，并将监视结果以机器可读的格式显示出来，从而可以帮助验证工程师有效地判断数据传输的正确性，达到验证单个模块和系统功能的目的。本文提出了一种SoC功能。验证平台中总线监视器的设计方法，并给出了具体的实现过程。     

系统芯片中低功耗测试的几种方法

在系统芯片可测试性设计中考虑功耗优化问题是当前国际上新出现的研究领域。在可测试性设计中考虑功耗的主要原因是数字电路在测试方式下的功耗比系统在正常工作方式下高很多。测试期间的功耗会引发系统成本上升，可靠性降低，成品率下降。本文介绍低功耗测试技术中的一些基本概念，对已有的几种主要的降低测试功耗方法进行分析，最后给出一种高性能微处理器的真速低功耗自测试方法。     

21世纪微电子芯片设计技术发展方向

文章主要阐述了21世纪微电子芯片技术及其发展的三个方向：1）遵照Moore定律和按比例缩小原理继续高速发展；2）系统芯片（SOC）；3）智能芯片，或赋予芯片更多的灵气。     

InVADE: Integrated Vasculature for Assessing Dynamic Events

Drug screening with simplified 2D cell culture and relevant animal testing fail to predict clinical outcomes. With the rising cost of drug development, predictive 3D tissue models with human cells are in urgent demand. Establishing vascular perfusion of 3D tissues has always been a challenge, but it is necessary to mimic drug transport and to capture complex interorgan crosstalk. Here, a versatile multiwell plate is presented empowered by built‐in microfabricated vascular scaffolds that define the vascular space and support self‐assembly of various parenchymal tissues. In this configuration, assembly and organ‐specific function of a metabolically active liver, a free‐contracting cardiac muscle, and a metastatic solid tumor are demonstrated, tracking organ function using noninvasive analysis techniques. By linking the 3D tumor and the liver tissue in series, it is demonstrated that the presence of liver tissue is crucial to correctly reveal the efficacy of a chemotherapeutic drug, Tegafur. Furthermore, the complete cancer metastasis cascade is demonstrated across multiple organs, where cancer cells escaping from the solid tumor can invade a distant liver tissue connected through a continuous vascular interface. This combinatory use of microfabricated scaffold onto a standard cell culturing platform can offer important insights into the mechanics of complex interorgan biological events.     

SystemC:一种新的系统建模语言

文章介绍了一种国外正在研究的新的系统建模语言SystemC，因其较好地结合了面向对象的设计方法和硬件建模的特点，从而有望解决系统建模和HW／SW协同设计中等一系列问题。     

基于RISC的16位嵌入式CPU的设计

介绍了一个嵌入式ＲＩＳＣ型ＰＣＵ。该ＣＰＵ采用哈佛结构、４级指令流水线、２０位指令字长和１６位数据字长,并设置了用于片内外部寄存器的高速接口。设计中采用Ｂｙｐａｓｓ技术解决了数据相关问题,开发了高效的结构化编程语言和相应的编译器。     

系统芯片的可测性设计

系统芯片SoC可以实现一个系统的功能,为了保证系统芯片的功能正确性与可靠性,在它的设计与制造的多个阶段必需进行测试。由于系统芯片的集成度高,结构和连接关系复杂,使得对它进行测试的难度越来越大,因此需要采用专门的测试结构。本文对系统芯片的可测性设计以及测试结构的设计方法等进行了介绍和综述。     

Performance evaluation of a routing algorithm based on Hopfield Neural Network for network-on-chip

Network on chip (NoC) has emerged as a solution to overcome the system on chip growing complexity and design challenges. A proper routing algorithm is a key issue of an NoC design. An appropriate routing method balances load across the network channels and keeps path length as short as possible. This survey investigates the performance of a routing algorithm based on Hopfield Neural Network. It is a dynamic programming to provide optimal path and network monitoring in real time. The aim of this article is to analyse the possibility of using a neural network as a router. The algorithm takes into account the path with the lowest delay (cost) form source to destination. In other words, the path a message takes from source to destination depends on network traffic situation at the time and it is the fastest one. The simulation results show that the proposed approach improves average delay, throughput and network congestion efficiently. At the same time, the increase in power consumption is almost negligible.     

Program Cache Busy Time Control Method for Reducing Peak Current Consumption of NAND Flash Memory in SSD Applications

In current NAND flash design, one of the most challenging issues is reducing peak current consumption (peak ICC), as it leads to peak power drop, which can cause malfunctions in NAND flash memory. This paper presents an efficient approach for reducing the peak ICC of the cache program in NAND flash memory — namely, a program Cache Busy Time (tPCBSY) control method. The proposed tPCBSY control method is based on the interesting observation that the array program current (ICC2) is mainly decided by the bit‐line bias condition. In the proposed approach, when peak ICC2 becomes larger than a threshold value, which is determined by a cache loop number, cache data cannot be loaded to the cache buffer (CB). On the other hand, when peak ICC2 is smaller than the threshold level, cache data can be loaded to the CB. As a result, the peak ICC of the cache program is reduced by 32% at the least significant bit page and by 15% at the most significant bit page. In addition, the program throughput reaches 20 MB/s in multiplane cache program operation, without restrictions caused by a drop in peak power due to cache program operations in a solid‐state drive.     

Automatic synthesis of embedded SW for evaluating physical implementation alternatives from UML/MARTE models supporting memory space separation

The proposed approach presents a method for automatically synthesizing the SW code of complex embedded systems from a model-driven system specification. The solution is oriented to enabling easy exploration and design of different allocations of SW components in heterogeneous platforms, minimizing designer effort. The system is initially described following the UML/MARTE standard. Applying this standard, the system is modeled, describing its components, interfaces and communication links, the system memory spaces, the resource allocations and the HW architecture. From that information, a SW infrastructure containing the communication infrastructure is generated ad-hoc for the system depending on the HW architecture and the resource allocations evaluated. The consequent communication overhead reduction can result in an important advantage for system performance optimization.     

Simultaneous Culturing of Cell Monolayers and Spheroids on a Single Microfluidic Device for Bridging the Gap between 2D and 3D Cell Assays in Drug Research

Two‐dimensional (2D) cell cultures have been the primary screening tools to predict drug impacts in vitro for decades. However, owing to the lack of tissue‐specific architecture of 2D cultures, secondary screening using three‐dimensional (3D) cell culture models is often necessary. A microfluidic approach that facilitates side‐by‐side 2D and 3D cell culturing in a single microchannel and thus combines the benefits of both set‐ups in drug screening; that is, the uniform spatiotemporal distributions of oxygen, nutrients, and metabolic wastes in 2D, and the tissue‐like architecture, cell–cell, and cell–extracellular matrix interactions only achieved in 3D. The microfluidic platform is made from an organically modified ceramic material, which is inherently biocompatible and supports cell adhesion (2D culture) and metal adhesion (for integration of impedance electrodes to monitor cell proliferation). To induce 3D spheroid formation on another area, a single‐step lithography process is used to fabricate concave microwells, which are made cell‐repellant by nanofunctionalization (i.e., plasma porosification and hydrophobic coating). Thanks to the concave shape of the microwells, the spheroids produced on‐chip can also be released, with the help of microfluidic flow, for further off‐chip characterization after culturing. In this study, the methodology is evaluated for drug cytotoxicity assessment on human hepatocytes.