Asynchronous 2‐Phase Protocol Based on Ternary Encoding for On‐Chip Interconnect

Level‐encoded dual‐rail (LEDR) has been widely used in on‐chip asynchronous interconnects supporting a 2‐phase handshake protocol. However, it inevitably requires 2N wires for N‐bit data transfers. Encoder and decoder circuits that perform an asynchronous 2‐phase handshake protocol with only N wires for N‐bit data transfers are presented for on‐chip global interconnects. Their fundamentals are based on a ternary encoding scheme using current‐mode multiple valued logics. Using 0.25 μm CMOS technologies, the maximum reduction ratio of the proposed circuits, compared with LEDR in terms of power‐delay product, was measured as 39.5% at a wire length of 10 mm and data rate of 100 MHz.     

Contention‐based geographic forwarding in asynchronous duty‐cycled wireless sensor networks

In asynchronous duty‐cycled wireless sensor networks, it is desirable that the data forwarding scheme is adaptive to the dynamics caused by the uncertainty of sensor nodes’ working schedules. Contention‐based forwarding is designed to adapt to the dynamic environments. In this work, we are interested in the contention‐based geographic forwarding (CGF) for two asynchronous duty‐cycling (ADC) models, which we refer to as uninterruptible ADC (U‐ADC) and interruptible ADC (I‐ADC). We propose a new residual time‐aware routing metric for CGF in the I‐ADC model and present a residual time‐aware forwarding scheme using this metric. We evaluate the performance of CGF in both asynchronous duty‐cycling models. Simulation results show that CGF in the U‐ADC model provides a shorter delivery delay while suffering from a high sender effective duty cycle problem. CGF in the I‐ADC model incurs a very long data delivery delay, but it can achieve a good load balancing among nodes. It is also demonstrated that the proposed residual time‐aware forwarding scheme lowers the effects of the performance degradation caused by the pure asynchronous duty‐cycling operation. Copyright © 2011 John Wiley & Sons, Ltd.     

An improved current mode logic latch for high‐speed applications

In this paper, an improved current mode logic (CML) latch design is proposed for high‐speed on‐chip applications. Transceivers use various methods in fast data transmission in wireless/wire‐line application. For an asynchronous transceiver, the improved CML latch is designed using additional NMOS transistors in conventional CML latch which helps to boost the output voltage swing. The proposed low‐power CML latch‐based frequency divider is compatible for higher operating frequency (16 GHz). Next, the delay model is also developed based on small signal equivalent circuit for the analysis of the proposed latch. The output voltage behavior of the proposed latch is analyzed using 180‐nm standard CMOS technology.     

OFDM‐Based STBC with Low End‐to‐End Delay for Full‐Duplex Asynchronous Cooperative Systems

We propose a new space‐time block coding (STBC) for asynchronous cooperative systems in full‐duplex mode. The orthogonal frequency division multiplexing (OFDM) transmission technique is used to combat the timing errors from the relay nodes. At the relay nodes, only one OFDM time slot is required to delay for a pair‐wise symbol swap operation. The decoding complexity is lower for this new STBC than for the traditional quasi‐orthogonal STBC. Simulation results show that the proposed scheme achieves excellent performances.     

An energy‐efficient asynchronous wake‐up scheme for underwater acoustic sensor networks

In addition to the requirements of the terrestrial sensor network where performance metrics such as throughput and packet delivery delay are often emphasized, energy efficiency becomes an even more significant and challenging issue in underwater acoustic sensor networks, especially when long‐term deployment is required. In this paper, we tackle the problem of energy conservation in underwater acoustic sensor networks for long‐term marine monitoring applications. We propose an asynchronous wake‐up scheme based on combinatorial designs to minimize the working duty cycle of sensor nodes. We prove that network connectivity can be properly maintained using such a design even with a reduced duty cycle. We study the utilization ratio of the sink node and the scalability of the network using multiple sink nodes. Simulation results show that the proposed asynchronous wake‐up scheme can effectively reduce the energy consumption for idle listening and can outperform other cyclic difference set‐based wake‐up schemes. More significantly, high performance is achieved without sacrificing network connectivity. Copyright © 2015 John Wiley & Sons, Ltd.     

Protocol design and data detection for two‐way relay networks with fractional asynchronous delays

In wireless two‐way relay systems, it is difficult to achieve perfect timing synchronization among different nodes. In this paper, we investigate relaying protocol design and data detect schemes for asynchronous two‐way relaying systems to combat the intersymbol interference caused by asynchronous transmission. We consider fractional asynchronous delays and two schemes are proposed based on cyclic prefixed single carrier block transmission, namely, the receiver frequency domain equalization scheme and relay synchronization and network coding (RSNC) scheme. In the receiver frequency domain equalization scheme, the relay simply amplifies the received signal and forwards to the two source nodes, and fractionally spaced frequency domain equalizer (FS‐FDE) is employed at the receiver to recover the transmit data. In the RSNC scheme, the asynchronous signals are resynchronized with an FS‐FDE at the relay node. The output signals of FS‐FDE are then demodulated and network coded before forwarding to the two source nodes. In this RSNC scheme, data detection at the source nodes is the same as that in synchronous networks because the asynchronous signals have already been synchronized at the relay node. Simulation results show that the performance of both schemes is almost the same as in the perfect synchronized two‐way relaying systems. Copyright © 2012 John Wiley & Sons, Ltd.     

Mini‐Slot‐Based Transmission Scheme for Local Customer Internetworking in PONs

We propose a new mini‐slot transmission scheme for a passive optical network (PON) in which each customer can be switched either to access mode or to internetworking mode dynamically. In this paper, we present the system implementation (called LAN‐PON) as well as the performance of the proposed transmission scheme to illustrate its feasibility and benefits. A mini‐slot scheme can rapidly reduce the queuing delay, which increases due to the flooding of the deflected packets in a deflection scheme. We evaluate the impact of mode switching time on the bandwidth gain (throughput) and delay of local area network (LAN) traffic in the LAN‐PON with a mini‐slot scheme. We also analyze a theoretical delay model of the proposed scheme. The simulation results demonstrate that switching time has an impact on LAN performance, and the average packet delay of the proposed scheme is significantly improved compared to that of the deflection scheme.     

Orthogonal superimposed training design for block transmission over frequency‐selective fading channels

Channel estimation for single‐carrier block transmission over frequency‐selective fading channel using superimposed training is addressed. A novel affine precoding model based on orthogonal polyphase sequence set is designed to decouple channel estimation from symbol detection. The orthogonal constraints on the training and precoding matrices ensure the separation of superimposed signals and accurate channel estimation with less training overheads as compared with time‐multiplexed scheme. Simulation results show that the proposed scheme exhibits good performance and outperforms another data‐dependent superimposed training scheme, especially for compact constellations or channel with long delay‐spread. Copyright © 2014 John Wiley & Sons, Ltd.     

Differential bidirectional transceiver for on-chip long wires

This work presents a differential bidirectional transceiver (DBT) for on-chip long wires. To enhance operating speed and reduce power consumption, the voltage swing on the wire is reduced using current-mode scheme. Consequently, our design performs higher data rate when wire length is extended. Moreover, adoption of differential scheme with a moderate tradeoff of area effectively lowers power supply noise and common mode noise. The receiver adopts four input differential pairs along with current summation circuit to evaluate small signal differences of every that state resulted from transmitting different data. Simulations using 0.18-μm device model indicates that the total input to output delay over a 5 mm long wire is 0.96 ns, with a power consumption of 8.724 mW at a speed of 1.2 Gbps and a maximum achievable data rate of 1.5 Gbps. A test chip is realized and successfully verifies the performance of the transceiver.     

CMOS current steering logic for low-voltage mixed-signal integratedcircuits

A quiet logic family-complementary metal-oxide-semiconductor (CMOS) current steering logic (CSL)-has been developed for use in low-voltage mixed-signal integrated circuits. Compared to a CMOS static logic gate with its output range of ΔV_logic≈V_dd , a CSL gate swings only ΔV_logic≈V_T+0.25 V because the constant current supplied by the PMOS load device is steered to ground through either an NMOS diode-connected device or switching network. Owing to the constant current, digital switching noise is 100× smaller than in static logic. Another useful feature which can be used to calibrate CSL speed against process, temperature, and voltage variations is propagation delay that is approximately constant versus supply voltage and linear with bias current. Several CSL circuits have been fabricated using 0.8 and 1.2 μm high-V_T n-well CMOS processes. Two self-loaded 39-stage ring oscillators fabricated using the 1.2 μm process (1.2 V power supply) exhibited power-delay products of 12 and 70 fJ with average propagation delays of 0.4 and 0.7 ns, respectively. High-V_T and low-V_T CSL ALU's were operational at V _dd≈=0.70 V and V_dd≈0.40 V, respectively     

Mapping and Scheduling for Circuit‐Switched Network‐on‐Chip Architecture

Network‐on‐chip (NoC) architecture provides a high‐performance communication infrastructure for system‐on‐chip designs. Circuit‐switched networks guarantee transmission latency and throughput; hence, they are suitable for NoC architecture with real‐time traffic. In this paper, we propose an efficient integrated scheme which automatically maps application tasks onto NoC tiles, establishes communication circuits, and allocates a proper bandwidth for each circuit. Simulation results show that the average waiting times of packets in a switch in 6×6, 8×8, and 10×10 mesh NoC networks are 0.59, 0.62, and 0.61, respectively. The latency of circuits is significantly decreased. Furthermore, the buffer of a switch in NoC only needs to accommodate the data of one time slot. The cost of the switch in the circuit‐switched network can be reduced using our scheme. Our design provides an effective solution for a critical step in NoC design.     

τ‐AIMD for asynchronous receiver feedback

In this work we first describe an asynchronous‐feedback model which corresponds to the diverse roundtrip times (RTTs) of competing flows within the same communication channel. We show that even when the feedback of the receivers/network is asynchronous, the duration of a congestion epoch represents ‘common knowledge’ for the competing flows. Based on this property, we propose a diverse linear increase scheme in proportion to the RTT of each flow and we adjust periodically the windows of the competing flows accordingly, in order to enhance fairness of asynchronous‐feedback environments. We name this scheme τ‐AIMD and show that fairness of flows in asynchronous systems is improved since the increase‐rate diversity of long and short RTT flows is largely canceled. We use the max–min notion of fairness to show that τ‐AIMD can constitute the foundation for other window‐based, end‐to‐end algorithms that target a good balance between efficiency and fairness. Copyright © 2004 John Wiley & Sons, Ltd.     

Delay‐aware privacy‐preserving location‐based services under spatiotemporal constraints

The ubiquitous use of location‐based services (LBS) through smart devices produces massive amounts of location data. An attacker, with an access to such data, can reveal sensitive information about users. In this paper, we study location inference attacks based on the probability distribution of historical location data, travel time information between locations using knowledge of a map, and short and long‐term observation of privacy‐preserving queries. We show that existing privacy‐preserving approaches are vulnerable to such attacks. In this context, we propose a novel location privacy‐preserving approach, called KLAP, based on the three fundamental obfuscation requirements: minimum k ‐locations, l ‐diversity, and privacy a rea p reservation. KLAP adopts a personalized privacy preference for sporadic, frequent, and continuous LBS use cases. Specifically, it generates a secure concealing region (CR) to obfuscate the user's location and directs that CR to the service provider. The main contribution of this work is twofold. First, a CR pruning technique is devised to establish a balance between privacy and delay in LBS usage. Second, a new attack model called a long‐term obfuscated location tracking attack, and its countermeasure is proposed and evaluated both theoretically and empirically. We assess KLAP with two real‐world datasets. Experimental results show that it can achieve better privacy, reduced delay, and lower communication costs than existing state‐of‐the‐art methods.     

Design and Implementation of Open‐Loop Clock Recovery Circuit for 39.8 Gb/s and 42.8 Gb/s Dual‐Mode Operation

This paper proposes an open‐loop clock recovery circuit (CRC) using two high‐Q dielectric resonator (DR) filters for 39.8 Gb/s and 42.8 Gb/s dual‐mode operation. The DR filters are fabricated to obtain high Q‐values of approximately 950 at the 40 GHz band and to suppress spurious resonant modes up to 45 GHz. The CRC is implemented in a compact module by integrating the DR filters with other circuits in the CRC. The peak‐to‐peak and RMS jitter values of the clock signals recovered from 39.8 Gb/s and 42.8 Gb/s pseudo‐random binary sequence (PRBS) data with a word length of 2³¹?1 are less than 2.0 ps and 0.3 ps, respectively. The peak‐to‐peak amplitudes of the recovered clocks are quite stable and within the range of 2.5 V to 2.7 V, even when the input data signals vary from 150 mV to 500 mV. Error‐free operation of the 40 Gb/s‐class optical receiver with the dual‐mode CRC is confirmed at both 39.8 Gb/s and 42.8 Gb/s data rates.     

一种低延迟低功耗的片上全局互连方法

提出了一种用于片上全局互连的混合插入方法. 该方法利用中继驱动器和低摆幅差分信号电路在驱动不同长度连线时的优点，将它们混合插入到连线的合适位置，从而降低互连的延时和功耗. 模拟结果表明，该方法与已有方法相比在延时、能耗、能耗延时积以及面积等方面都获得了一定程度的改善.     

Common‐Mode Current on a Wire through a Corrugated Aperture

This paper investigates the effect of a corrugated aperture on a common‐mode current traveling along a penetrating wire. Computational results illustrate that the corrugated aperture acts as a filter, significantly reducing the common‐mode current on the wire. This effect causes a reduction of radiated emission from cables passing through apertures on shielding enclosures. To predict and analyze the characteristics of the common‐mode current on a straight wire passing through a corrugated aperture with cylindrical symmetry, the finite‐difference time‐domain (FDTD) method is applied.     

Quadrature Oscillators with Grounded Capacitors and Resistors Using FDCCIIs

Two current‐mode and/or voltage‐mode quadrature oscillator circuits each using one fully‐differential second‐generation current conveyor (FDCCII), two grounded capacitors, and two (or three) grounded resistors are presented. In the proposed circuits, the current‐mode quadrature signals have the advantage of high‐output impedance. The oscillation conditions and oscillation frequencies are orthogonally (or independently) controllable. The current‐mode and voltage‐mode quadrature signals can be simultaneously obtained from the second proposed circuit. The use of only grounded capacitors and resistors makes the proposed circuits ideal for integrated circuit implementation. Simulation results are also included.     

Architectural Design Issues in a Clockless 32‐Bit Processor Using an Asynchronous HDL

As technology evolves into the deep submicron level, synchronous circuit designs based on a single global clock have incurred problems in such areas as timing closure and power consumption. An asynchronous circuit design methodology is one of the strong candidates to solve such problems. To verify the feasibility and efficiency of a large‐scale asynchronous circuit, we design a fully clockless 32‐bit processor. We model the processor using an asynchronous HDL and synthesize it using a tool specialized for asynchronous circuits with a top‐down design approach. In this paper, two microarchitectures, basic and enhanced, are explored. The results from a pre‐layout simulation utilizing 0.13‐μm CMOS technology show that the performance and power consumption of the enhanced microarchitecture are respectively improved by 109% and 30% with respect to the basic architecture. Furthermore, the measured power efficiency is about 238 μW/MHz and is comparable to that of a synchronous counterpart.     

High speed wide fan‐in designs using clock controlled dual keeper domino logic circuits

Clock Controlled Dual keeper Domino logic structures (CCDD_1 and CCDD_2) for achieving a high‐speed performance with low power consumption and a good noise margin are proposed in this paper. The keeper control circuit comprises an additional PMOS keeper transistor controlled by the clock and foot node voltage. This control mechanism offers abrupt conditional control of the keeper circuit and reduces the contention current, leading to high‐speed performance. The keeper transistor arrangement also reduces the loop gain associated with the feedback circuitry. Hence, the circuits offer less delay variability. The design and simulation of various wide fan‐in designs using 180 nm CMOS technology validates the proposed CCDD_1 and CCDD_2 designs, offering an increased speed performance of 7.2% and 8.5%, respectively, over a conventional domino logic structure. The noise gain margin analysis proves good robustness of the CCDD structures when compared with a conventional domino logic circuit configuration. A Monte Carlo simulation for 2,000 runs under statistical process variations demonstrates that the proposed CCDD circuits offer a significantly reduced delay variability factor.