A Symmetric Complementary Structure for RF CMOS Analog Squarer and Four-Quadrant Analog Multiplier

A symmetric complementary structure for CMOS analog squarer and four-quadrant multiplier is proposed and analyzed. Analog squarer and a four-quadrant analog multiplier by utilizing the square-algebraic identity in the MOS triode region are presented. The squarer has a symmetric complementary configuration of the push-pull source follower and provides high performance in terms of linearity, power consumption, frequency response and total harmonic distortion (THD). The squarer, with –3 dB bandwidth of 1.3 GHz, had a nonlinearity error less than 1% over input signal range of ±1 V. The multiplier is basically constructed by voltage subtractors (for differential function of inputs) and sum-squaring as well as difference-squaring core circuits (for multiplication of two differential inputs signals). The multiplier has a nonlinearity error less than 1% over ±0.5 V input range. The circuit provides a –3 dB bandwidth higher than 1.3 GHz and exhibits a THD lower than 1% with a 1 V peak-to-peak input voltage, which dissipating 2.6 mW. The second-order effects including mismatch effects are discussed. The proposed circuits will be useful in various RF analog signal-processing applications.     

Optimization of MOS amplifier performance through channel length and inversion level selection

The dependence of MOS amplifier performance on channel length and channel inversion is simulated and discussed. Suggestions are made regarding the optimization of voltage gain, nonlinear distortion and the gain-bandwidth product (GBW) through careful device length and inversion level selection. The midband voltage gain of the common-source amplifier is shown to remain relatively constant when biased for weak inversion operation, with short-channel devices continuing to amplify effectively at very low levels of inversion, allowing for extremely low power circuits. Total harmonic distortion is reduced through decreasing channel length and/or the level of channel inversion. The GBW is optimized through the use of minimum sized transistors biased to operate in the strong inversion region.     

A low power and low distortion rail-to-rail input/output amplifier using constant current technique

A rail-to-rail amplifier with constant transconductance,intended for audio processing,is presented.The constant transconductance is obtained by a constant current technique based on the input differential pairs operating in the weak inversion region.MOSFETs working in the weak inversion region have the advantages of low power and low distortion.The proposed rail-to-rail amplifier,fabricated in a standard 0.35μm CMOS process,occupies a core die area of 75×183μm~2.Measured results show that the maximum power consumption is 85.37μW with a supply voltage of 3.3 V and the total harmonic distortion level is 1.2%at 2 kHz.     

Robust Design of LV/LP Low-Distortion CMOS Rail-to-Rail Input Stages

Two robust CMOS rail-to-rail OpAmp input stages are presented for low voltage ( 3 V) applications. The robust input stages are implemented using two recently reported universal approaches to achieve constant transconductance. Transconductance control circuit is also introduced to compensate for K _p , K _n mismatch of PMOS and NMOS differential pairs in the input stage. The input stages are designed for operation in the strong inversion and have a rail-to-rail common mode input voltage range. Compared with an OpAmp with simple complementary input pairs, a two stage rail-to-rail OpAmp design example exhibits lower total harmonic distortion (THD) levels over the entire common mode input voltage range.currently on leave as a visiting scholar at OSU     

Using the weak inversion region to optimize input stage design of CMOS op amps

Operation of MOS devices in the strong, moderate, and weak inversion regions is considered. The advantages of designing the input differential stage of a CMOS op amp to operate in the weak or moderate inversion region are presented. These advantages include higher voltage gain, less distortion, and ease of compensation. Specific design guidelines are presented to optimize amplifier performance. Simulations that demonstrate the expected improvements are given.     

Enhanced source-degenerated CMOS differential transconductor

A simple technique to improve the output resistance and the linearity of a source-degenerated differential CMOS transconductor is presented, useful even under low supply voltage. It combines the utilization of a super-transistor as a unity-gain buffer and the use of the weak inversion region to optimize a regulated cascode source. Using a standard 0.13 μm CMOS technology with 1.5 V supply voltage, simulation results show the transconductor attains more than 1 GΩ as differential output resistance and a third-order harmonic distortion factor less than −110 dB at 1 kHz for a 0.35 V_pp differential input signal. Other performances are 126 μW power consumption and 65 MHz bandwidth.     

New CMOS four-quadrant multiplier and squarer circuits

A CMOS four-quadrant multiplier and a squarer using the positive feedback loops consisting of the current mirrors are presented. Simulation results are given to verify the theoretical analysis. The input range of this multiplier is over ±2.5V with the linearity error less than 1% and its-3dB bandwidth is about 20MHz. The total harmonic distortion is less than 1% with the input range up to ±2V. The squarer has a ±1.6V input range. Second order effects such as mobility reduction and transistor mismatch have been discussed. Experimental results by using discrete components are also given. The proposed circuits are expected to be useful in analog signal-processing applications.     

The MOS capacitor amplifier

It is well known that low noise amplification can be performed by using a capacitor whose capacitance can be controlled. In this paper, it is shown that changing the inversion level of a MOS transistor allows voltage amplification. The theoretical characterization of this amplifier in terms of gain and harmonic distortion is made, and comparisons with HSPICE results are performed. Finally, some practical considerations to improve the performance of the circuit are presented.     

A 0.25-V 22-nS symmetrical bulk-driven OTA for low-frequency G_m-C applications in 130-nm digital CMOS process

This paper presents a 0.25-V supplied bulk-driven symmetrical OTA implemented in 130-nm CMOS process. By operating in weak inversion, and using a distributed layout approach, the OTA can benefit from the voltage reduction and high linearity enabled by halo-implanted transistors. The proposed circuit consumes only 10-nW, features a low transconductance of 22-nS, and a total harmonic distortion of 0.53 % for a 100-mV_pp input voltage, thus making it suitable for low-frequency and low-power \(G_m\) -C applications.     

A Fully Differential CMOS Voltage Buffer for?Continuous- and Discrete-Time Applications

This paper presents a new CMOS analog fully differential voltage buffer, with large dynamic range and low harmonic distortion. Its design is based on the use of cross-coupled input differential pairs and internal current feedback. Two design approaches are proposed, with the objective of minimizing power consumption: one for switched-capacitor circuits and the other for Gm-C circuits. Design equations and simulation results are presented as well. Illustrative design examples are developed for a 0.35-μm CMOS technology using a power supply voltage of 2.5 V.     

FGMOS transistor based low voltage and low power fully programmable Gaussian function generator

In this paper floating gate MOS (FGMOS) transistor based fully programmable Gaussian function generator (GFG) is presented. The circuit combines the exponential characteristics of MOS transistor in weak inversion, tunable property of FGMOS transistor, and its square law characteristic in strong inversion region to implement the GFG. FGMOS based squarer is the core sub circuit of GFG that helps to implement full Gaussian function for positive as well as negative half of the input voltage. FGMOS implementation of the circuit provides low voltage operation, low power consumption, reduces the circuit complexity and increases the tunability of the circuit. The performance of circuit is verified at 0.75 V in TSMC 0.18 μm CMOS, BSIM3 and level 49 technology by using Cadence Spectre simulator. To ensure robustness of the proposed GFG, simulation results for various process corner variations have also been included.     

Low-voltage pseudo-differential transconductor with improved tunability-linearity trade-off

A new low-voltage pseudo-differential CMOS transconductor using transistors in the saturation region is presented. It keeps the input common-mode voltage constant, while its transconductance is easily tunable through a DC voltage preserving linearity for a moderate range of G/sub m/ values. Post-layout results for a 2.7 V-0.5 /spl mu/m CMOS design dissipating less than 1.5 mW show a 1:2 G/sub m/ tuning range with an almost constant bandwidth over 600 MHz. Total harmonic distortion figures are below -60 dB over the whole range at 10 MHz up to a 100 /spl mu/A/sub p-p/ differential output.     

A CMOS transconductor with multidecade tuning using balanced current scaling in moderate inversion

A versatile CMOS transconductor is proposed. Voltage-to-current conversion employs a polysilicon resistor and features high linearity over a wide input range and high current efficiency. Programmable balanced current mirrors able to operate in weak or moderate inversion regions provide wide transconductance gain tuning range without degrading other performance parameters like input range and linearity. The transconductor has two degrees of freedom for gain tuning. A 0.5-/spl mu/m implementation achieves a SFDR of 68 dB and a THD of -66.5dB using a dual supply of /spl plusmn/1.3 V with differential input swings equal to 77% of the total supply voltage, transconductance tuning over two decades, and 1.7 mW of static power consumption. Measurements demonstrate that operation in moderate inversion can lead to much less distortion levels than in strong inversion.     

Design of Low-Voltage Highly Linear Switched-R-MOSFET-C Filters

This paper discusses the design, analysis and performance of a low-voltage, highly linear switched-R-MOSFET-C filter. High linearity, even at a low supply voltage, is achieved through the use of duty-cycle-controlled tuning. Tuning MOSFETs are switched completely on while conducting, such that their nonlinear resistance is much smaller than the linear filter resistors, resulting in low distortion. The MOSFETs are also placed inside the filter feedback loop which further reduces distortion. Because tuning is done in the time domain, rather than in the voltage domain, the tuning range is independent of the supply voltage. The filter achieves -77 dB total harmonic distortion (THD) using a 0.6-V supply, and -90 dB THD using a 0.8-V supply, with a 0.6-Vpp differential 2 kHz sine input. The prototype IC, implemented in a 0.18-mum CMOS process, occupies an area of 0.7 mm² and consumes 1 mW of power from a 0.6-V supply.     

Over rail-to-rail fully differential voltage-to-current converters for nm scale CMOS technology

The converters presented in this paper are based on long channel complementary MOS transistors, instead of the commonly used differential amplifiers or differential transistor pairs which are difficult to implement in low voltage, nm scale CMOS technology. Nonlinearities of drain currents can be cancelled in the fully differential structure. As a result, the low power, nanometre standard digital CMOS technology converters are obtained. Layout examples are designed in 65 nm TSMC technology. Post-layout simulations show that the range of input voltage over rail-to-rail is achieved with very good linearity and reduced harmonic distortion.     

Harmonic and intermodulation performance of moderate inversion MOSFET transconductors

This article discusses the harmonic and intermodulation performance of moderate inversion MOSFET transconductors. The bulk of the nMOS transistor is tied to ground, at all levels of inversion, including moderate inversion and the transistor is operating in the saturation region where it behaves qualitatively as a constant current source. The current–voltage characteristic of the transistor is approximated using a Fourier-series model. Using this model, analytical expressions are obtained for amplitudes of the harmonics and intermodulation products resulting from multi-sinusoidal gate-to-source input voltages. The special case of a two equal-amplitude sinusoidal input is considered in detail and the results are compared with previously published results.     

RF circuit implications of moderate inversion enhanced linear region in MOSFETs

The implications for radio frequency circuit design of the nonlinear behavior of a MOSFET transistor over all regions of operation, including moderate inversion region, are investigated. Third-order intermodulation distortion in a MOSFET amplifier is analyzed by means of Volterra Series representation. Analysis and measurements reveal a significant peaking, or "sweet-spot" of the third-order intercept point in the moderate inversion region. As a result, a significant increase in linearity with low power consumption is possible. Analysis and measurements shows the dependance of distortion on the frequency, and transistor parameters, as well as the effects of the load impedance and feedback.     

A high-precision current-mode multifunction analog cell suitable for computational signal processing

In this paper, a high linear, low-voltage two-quadrant current squarer as multifunction analog cell, is presented. To implement the squarer circuit, translinear loops with matched NMOS transistors operating in weak inversion region are used. The proposed cell is used as a basic building block for current-mode computational analog functions such as rectifier (absolute-value), multi-input vector summation and exponential function generator. We perform post-layout plus Monte Carlo simulations of the presented functions with 0.18 μm (level-49 parameters) TSMC CMOS technology that prove their superiority over some other advanced works and robustness against PVT (process, voltage and temperature) variations.     

Transconductance amplifier with low-power consumption

A modified transconductance amplifier with low harmonic distortion and high current efficiency is proposed. It can be used in high-frequency applications up to 10 MHz. Each half of the transconductor differential input stage consists of a pair of transistors in saturation and linear regimes with a voltage feedback loop. Results of theoretical analysis are confirmed by SPICE simulations.     

Low phase-noise VCO utilizing modified symmetric load and partial positive feedback for FDSM

The voltage-controlled oscillator (VCO) in frequency-based $\Updelta\Upsigma$ modulator (FDSM) systems behaves as a voltage-to-phase integrator converting an analog input voltage to phase information. Tuning range and phase noise are the most important factors of the basic design of a VCO in FDSM systems. In this paper a novel low phase-noise and wide tuning-range differential VCO based on a differential ring oscillator with modified symmetric load and a partial positive feedback in the differential delay cell is presented. The VCO is combined with a new bias circuit and implemented using 90 nm CMOS process technology. By using modified NMOS symmetric loads and a PMOS tail for delay cells, the VCO phase noise can be reduced with more than 13 dB compared to that of the conventional approach, achieving ?125 dBc/Hz at 500 kHz offset from the center frequency of 450 MHz. The wide tuning-range by using two added transistors (parallel with the active loads) increases the operating frequency range by about 22%, while the partial positive feedback provides the necessary bias condition for the circuit to oscillate. The designed VCO operating at a low power supply voltage of 0.6V can achieve low power consumption of 670???W at oscillation frequency of 800 MHz and good linearity reducing harmonic distortion in the $\Updelta\Upsigma$ modulator.