Unifying simulation and execution in a design environment for FPGAsystems

Field programmable gate array (FPGA)-based systems provide advantages over conventional hardware including: (1) availability of the hardware during design and debug; (2) programmability; and (3) visibility. These three advantages can greatly shorten the design and verification cycle. This paper discusses a design environment that exploits these three FPGA-specific advantages to create a unified simulation/execution debug environment implemented in the JHDL design system. The described system provides a hardware debugging environment with the functionality of a simulator but up to 10000× faster. In addition, testbenches and other typical verification software used in simulators can be used to verify running hardware     

多通道微量注射泵的设计与实现

微量注射泵广泛应用于临床医疗和生命科学研究中。旨在开发一套性能优越的自动化送液系统,要求系统具有精度高,能同时联动控制多台注射泵进行加减速注射,且计算机实时控制的特点。使用MicrosoftVisual C＋＋6．0开发工具设计一款上住机监控软件,以实现自动化处理。硬件采用ARM＋FPGA的组合,充分发挥FPGA优越的逻辑时序功能和并行处理的优点。步进电机驱动器的高细分提高了注射精度,应用多个传感器对注射状态进行检测,成功实现了智能精密注射和对注射器的保护。     

基于FPGA技术的位置反馈系统设计

介绍了基于FPGA器件的角度位置反馈电路的具体实现方法。阐述了以多极双通道旋转变压器为测量元件的位置处理电路转换和纠错的原理和方法。给出了以FPGA器件为核心的硬件设计,微机接口为PCI04总线。电路被应用于多种跟踪系统中。实践证明,其静、动态技术指标及性能理想,可广泛用于各种控制系统中。     

Development of a Run-Time Reconfiguration System with Low Reconfiguration Overhead

The concept of using a microcontroller coupled to re-programmable FPGAs is being used at the heart of Run-Time Reconfigurable (RTR) systems. This paper presents the development of an RTR system for DSP and telecommunication applications. It differs from other systems, in that it treats reconfiguration time as a key design parameter by employing design for reconfiguration where partial reconfiguration is identified in the design of the circuit architecture. Reductions of up to 75% in the implementation time of multiplication, division and square root circuits have been achieved using the Xilinx XC6200 FPGA family. A special hardware/software interface called the Virtual Hardware Handler, has also been developed to support the design approach. It vastly simplifies the reconfiguration operation, reducing it to a simple process of passing pointers and data. The approach has been implemented on a windows-based RTR system.     

Applying test driven development to embedded software

Test driven development (TDD) is increasing in information technology applications and product development; however, it has not been widely applied in embedded software development. Embedded developers face many challenges. TDD can help overcome some of these challenges, but TDD has to be adapted for embedded systems development. TDD is an important software development practice that can help embedded developers deliver higher quality products. The embedded TDD cycle can help take hardware availability off the software critical path, enabling steady progress with or without hardware. TDD can be used for embedded development in C and C++. Java may also be an option for some embedded systems, and Java is better suited for TDD, as the tools for Java support are much more advanced.     

An open medical imaging workstation architecture forplatform-independent 3-D medical image processing and visualization

A need for an entirely new medical workstation design was identified to increase the deployment of 3D medical imaging and multimedia communication. Recent wide acceptance of the World Wide Web (WWW) as a general communication service within the global network has shown how big the impact of standards and open systems can be. Information is shared among heterogeneous systems and diverse applications on various hardware platforms only by agreeing on a common format for information distribution. For medical image communications, the Digital Imaging and Communication in Medicine (DICOM) standard is possibly anticipating such a role. Logically, the next step is open software: platform-independent tools, which can as easily be transferred and used on multiple platforms. Application of the platform-independent programming language Java enables the creation of plug-in tools, which can easily extend the basic system. Performance problems inherent to all interpreter systems can be circumvented by using a hybrid approach. Computationally intensive functions like image processing functions can be integrated into a natively implemented optimized image processing kernel. Plug-in tools implemented in Java can utilize the kernel functions via a Java-wrapper library. This approach is comparable to the implementation of computationally intensive operations in hardware     

基于FPGA的面阵CCD驱动电路的设计

介绍一种面阵CCD传感器TH7888A的原理和性能,分析其对驱动信号的时序要求,选用FPGA器件作为硬件设计平台,使用VHDL语言对驱动信号时序进行硬件描述,针对Xilinx公司的Spartan3系列芯片进行仿真及配置;选用LM117提供CCD所需的偏置电压,EL7212提供驱动。系统测试结果表明,该CCD驱动电路可以满足CCD的工作要求。     

基于SOPC可重构的图像采集与处理系统设计

针对目前PC算法无法实现图像实时处理以及固定硬件平台很难实现算法修改或者升级的问题,设计一种基于SOPC可重构的图像采集与处理系统,实现了图像数据的片上实时处理以及在不改变硬件电路结构而完成算法修改或者升级的功能。此系统围绕两块Xilinx FPGA芯片进行设计,通过FPGA以及其Microblaze 32 bit软核处理器和相关接口模块实现硬件电路设计,结合FPGA开发环境ISE工具和EDK工具协作完成软件设计。由于采用SOPC技术和可重构技术,此设计具有设计灵活、处理速度快和算法可灵活升级等特点。     

相关干涉仪测向算法的FPGA设计实现

相关干涉仪算法是一种设计实现非常简便的测向方法,使用FPGA设计技术可以解决处理速度比较慢的问题。介绍了相关干涉仪测向算法的原理和技术特点,对设计中采用的5阵元圆形天线阵相关干涉仪测向系统的硬件平台组成结构和处理过程进行了简述,并且详细说明了使用FPGA所实现的主要功能和FPGA设计所采用的设计工具。对设计中采用的关键技术和采用FPGA实现相关干涉仪测向处理后测向处理速度的提高进行了分析比较。     

Improving functional density using run-time circuit reconfiguration[FPGAs]

The ability to provide flexibility and allow fine-grain circuit specialization make field programmable gate arrays (FPGA's) ideal candidates for computing elements within application-specific architectures. The benefits of gate-level specialization and reconfigurability can be extended by reconfiguring circuit resources at run-time. This technique, termed run-time reconfiguration (RTR), allows the exploitation of dynamic conditions or temporal locality within application-specific problems. For several applications, this technique has been shown to reduce the hardware resources required for computation. The use of this technique on conventional FPGA's, however, requires additional time for circuit reconfiguration. A functional density metric is introduced that balances the advantages of RTR against its associated reconfiguration costs. This metric is used to justify run-time reconfiguration against other more conventional approaches. Several run-time reconfigured applications are presented and analyzed using this approach     

FPGA prototyping of a RISC processor core for embedded applications

Application-specific processors offer an attractive option in the design of embedded systems by providing high performance for a specific application domain. In this work, we describe the use of a reconfigurable processor core based on an RISC architecture as starting point for application-specific processor design. By using a common base instruction set, development cost can be reduced and design space exploration is focused on the application-specific aspects of performance. An important aspect of deploying any new architecture is verification which usually requires lengthy software simulation of a design model. We show how hardware emulation based on programmable logic can be integrated into the hardware/software codesign flow. While previously hardware emulation required massive investment in design effort and special purpose emulators, an emulation approach based on high-density field-programmable gate array (FPGA) devices now makes hardware emulation practical and cost effective for embedded processor designs. To reduce development cost and avoid duplication of design effort, FPGA prototypes and ASIC implementations are derived from a common source: We show how to perform targeted optimizations to fully exploit the capabilities of the target technology while maintaining a common source base     

一种基于改进型游程编码的FPGA动态重构方法

在分析传统FPGA动态重构方法性能缺陷的基础上,创新性的提出了基于改进型游程编码的FPGA动态重构方法,并详细介绍了该方法的设计实现。与传统FPGA动态重构方法对比测试结果表明,基于改进型游程编码的FPGA动态重构方法不仅可以显著提高FPGA动态重构的速度,而且可以降低对程序存储器容量要求。目前,该技术已在重大工程项目中得到应用。     

基于FPGA的步进电机控制器研究和实现

步进电机是一种将电脉冲转化为角位移的执行机构,已广泛应用于各种自动化控制系统中。为了提高对步进电机的细分要求,提出了基于FPGA控制的步进电机控制器方案。给出了用VHDL语言层次化设计各功能模块的过程,利用QuartusⅡ进行仿真,给出了仿真结果,并成功地在FPGA器件上验证了设计的可能性。采用FPGA器件和VHDL语言。只需修改模块程序参数,而无须修改硬件电路就能实现各种控制。该设计硬件结构简单可靠,可根据实践需要灵活方便进行配置。     

NEW APPROACH TO EMULATE SEU FAULTS ON SRAM BASED FPGAS简

Field Programmable Gate Arrays （FPGAs） offer high capability in implementing of com- plex systems, and currently are an attractive solution for space system electronics. However, FPGAs are susceptible to radiation induced Single-Event Upsets （SEUs）. To insure reliable operation of FPGA based systems in a harsh radiation environment, various SEU mitigation techniques have been provided In this paper we propose a system based on dynamic partial reconfiguration capability of the modern devices to evaluate the SEU fault effect in FPGA. The proposed approach combines the fault injection controller with the host FPGA, and therefore the hardware complexity is minimized. All of the SEU injection and evaluation requirements are performed by a soft-core which realized inside the host FPGA Experimental results on some standard benchmark circuits reveal that the proposed system is able to speed up the fault injection campaign 50 times in compared to conventional method.     

Configurable logic for digital communications: some signalprocessing perspectives

For the past two decades software programmable digital signal processors and ASICs have provided hardware solutions for signal processing system designers. A new option has become available: field programmable gate arrays. FPGA-based DSP platforms allow the designer to realize a data path that exactly matches the required processing, while at the same time maintaining the flexibility of a software approach. This article presents an overview of some FPGA DSP applications. Several filter designs are presented, and the use of CORDIC arithmetic for constructing an FPGA carrier recovery loop is outlined. In addition to presenting design examples that can be realized using present-generation devices and tools, we take a brief look at how the dynamic reconfiguration aspect of certain FPGAs could be exploited in future-generation communication technologies     

基于DSP和FPGA的光学遥感器控制器系统设计

本文提出了一种基于DSP和FPGA的光学遥感器控制器系统的设计方案。该系统以DSP为核心处理器,FPGA辅助其进行控制和通信,实现了系统的工程参数采集、与卫星平台的1553B通信、与光学遥感器内各分系统的RS485通信功能。详细阐述了系统的组成和软硬件设计。实验结果表明,DSP和FPGA能够很好协作完成控制和通信功能。相比基于单一处理器的系统,本系统构架可以简化硬件设计,灵活性强,且工作稳定、可靠,可应用于大多数控制系统。     

A reprogrammable gate array and applications

A field-programmable gate array (FPGA) can implement thousands of gates of logic, has no up-front fixed costs, and can be programmed in a few minutes by writing into on-chip static memory is described. This kind of FPGA can be reprogrammed any number of times, providing a versatile platform for rapid hardware implementation. Reprogrammable technology allows software-like design methodologies to be applied to logic design. The construction of this kind of FPGA, design tradeoffs, and examples of applications that take advantage of reprogrammability are examined