A new current-differencing single-supply operational amplifier

The conventional integrated-circuit operational amplifier is not well suited to many system applications that operate from only a single power supply voltage. To more optimally meet the requirements of industrial control systems a new current- differencing opamp has been developed that uses a simple circuit to provide a gain element that out performs the 741 IC opamp. As a result of the circuit simplicity, multiple opamps are possible and six independent internally compensated amplifiers have been fabricated on a single 80/spl times/93-mil die. Many circuits are presented only not to show how this circuit can perform most the application functions of a standard IC opamp, but also to indicate the increased usefulness of this new input current differencing type of opamp circuit in single power-supply control system applications.     

Direct-Charge-Transfer Pseudo-N-Path SC Circuit Insensitive to the Element Mismatch and Opamp Nonidealities

A novel pseudo-N-path switched-capacitor circuit is described. Its center frequency is insensitive to element mismatch as well as to the finite gain and bandwidth of the opamps used. In this new architecture, the charges from the input source to the output are not transferred by an opamp; rather the opamp is used only as a buffer. The performance of the circuit is superior to that of a regular pseudo-N-path structure.     

Distortion in single-, two- and three-stage amplifiers

Nonlinear distortion in single-, two-, and three-stage operational amplifiers (opamps) is the main scope of this paper. For each opamp, distortion contributions from different groups of transistors are identified and plotted versus frequency. This makes it possible to find the strongest sources of distortion in the various frequency regions. Further, equations that describe the third harmonic as a function of circuit parameters and input frequency are presented. Despite the simplifications, these equations describe the third harmonic accurately. Further, they provide insight and understanding by connecting distortion to circuit parameters such as transconductances, capacitances, poles, and zeros. The comparison of the opamps shows that each opamp has a frequency region where the distortion is lower than for the other two. The three-stage op amp has far lower distortion at low frequencies, the single-stage op amp is better at high frequency and the two-stage op amp is best for the mid frequency range.     

Cascadable Current-Mode Biquads

New procedures are presented that yield cascadable, opamp based current-mode biquads from voltage-mode biquads without the use of voltage-mode to current-mode transformations. The opamps in the resulting current-mode circuits can be replaced by current-mode devices, such as current conveyors, producing circuits that are fully current-mode. The procedures are applied to several multi-opamp voltage-mode circuits to achieve current-mode lowpass, highpass, bandpass, notch, and allpass filters. The procedures are also applied to a single opamp circuit. Experimental results are given.     

Novel output stage for DC gain enhancement of opamp and OTA

A novel output stage for OTAs and opamps for gain enhancement is described. The proposed circuit using positive feedback to cancel the output conductance allows the DC gain to be enhanced without affecting the bandwidth of the OTA and opamp.<>     

实用集成运算放大器宏模型的研究

本文提出了一个新的通用运算放大器（简称运放）宏模型，它几乎能精确地模拟运放的全部特性，其中的等效输入噪声、温度响应和电源电压抑制比等特性的模拟，则是以前发表的同类模型所不具备的。它不仅可模拟大、中、小信号激励的线性或非线性响应，并且对双极型、双极－场效应管混合型和ＭＯＳ型运放都适用。此外，对输入级电流饱和特性也作了精确地模拟；推导出了其频域分析中的解析表达式。     

Four-quadrant analogue multiplier using operational amplifier

A method to realise a four-quadrant analogue multiplier using general-purpose operational amplifiers (opamps) as only the active elements is described in this article. The realisation method is based on the quarter-square technique, which utilises the inherent square-law characteristic of class AB output stage of the opamp. The multiplier can be achieved from the proposed structure with using either bipolar or complementary metal-oxide-semiconductor (CMOS) opamps. The operation principle of the proposed multiplier has been confirmed by PSPICE analogue simulation program. Simulation results reveal that the principle of proposed scheme provides an adequate performance for a four-quadrant analogue multiplier. Experimental implementations of the proposed multiplier using bipolar and CMOS opamps are performed to verify the circuit performances. Measured results of the experimental proposed schemes based on the use of bipolar and CMOS opamps with supply voltage ±2.4 V show the worst-case relative errors of 0.32% and 0.47%, and the total harmonic distortions of 0.47% and 0.98%, respectively.     

A Low-Power Reconfigurable Analog Filter for UMTS/WLAN Receivers

A low-power analog filter able to be reconfigured in order to be used in UMTS and WLAN applications is reported. The 4th order low-pass continuous-time filter is going to be included in the receiver path of a reconfigurable terminal. The filter is made up by the cascade of two Active-G$_m$-RC low-pass biquadratic cells. The unity-gain-bandwidth of the opamps embedded in the Active-G$_m$-RC cells is comparable to the filter cut-off frequency. Thus, the power consumption of the opamp can be strongly reduced. In addition, the filter can be programmed in order to process UMTS and WLAN signals, while a little area overhead is required since the filter can share capacitors as well as opamps in both operations modes. The cut-off frequency deviation due to the technological spread, aging and temperature variation is adjusted by using a tuning circuit.The full device in a 0.13 μ$m CMOS technology occupies a 2.8 mm²area.     

Current-feedback operational amplifier: Some features of its transient radiation response

The behavior is investigated of a current-feedback opamp exposed to pulsed ionizing radiation sufficiently intense to produce voltage surges in the opamp. For a system using such opamps, the possibilities of maintaining normal operation under the stated conditions are explored.     

Linear and nonlinear modeling of switched-capacitor ΔΣ modulators

A new methodology is presented for both linear and nonlinear circuit-level modeling of switched-capacitor ΔΣ modulators. It takes account of the MOSFET parasitic capacitances, switch on-resistances, opamp gain-bandwidth products, the nonlinear behavior of the parasitic capacitances and opamps, clock jitter, etc. Mathematically, a system of circuit equations is constructed by nodal analysis in the frequency domain, and its solutions in the form of Volterra series are mapped into the time domain by numerical Laplace inversion. The methodology can be used for nonlinear-distortion analysis. It is implemented in software within MATLAB.     

Design of an Operational Amplifier Input Stage Immune to EMI

This paper presents a new analytical model to predict upsets, which are induced by electromagnetic interferences (EMI) in CMOS operational amplifiers (opamps). In particular, it is pointed out that the demodulation of EMI, which is experienced in feedback CMOS opamps, is related to the power spectral density of the interfering signals reaching the opamp input terminals. Furthermore, the new model is employed to design a differential stage immune to EMI.     

Failures induced on analog integrated circuits by conveyed electromagnetic interferences: A review

Failures induced on analog integrated circuits by electromagnetic interference (EMI) will be analyzed with particular emphasis on integrated operational amplifiers built with different technologies. Additionally, the correlation found between EMI susceptibility and large-signal opamp behavior will be discussed. Some criteria for the design of low EMI susceptibility opamps will be derived. Finally, as an application example, the design of a BiCMOS opamp with an extremely low-probability EMI-induced failure will be presented.     

A 10-bit 50-MS/s Pipelined ADC With Opamp Current Reuse

Power and area saving concepts such as operational amplifier (opamp) bias current reuse and capacitive level shifting are used to lower the analog power of a 10-bit pipelined analog-to-digital converter (ADC) to 220 muW/MHz. Since a dual-input bias current reusing opamp performs as two opamps, the opamp summing nodes can be reset in every clock cycle. By using only N-channel MOS (NMOS) input stages, the capacitive level shifter simplifies the gain-boosting amplifier design and enables fast opamp settling with low power-consumption. The prototype achieves 9.2/8.8 effective number of bits (ENOB) for 1- and 20-MHz inputs at 50 MS/s. The ADC works within the temperature range of 0deg to 85 degC and the supply voltage from 1.62 to 1.96 V with little measured loss in the ENOB. The chip consumes 18 mW (11 mW for the analog portion of the ADC and 7 mW for the rest including buffers) at 1.8 V, and the active area occupies 1.1 times 1.3 mm² using a 0.18-mum complementary metal oxide semiconductor (CMOS) process     

A low-power reconfigurable analog-to-digital converter

A low-power CMOS reconfigurable analog-to-digital converter that can digitize signals over a wide range of bandwidth and resolution with adaptive power consumption is described. The converter achieves the wide operating range by (1) reconfiguring its architecture between pipeline and delta-sigma modes; (2) varying its circuit parameters, such as size of capacitors, length of pipeline, and oversampling ratio, among others; and (3) varying the bias currents of the opamps in proportion to the converter sampling frequency, accomplished through the use of a phase-locked loop (PLL). This converter also incorporates several power-reducing features such as thermal noise limited design, global converter chopping in the pipeline mode, opamp scaling, opamp sharing between consecutive stages in the pipeline mode, an opamp chopping technique in the delta-sigma mode, and other design techniques. The opamp chopping technique achieves faster closed-loop settling time and lower thermal noise than conventional design. At a converter power supply of 3.3 V, the converter achieves a bandwidth range of 0-10 MHz over a resolution range of 6-16 bits, and parameter reconfiguration time of twelve clock cycles. Its PLL lock range is measured at 20 kHz to 40 MHz. In the delta-sigma mode, it achieves a maximum signal-to-noise ratio of 94 dB and second and third harmonic distortions of 102 and 95 dB, respectively, at 10 MHz clock frequency, 9.4 kHz bandwidth, and 17.6 mW power. In the pipeline mode, it achieves a maximum DNL and INL of ±0.55 LSBs and ±0.82 LSBs, respectively, at 11 bits, at a clock frequency of 2.6 MHz and 1 MHz tone with 24.6 mW of power     

74 dB SNDR Multi-Loop Sturdy-MASH Delta-Sigma Modulator Using 35 dB Open-Loop Opamp Gain

This paper presents a new multi-loop delta-sigma modulator which overcomes the necessity of high DC gain opamps that were needed in previous multi-loop modulators. Enabling the use of low gain opamps also allows low-voltage operation due to the reduced number of transistors between the power supply rails. In addition, all the digital filters are removed from the output of this modulator to minimize the overall system requirement. Instead, an in-loop digital addition facilitates the desired noise transfer functions of both loops. This combines stability advantage of the multi-loop structure with relaxed circuit requirement of the single-loop modulator. A fourth order modulator is implemented in a 0.18 $mu$m CMOS technology to demonstrate this concept. Measurement results show that, with open-loop opamp gain of less than 35 dB, the implemented prototype IC achieves over 74 dB SNDR at an oversampling ratio of 16. The sampling frequency is 20 MHz and the total power dissipation is 3.2 mW at 1.2 V supply.      

A new nonlinear model of EMI-induced distortion phenomena in feedback CMOS operational amplifiers

This paper deals with distortion phenomena induced by radio-frequency interference (RFI) in analog integrated circuits and it concentrates on the effects induced by RFI on the operation of feedback CMOS operational amplifiers (opamps). In particular, the paper describes a new nonlinear model, which makes possible the prediction of upset in the opamp output nominal signal when RFI is superimposed on the input nominal signals. Such a model can be employed when the transistors of the input differential pair are driven by RFI either in strong or weak nonlinear operation. Results of experimental tests performed on a Miller CMOS opamp connected in the voltage follower configuration are presented and compared with model predictions.     

Design of integrated BiCMOS operational amplifiers with low-probability EMI-induced-failures

Electromagnetic interference may cause failures in operational amplifiers. The probability of these failures can be reduced by properly designing the opamp, once the failure mechanism has been discovered. In this paper the design of some integrated BiCMOS operational amplifiers with a very low-probability of electromagnetic interference (EMI) induced failures is reported. In particular, it is shown that opamps exhibiting good general performances as well as low EMI-susceptibility can be obtained only if their response to a large square-wave input signal is symmetric and the influence of some parasitic capacitances in the input stage is compensated. Following these guide-lines, we found possible to design BiCMOS opamp structures exhibiting EMI susceptibility of only a few mV up to several hundred MHz when they are driven with an interfering input signal of some volts.     

Oscillation-Test Technique for CMOS Operational Amplifiers by Monitoring Supply Current

A comparison of the merits and possibilities of considering the output voltage and the negative supply current as test observables when using the Oscillation-test technique is carried out. The method is applied to CMOS opamps considering an exhaustive analysis of catastrophic defects (opens, shorts), GOS and floating gates using HSPICE. We analyze deviations in both frequency and signal amplitude of each observable comparing their sensitivity to defects. Results show that the supply current peak value provides the highest defect coverage for a single opamp oscillator, while the oscillating frequency provides the highest fault coverage for a double opamp oscillator.     

Finite common-mode rejection in fully differential operational amplifiers

A nonlinear mechanism which affects common-mode rejection (CMR) of fully differential integrated operational amplifiers (opamps) is highlighted and analysed by computer simulations. In particular, it is shown how the finite CMR of fully differential opamp circuits under practical operating conditions is mainly related to such a mechanism rather than to transistor mismatch.     

Design of SOI CMOS operational amplifiers for applications up to300°C

Design guidelines using two analog parameters (Early voltage and transconductance to drain current ratio) are proposed for correct operation of silicon-on-insulator (SOI) CMOS operational amplifiers (opamp) at elevated temperature up to 300°C. The dependence of these parameters on temperature is first described. A new single-stage CMOS opamp model using only these two parameters is presented and compared to measurements of several implementations operating up to 300°C for applications such as micropower (below 4 μW at 1.2 V supply voltage), high gain (65 dB) or high frequency up to 100 MHz. Trade-offs among such factors as gain, bandwidth, phase margin, signal swing, noise, matching, slew rate and power consumption are described. The extension to other architectures is suggested and the design methodology is valid for bulk as well as SOI CMOS opamps