Analysis of thin gate oxide degradation during fabrication ofadvanced CMOS ULSI circuits

The electrical characteristics uniquely associated with the thin gate oxide degradation of the advanced CMOS technology in manufacturing were determined for the first time. They were different from Fowler-Nordheim (F-N) stress, and therefore, cannot be simulated by the F-N stress. The p⁺ thin gate oxides were found to be inherently more susceptible to gate oxide degradation than the n⁺ gate oxides. The p⁺ oxide degradation is caused by a combination of the process-induced defect and plasma charging. The nature of the defect and its formation were identified by electrical and physical analysis. The defect formation was modeled. The p-channel gate oxide degradation will be worse with gate oxide scaling, and may limit the device scaling     

The effect of Fowler-Nordheim tunneling current stress on mobilityin n-channel MOSFETs

The electron effective mobility in n-channel MOSFETs has been investigated under Fowler-Nordheim (F-N) tunneling current stress at room temperature. With F-N current stress, mobilities become smaller than of the prestress mobilities over the whole region of inversion carrier density N_inv, and the N_inv -dependence of the mobility almost disappears     

Effects of controlled texturization of the crystalline Si surfaceon the SiO2/Si effective barrier height

A two-stage plasma etch texturination process to control the level of crystalline silicon surface roughness has been investigated. Initially, a Cl₂ plasma etch is used to produce a very rough Si surface. This is followed by an isotropic SF₆ plasma etch, whose etch time is used to reduce and control the level of surface roughness created by the previous step. Oxides grown on texturized Si surfaces with short SF₆ etch times exhibit lower effective SiO₂/Si barrier height and greater electron injection enhancement than those with longer SF₆ etch times     

New Gate CD Control Technology Using CF 4 Plasma Treatment Following HBr/O 2 Plasma Treatment Step in Gate Etch Process Using Organic BARC

A new technology of resist trimming in a gate etch process using organic bottom antireflective coating (BARC) for accurate and stable gate critical dimension (CD) control of sub-0.18-mum node technology is presented in this paper. The new method uses an in situ CF₄ plasma treatment following an HBr/O₂ plasma treatment step as a part of the gate etch process to achieve a stable gate CD. The new method controls gate CD by trimming the photo resist masking gate line by reducing the effect of etch by-products, the source of CD variation, after etching organic BARC with HBr/O₂ plasma. It shows the markedly improved gate CD capability over the conventional one using just an HBr/O₂ plasma treatment for the CD control. We confirm that this new method is very useful and effective for the accurate gate CD control for sub-0.18-mum node metal-oxide semiconductor technology     

Damage to n-MOSFETs from electrical stress Relationship to processing damage and impact on device reliability

The study reported herein examines and compares damage to n-channel and p-channel metal-oxide-silicon field-effect transistors (MOSFETs) from direct current (d.c.) and alternating current (a.c.) electrical stresses as well as the relationship of this damage to plasma processing damage in MOSFETs. The lightly-doped drain (LDD) MOSFETs used are of 0.5 μm channel length and with a 90 Å thick thermally grown gate oxide fabricated using a full flow CMOS process up to and including metal-1 processes and post-metallization annealing (PMA). The damage to MOSFETs is assessed using transistor parameter characterization and charge-to-breakdown measurements on the gate oxide. It is found that manifestations of d.c. stress-induced damage and a.c. stress-induced damage to transistors are fairly similar in that both forms of damage are passivated by PMA and are reactivated by a subsequent d.c. electrical stress. However, a.c. stress-induced damage is observed to occur at much lower electric fields across the gate oxide than those necessary for d.c. stress-induced damage to be significant. This is attributed to a.c. currents, caused by carrier hopping, occurring at relatively low electric fields. One implication of our results is that plasma-charging damage, often attributed to d.c. electrical stress alone, may comprise an a.c. electrical stress component too.     

Implementation of tungsten metallization in multilevelinterconnection technologies

The techniques of experimental design and response-surface methodology have been used to produce empirical models of the deposition and etchback of tungsten in commercially available reactors for a tungsten plug technology. Deposition was carried out in a Genus 8402 LPCVD (low-pressure chemical vapor deposition) batch reactor by the H ₂ reduction of WF₆. Response-surfaces for deposition rate, sheet resistance uniformity, resistivity, and film stress were developed as a function of reactor pressure, reactor temperature, and flow rate of WF₆ at a fixed H₂ flow rate using linear-interactive models. A thin layer of TiN was used to ensure adhesion of tungsten to SiO₂. Etchback of the composite layer of W/TiN to form via plugs was performed in a Tegal 804 single-wafer system with a two-step process using mixtures of SF₆ with C₂F₆ and He with Cl₂ in step 1 and step 2, respectively. Process parameters for both steps were obtained from quadratic models of etch rate and etch uniformity     

Electrical properties of N2O/NH3 plasma grownoxynitride on strained-Si

Growth of ultrathin (<100 Å) oxynitride on strained-Si using microwave N₂O and NH₃ plasma is reported. X-ray photoelectron spectroscopy (XPS) results indicate a nitrogen-rich layer at the strained-Si/SiO₂ interface. The electrical properties of oxynitrides have been characterized using a metal-insulator-semiconductor (MIS) structure. A moderately low value of insulator charge density (6.1×10¹⁰ cm^-2) has been obtained for NH₃ plasma treated N₂O oxide sample. Nitrided oxide shows a larger breakdown voltage and an improved charge trapping properties under Fowler-Nordheim (F-N) constant current stress     

A simple process to produce a high quality silicon surface prior toselective epitaxial growth

A simple and low-cost process was devised to eliminate etch damage resulting from oxide etching on the seed-hole surface prior to selective epitaxial growth (SEG) of silicon. The process consists of a low power C ₂F₆ RIE step which was performed right after the oxide etch step in the same etch reactor. The use of this step excluded the need of a conventional sacrificial oxide to remove damaged silicon regions and residual polymers. The n-p diodes resulting from n-type SEG grown on p-type substrate were used to evaluate the quality of the silicon surface prior to SEG     

Interlevel dielectric via etch process monitoring by atomic forcemicroscopy

The use of AFM for in-line monitoring of an interlevel dielectric via plasma etching step is reported. By comparing etch depths, to via types contacting both Au- and W-based metals, the AFM can non-destructively determine whether micrometre-sized vias have been cleared. Owing to the etch selectivity of the SF₆/O₂ plasma, the Au-based ohmic metal acts as an etch stop whereas the W-based refractory gate contact continues to etch     

Modeling magnetically enhanced RIE of aluminum alloy films usingneural networks

Aluminum (Al) and its alloy films are widely used for fabricating VLSI interconnections. The discharge behavior of a magnetically enhanced reactive ion etching (MERIE) of Al(Si) has been modeled using neural networks. A 2^6-1 fractional factorial experiment was employed to characterize etch variations with RF power, pressure, magnetic field and gas mixtures of Cl₂, BCl₃, and N₂. Responses of an Al(Si) film etched in a chlorine-based plasma include etch rate, selectivity to oxide, anisotropy and bias of critical dimension (CD). The generalization accuracy of the models, measured by the root-mean squared error (RMS) on a test set, are 285 Å/min for etch rate, 5.58 for oxide selectivity, 0.08 for anisotropy, and 3.82 Å/min for CD bias. Al(Si) etch rate was found to be chlorine-dependent with significantly affected by magnetic field variations. For the other etch responses, RF power was dominant. Gas additives such as BCl₃ and N₂ were seen to have conflicting effects on etch outputs. Predicted Al(Si) etch behaviors from neural process models were in qualitative good agreement with reported experimental results     

Deep submicron CMOS based on silicon germanium technology

The advantages to be gained by using SiGe in CMOS technology are examined, Conventional MOSFETs are compared with SiGe heterojunction MOSFETs suitable for CMOS technology and having channel lengths between 0.5 and 0.1 μm. Two-dimensional computer simulation demonstrates that the improved mobility in the SiGe devices, due to higher bulk mobility and the elimination of Si/SiO₂ interface scattering by the inclusion of a capping layer, results in significant velocity overshoot close to the source-end of the channel. The cut-off frequency, f_t , is found to increase by around 50% for n-channel devices while more than doubling for p-channel devices for typical estimates of mobility. The results offer the prospect of a more balanced CMOS and improved circuit speed especially when using dynamic logic     

Thermally and electrically isolated single crystal siliconstructures in CMOS technology

Thermally and electrically isolated single crystal silicon structures have been fabricated using a post-processing anisotropic tetramethyl ammonium hydroxide (TMAH) electrochemical etch. The process was carried out on CMOS circuits fabricated by a commercial foundry. Since the etch consists of a single micromachining step performed on packaged and bonded dice, this technique has the potential for cost-effective prototyping and production of integrated sensors and circuits     

FGA effects on plasma-induced damage: beyond the appearances

Indispensable for manufacturing of modern CMOS technologies, plasma processes result in charging of dielectric surfaces, thus damaging the gate oxide. A forming gas annealing (FGA) step is usually done at the end of the process to passivate and/or recover this damage. We investigated this problem on thin (3.5 nm) gate oxides by using a series of stress-anneal-stress steps on devices with different level of latent damage. Our results confirm that FGA actually reduces the number of traps responsible for stress-induced leakage current (SILC) or for microbreakdown in ultrathin gate oxides, but also put in evidence that defects induced by plasma treatments and those generated by way of electrical stress feature different anneal kinetics. Further, we have identified two categories of dielectric breakdown events, whose characteristics are strongly modified by the FGA step.     

A gate-charging model for ILD related plasma processes in MOSFETs

A model explaining gate-charging damage in MOSFETs observed during inter-layer-dielectric (ILD)-related plasma processes is reported. It indicates that the charging damage associated with the ILD plasma process can be related to the effect of photoconduction and/or capacitive impedance coupling of plasma potential through the multiple ILD layers. The model leads to a conclusion that by placing a larger-area lower-layer metal (such as Metal-1) plate or polysilicon plate at the gate terminal of MOSFETs, this ILD process-related charging damage can be eliminated or significantly reduced due to a substantial reduction in the gate-to-substrate impedance of the transistors.     

An 0.18-μm CMOS for mixed digital and analog applications withzero-volt-Vth epitaxial-channel MOSFETs

An 0.18-μm CMOS technology with multi-V_ths for mixed high-speed digital and RF-analog applications has been developed. The V _ths of MOSFETs for digital circuits are 0.4 V for NMOS and -0.4 V for PMOS, respectively. In addition, there are n-MOSFET's with zero-volt-V_th for RF analog circuits. The zero-volt-V_th MOSFETs were made by using undoped epitaxial layer for the channel regions. Though the epitaxial film was grown by reduced pressure chemical vapor deposition (RP-CVD) at 750°C, the film quality is as good as the bulk silicon because high pre-heating temperature (940°C for 30 s) is used in H₂ atmosphere before the epitaxial growth. The epitaxial channel MOSFET shows higher peak g_m and f_T values than those of bulk cases. Furthermore, the g_m and f_T values of the epitaxial channel MOSFET show significantly improved performances under the lower supply voltage compared with those of bulk. This is very important for RF analog application for low supply voltage. The undoped-epitaxial-channel MOSFETs with zero-V_th will become a key to realize high-performance and low-power CMOS devices for mixed digital and RF-analog applications     

Development of an etchant for selectively etching TiWNxin the presence of electroplated 95%Pb-5%Sn solder

Shrinking die sizes and increasing I/O density is motivating the push toward flip chip packages. A flip chip interconnection system with a under bump metallurgy stack containing sputtered TiWN_X/sputtered Cu/electroplated Cu stud/electroplated 95%Pb-5%Sn was developed. An important step in the above process is the selective etching of the sputtered Cu bus layer and the TiWN_X barrier layer, in the presence of the Pb-Sn solder. The Cu bus layer was selectively etched using commercial etchants. However, no commercial etchants were available for selectively etching the TiWN_X layer, H₂O₂-NH₄OH based etching systems, popularly known as Standard Clean-1 cleaning solutions, have been extensively used to clean silicon wafers in front end wafer fabrication where only trace metal contamination exists. Since metals like lead, copper, titanium, tin and tungsten catalyze the heterogeneous decomposition of the peroxide, the unstable H₂O₂-NH₄OH based etching systems are rarely used to etch metal films. In this paper the development of a H ₂O₂-NH₄OH based etchant to selectively etch the sputtered TiWN_X films in the presence of electroplated 95%Pb-5%Sn solder bumps is discussed. A 2³ full factorial experiment with mid point was conducted to establish the etchant composition, as well as process temperature, that give satisfactory responses with respect to etch time, permissable undercut of the Cu stud (caused by the NH₄OH), and acceptable bump shape after reflow. Statistical analysis was used to understand the significant factors influencing the etch rate and undercut. An etchant containing 6% by volume of 30%-H₂O₂ and 0.75% by volume of 30%-NH₄OH operated at a temperature of 37°C was found to give satisfactory results     

LDD MOSFETs using disposable sidewall spacer technology

A technology for fabricating lightly doped drain (LDD) MOSFET devices based on disposable sidewall spacers is presented. Using a thin polysilicon buffer layer between the low-temperature oxide (LTO) sidewall spacers and the oxidized polysilicon gate, a single masking step can be used to form the n^- and n⁺ or p^- and p⁺ source/drain implants for the NMOS and PMOS devices, respectively. In addition, the LTO sidewall spacers may be removed by a wet HF strip, thus minimizing additional damage to the gate oxide that may be caused by reactive ion etch removal. The disposable sidewall spacer technology is easily adaptable to a CMOS process as demonstrated by the fabrication of a 4 K×4 SRAM circuit using a conventional 1.5-μ CMOS technology     

A New Technique for Measuring Gate-Oxide Leakage in Charging Protected MOSFETs

While accurate measurement of gate-oxide leakage in isolated CMOS oxides can be straightforward, it is not the case for CMOS oxides connected to a plasma-charging protection device. In this paper, a method enabling accurate gate-oxide leakage extraction from CMOS transistors directly connected to a gated MOSFET-based charging protection device is described. The method extracts gate-oxide leakage at the bottom side of the gate-oxide from the drain/source terminal of the protected MOSFETs biased into inversion while diverting the parasitic leakages from the protection device into a P⁺ tap sink. The location and design of the P⁺ tap sink play an important role on the success of the method. The method demonstrates a high measurement accuracy over the conventional method with a nearly 99% absorption efficiency of the protection-device-induced leakage by the P ⁺ tap sink, with the test structures used in this study. The method enables a saving of up to 30% of the layout space in the design of the charging test structures in test chips by eliminating usage of the fuse between the protected and protecting devices. A correlation study performed with the data measured by the new method and the conventional method suggests that both protected and protecting transistors can experience gate-oxide damage at the same time during back-end integrated circuit (IC) manufacturing process if the protected transistors violate the gate-charging design rules. It also indicates that the protected transistors have higher chance to receive more severe damage than the protecting transistors due to different oxide damage mechanisms associated with the terminal connectivity of these transistors     

Low-pressure rapid thermal chemical vapor deposition of oxynitridegate dielectrics for n-channel and p-channel MOSFETs

The properties of oxynitride gate dielectrics formed using a low-pressure, rapid thermal chemical vapor deposition (RTCVD) process with SiH₄, NH₃, and N₂O as the reactive gases are presented. Material analyses show an increase of uniform nitrogen and interfacial hydrogen content with increasing NH₃/N₂O flow rate ratio. MOS capacitors with both n-type and p-type substrates and both n-channel and p-channel MOSFETs were analyzed electrically. The results show increasing fixed oxide charge and interface state density with increasing nitrogen and hydrogen content in the film. A decrease in peak transconductance and improved high-field transconductance was observed for n-channel MOSFETs. Improved resistance to hot-carrier interface state generation was also observed with increasing nitrogen concentration in the films. The results suggest that an optimal nitrogen concentration of approximately 3 at.% can be considered for further development of this technology     

Plasma Etching for Sub-45-nm TaN Metal Gates on High-k Dielectrics

Etching of TaN gates on high-k dielectrics (HfO₂ or HfAlO) is investigated using HBr/Cl₂ chemistry in a decoupled plasma source (DPS). The patterning sequence includes 248-nm lithography, plasma photoresist trimming, etching of a SiN-SiO₂ hard mask, and photoresist stripping, followed by TaN etching. TaN etching is studied by design of experiment (DOE) with four variables using a linear model with interactions. It is found that at a fixed substrate temperature and wafer chuck power, etch critical dimensions (CD) gain decreases with decreasing HBr/Cl₂ flow rate ratio and pressure and with increasing source power and total gas flow rate. Based on these DOE findings, subsequent optimization is performed and a three-step etching process is developed; a main feature of the process is progressively increasing HBr/Cl₂ flow rate ratio. The optimized process provides etch CD gain within 2 nm and gate profile close to vertical and reliable etch-stop on high-k dielectric. This process is successfully applied to the fabrication of the 40-nm HfAlO/TaN gate stack p-MOSFETs with good electrical parameters